asc_vsbus.c revision 1.24
1 /* $NetBSD: asc_vsbus.c,v 1.24 2001/05/16 05:36:56 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_cputype.h" 40 41 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 42 43 __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.24 2001/05/16 05:36:56 matt Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/reboot.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/bus.h> 64 #include <machine/vmparam.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <machine/cpu.h> 70 #include <machine/sid.h> 71 #include <machine/scb.h> 72 #include <machine/vsbus.h> 73 #include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 74 75 struct asc_vsbus_softc { 76 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 77 struct evcnt sc_intrcnt; /* count interrupts */ 78 bus_space_tag_t sc_bst; /* bus space tag */ 79 bus_space_handle_t sc_bsh; /* bus space handle */ 80 bus_space_handle_t sc_dirh; /* scsi direction handle */ 81 bus_space_handle_t sc_adrh; /* scsi address handle */ 82 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 83 bus_dma_tag_t sc_dmat; /* bus dma tag */ 84 bus_dmamap_t sc_dmamap; 85 caddr_t *sc_dmaaddr; 86 size_t *sc_dmalen; 87 size_t sc_dmasize; 88 unsigned int sc_flags; 89 #define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 90 #define ASC_DMAACTIVE 0x0002 91 #define ASC_MAPLOADED 0x0004 92 unsigned long sc_xfers; 93 }; 94 95 #define ASC_REG_KA46_ADR 0x0000 96 #define ASC_REG_KA46_DIR 0x000C 97 #define ASC_REG_KA49_ADR 0x0000 98 #define ASC_REG_KA49_DIR 0x0004 99 #define ASC_REG_NCR 0x0080 100 #define ASC_REG_END 0x00B0 101 102 #define ASC_MAXXFERSIZE 65536 103 #define ASC_FREQUENCY 25000000 104 105 static int asc_vsbus_match(struct device *, struct cfdata *, void *); 106 static void asc_vsbus_attach(struct device *, struct device *, void *); 107 108 struct cfattach asc_vsbus_ca = { 109 sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach 110 }; 111 112 /* 113 * Functions and the switch for the MI code 114 */ 115 static u_char asc_vsbus_read_reg(struct ncr53c9x_softc *, int); 116 static void asc_vsbus_write_reg(struct ncr53c9x_softc *, int, u_char); 117 static int asc_vsbus_dma_isintr(struct ncr53c9x_softc *); 118 static void asc_vsbus_dma_reset(struct ncr53c9x_softc *); 119 static int asc_vsbus_dma_intr(struct ncr53c9x_softc *); 120 static int asc_vsbus_dma_setup(struct ncr53c9x_softc *, caddr_t *, 121 size_t *, int, size_t *); 122 static void asc_vsbus_dma_go(struct ncr53c9x_softc *); 123 static void asc_vsbus_dma_stop(struct ncr53c9x_softc *); 124 static int asc_vsbus_dma_isactive(struct ncr53c9x_softc *); 125 126 static struct ncr53c9x_glue asc_vsbus_glue = { 127 asc_vsbus_read_reg, 128 asc_vsbus_write_reg, 129 asc_vsbus_dma_isintr, 130 asc_vsbus_dma_reset, 131 asc_vsbus_dma_intr, 132 asc_vsbus_dma_setup, 133 asc_vsbus_dma_go, 134 asc_vsbus_dma_stop, 135 asc_vsbus_dma_isactive, 136 NULL, 137 }; 138 139 static u_int8_t asc_attached; /* can't have more than one asc */ 140 141 static int 142 asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 143 { 144 struct vsbus_attach_args *va = aux; 145 volatile u_int8_t *ncr_regs; 146 int dummy; 147 148 if (asc_attached) 149 return 0; 150 151 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 152 if (cf->cf_loc[0] != 0x200c0080) 153 return 0; 154 } else if (vax_boardtype == VAX_BTYP_49 || 155 vax_boardtype == VAX_BTYP_53) { 156 if (cf->cf_loc[0] != 0x26000080) 157 return 0; 158 } else { 159 return 0; 160 } 161 162 ncr_regs = (volatile u_int8_t *) va->va_addr; 163 164 /* *** need to generate an interrupt here 165 * From trial and error, I've determined that an INT is generated 166 * only when the following sequence of events occurs: 167 * 1) The interrupt status register (0x05) must be read. 168 * 2) SCSI bus reset interrupt must be enabled 169 * 3) SCSI bus reset command must be sent 170 * 4) NOP command must be sent 171 */ 172 173 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 174 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 175 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 176 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 177 DELAY(10000); 178 179 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 180 return (dummy & NCRINTR_SBR) != 0; 181 } 182 183 184 /* 185 * Attach this instance, and then all the sub-devices 186 */ 187 static void 188 asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 189 { 190 struct vsbus_attach_args *va = aux; 191 struct asc_vsbus_softc *asc = (void *)self; 192 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 193 int error; 194 195 asc_attached = 1; 196 /* 197 * Set up glue for MI code early; we use some of it here. 198 */ 199 sc->sc_glue = &asc_vsbus_glue; 200 201 asc->sc_bst = va->va_iot; 202 asc->sc_dmat = va->va_dmat; 203 204 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 205 ASC_REG_END, 0, &asc->sc_bsh); 206 if (error) { 207 printf(": failed to map registers: error=%d\n", error); 208 return; 209 } 210 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 211 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 212 if (error) { 213 printf(": failed to map ncr registers: error=%d\n", error); 214 return; 215 } 216 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 217 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 218 ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh); 219 if (error) { 220 printf(": failed to map adr register: error=%d\n", 221 error); 222 return; 223 } 224 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 225 ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh); 226 if (error) { 227 printf(": failed to map dir register: error=%d\n", 228 error); 229 return; 230 } 231 } else { 232 /* This is a gross and disgusting kludge but it'll 233 * save a bunch of ugly code. Unlike the VS4000/60, 234 * the SCSI Address and direction registers are not 235 * near the SCSI NCR registers and are inside the 236 * block of general VAXstation registers. So we grab 237 * them from there and knowing the internals of the 238 * bus_space implementation, we cast to bus_space_handles. 239 */ 240 struct vsbus_softc *vsc = (struct vsbus_softc *) parent; 241 asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR); 242 asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR); 243 #if 0 244 printf("\n%s: adrh=0x%08lx dirh=0x%08lx", self->dv_xname, 245 asc->sc_adrh, asc->sc_dirh); 246 ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS; 247 #endif 248 } 249 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 250 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 251 252 switch (vax_boardtype) { 253 #if VAX46 || VAXANY 254 case VAX_BTYP_46: 255 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 256 break; 257 #endif 258 default: 259 sc->sc_id = 6; /* XXX need to get this from VMB */ 260 break; 261 } 262 263 sc->sc_freq = ASC_FREQUENCY; 264 265 /* gimme Mhz */ 266 sc->sc_freq /= 1000000; 267 268 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 269 &asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt); 270 evcnt_attach_dynamic(&asc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 271 self->dv_xname, "intr"); 272 273 /* 274 * XXX More of this should be in ncr53c9x_attach(), but 275 * XXX should we really poke around the chip that much in 276 * XXX the MI code? Think about this more... 277 */ 278 279 /* 280 * Set up static configuration info. 281 */ 282 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 283 sc->sc_cfg2 = NCRCFG2_SCSI2; 284 sc->sc_cfg3 = 0; 285 sc->sc_rev = NCR_VARIANT_NCR53C94; 286 287 /* 288 * XXX minsync and maxxfer _should_ be set up in MI code, 289 * XXX but it appears to have some dependency on what sort 290 * XXX of DMA we're hooked up to, etc. 291 */ 292 293 /* 294 * This is the value used to start sync negotiations 295 * Note that the NCR register "SYNCTP" is programmed 296 * in "clocks per byte", and has a minimum value of 4. 297 * The SCSI period used in negotiation is one-fourth 298 * of the time (in nanoseconds) needed to transfer one byte. 299 * Since the chip's clock is given in MHz, we have the following 300 * formula: 4 * period = (1000 / freq) * 4 301 */ 302 sc->sc_minsync = (1000 / sc->sc_freq); 303 sc->sc_maxxfer = 63 * 1024; 304 305 printf("\n%s", self->dv_xname); /* Pretty print */ 306 307 /* Do the common parts of attachment. */ 308 sc->sc_adapter.adapt_minphys = minphys; 309 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 310 ncr53c9x_attach(sc); 311 } 312 313 /* 314 * Glue functions. 315 */ 316 317 static u_char 318 asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 319 { 320 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 321 322 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 323 reg * sizeof(u_int32_t)); 324 } 325 326 static void 327 asc_vsbus_write_reg(sc, reg, val) 328 struct ncr53c9x_softc *sc; 329 int reg; 330 u_char val; 331 { 332 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 333 334 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 335 reg * sizeof(u_int32_t), val); 336 } 337 338 static int 339 asc_vsbus_dma_isintr(sc) 340 struct ncr53c9x_softc *sc; 341 { 342 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 343 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 344 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 345 } 346 347 static void 348 asc_vsbus_dma_reset(sc) 349 struct ncr53c9x_softc *sc; 350 { 351 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 352 353 if (asc->sc_flags & ASC_MAPLOADED) 354 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 355 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 356 } 357 358 static int 359 asc_vsbus_dma_intr(sc) 360 struct ncr53c9x_softc *sc; 361 { 362 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 363 u_int tcl, tcm; 364 int trans, resid; 365 366 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 367 panic("asc_vsbus_dma_intr: DMA wasn't active"); 368 369 asc->sc_flags &= ~ASC_DMAACTIVE; 370 371 if (asc->sc_dmasize == 0) { 372 /* A "Transfer Pad" operation completed */ 373 tcl = NCR_READ_REG(sc, NCR_TCL); 374 tcm = NCR_READ_REG(sc, NCR_TCM); 375 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 376 tcl | (tcm << 8), tcl, tcm)); 377 return 0; 378 } 379 380 resid = 0; 381 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 382 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 383 DELAY(1); 384 } 385 if (asc->sc_flags & ASC_MAPLOADED) { 386 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 387 0, asc->sc_dmasize, 388 asc->sc_flags & ASC_FROMMEMORY 389 ? BUS_DMASYNC_POSTWRITE 390 : BUS_DMASYNC_POSTREAD); 391 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 392 } 393 asc->sc_flags &= ~ASC_MAPLOADED; 394 395 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 396 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 397 398 trans = asc->sc_dmasize - resid; 399 if (trans < 0) { /* transferred < 0 ? */ 400 printf("asc_vsbus_intr: xfer (%d) > req (%lu)\n", 401 trans, (u_long) asc->sc_dmasize); 402 trans = asc->sc_dmasize; 403 } 404 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 405 tcl, tcm, trans, resid)); 406 407 *asc->sc_dmalen -= trans; 408 *asc->sc_dmaaddr += trans; 409 410 asc->sc_xfers++; 411 return 0; 412 } 413 414 static int 415 asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 416 int datain, size_t *dmasize) 417 { 418 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 419 420 asc->sc_dmaaddr = addr; 421 asc->sc_dmalen = len; 422 if (datain) { 423 asc->sc_flags &= ~ASC_FROMMEMORY; 424 } else { 425 asc->sc_flags |= ASC_FROMMEMORY; 426 } 427 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 428 panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel", 429 *asc->sc_dmaaddr); 430 431 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 432 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 433 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 434 435 if (asc->sc_dmasize) { 436 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 437 *asc->sc_dmaaddr, asc->sc_dmasize, 438 NULL /* kernel address */, 439 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 440 panic("%s: cannot load dma map", sc->sc_dev.dv_xname); 441 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 442 0, asc->sc_dmasize, 443 asc->sc_flags & ASC_FROMMEMORY 444 ? BUS_DMASYNC_PREWRITE 445 : BUS_DMASYNC_PREREAD); 446 bus_space_write_4(asc->sc_bst, asc->sc_adrh, 0, 447 asc->sc_dmamap->dm_segs[0].ds_addr); 448 bus_space_write_4(asc->sc_bst, asc->sc_dirh, 0, 449 asc->sc_flags & ASC_FROMMEMORY); 450 NCR_DMA(("%s: dma-load %lu@0x%08lx\n", sc->sc_dev.dv_xname, 451 asc->sc_dmamap->dm_segs[0].ds_len, 452 asc->sc_dmamap->dm_segs[0].ds_addr)); 453 asc->sc_flags |= ASC_MAPLOADED; 454 } 455 456 return 0; 457 } 458 459 static void 460 asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 461 { 462 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 463 464 asc->sc_flags |= ASC_DMAACTIVE; 465 } 466 467 static void 468 asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 469 { 470 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 471 472 if (asc->sc_flags & ASC_MAPLOADED) { 473 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 474 0, asc->sc_dmasize, 475 asc->sc_flags & ASC_FROMMEMORY 476 ? BUS_DMASYNC_POSTWRITE 477 : BUS_DMASYNC_POSTREAD); 478 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 479 } 480 481 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 482 } 483 484 static int 485 asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 486 { 487 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 488 489 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 490 } 491
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