asc_vsbus.c revision 1.29
1 /* $NetBSD: asc_vsbus.c,v 1.29 2003/05/03 18:11:06 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_cputype.h" 40 41 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 42 43 __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.29 2003/05/03 18:11:06 wiz Exp $"); 44 45 #include <sys/types.h> 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/errno.h> 50 #include <sys/ioctl.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/reboot.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/bus.h> 64 #include <machine/vmparam.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <machine/cpu.h> 70 #include <machine/sid.h> 71 #include <machine/scb.h> 72 #include <machine/vsbus.h> 73 #include <machine/clock.h> /* for SCSI ctlr ID# XXX */ 74 75 struct asc_vsbus_softc { 76 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 77 struct evcnt sc_intrcnt; /* count interrupts */ 78 bus_space_tag_t sc_bst; /* bus space tag */ 79 bus_space_handle_t sc_bsh; /* bus space handle */ 80 bus_space_handle_t sc_dirh; /* scsi direction handle */ 81 bus_space_handle_t sc_adrh; /* scsi address handle */ 82 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 83 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 84 bus_dmamap_t sc_dmamap; 85 caddr_t *sc_dmaaddr; 86 size_t *sc_dmalen; 87 size_t sc_dmasize; 88 unsigned int sc_flags; 89 #define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 90 #define ASC_DMAACTIVE 0x0002 91 #define ASC_MAPLOADED 0x0004 92 unsigned long sc_xfers; 93 }; 94 95 #define ASC_REG_KA46_ADR 0x0000 96 #define ASC_REG_KA46_DIR 0x000C 97 #define ASC_REG_KA49_ADR 0x0000 98 #define ASC_REG_KA49_DIR 0x0004 99 #define ASC_REG_NCR 0x0080 100 #define ASC_REG_END 0x00B0 101 102 #define ASC_MAXXFERSIZE 65536 103 #define ASC_FREQUENCY 25000000 104 105 static int asc_vsbus_match(struct device *, struct cfdata *, void *); 106 static void asc_vsbus_attach(struct device *, struct device *, void *); 107 108 CFATTACH_DECL(asc_vsbus, sizeof(struct asc_vsbus_softc), 109 asc_vsbus_match, asc_vsbus_attach, NULL, NULL); 110 111 /* 112 * Functions and the switch for the MI code 113 */ 114 static u_char asc_vsbus_read_reg(struct ncr53c9x_softc *, int); 115 static void asc_vsbus_write_reg(struct ncr53c9x_softc *, int, u_char); 116 static int asc_vsbus_dma_isintr(struct ncr53c9x_softc *); 117 static void asc_vsbus_dma_reset(struct ncr53c9x_softc *); 118 static int asc_vsbus_dma_intr(struct ncr53c9x_softc *); 119 static int asc_vsbus_dma_setup(struct ncr53c9x_softc *, caddr_t *, 120 size_t *, int, size_t *); 121 static void asc_vsbus_dma_go(struct ncr53c9x_softc *); 122 static void asc_vsbus_dma_stop(struct ncr53c9x_softc *); 123 static int asc_vsbus_dma_isactive(struct ncr53c9x_softc *); 124 125 static struct ncr53c9x_glue asc_vsbus_glue = { 126 asc_vsbus_read_reg, 127 asc_vsbus_write_reg, 128 asc_vsbus_dma_isintr, 129 asc_vsbus_dma_reset, 130 asc_vsbus_dma_intr, 131 asc_vsbus_dma_setup, 132 asc_vsbus_dma_go, 133 asc_vsbus_dma_stop, 134 asc_vsbus_dma_isactive, 135 NULL, 136 }; 137 138 static u_int8_t asc_attached; /* can't have more than one asc */ 139 140 static int 141 asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 142 { 143 struct vsbus_attach_args *va = aux; 144 volatile u_int8_t *ncr_regs; 145 int dummy; 146 147 if (asc_attached) 148 return 0; 149 150 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 151 if (cf->cf_loc[0] != 0x200c0080) 152 return 0; 153 } else if (vax_boardtype == VAX_BTYP_49 || 154 vax_boardtype == VAX_BTYP_53) { 155 if (cf->cf_loc[0] != 0x26000080) 156 return 0; 157 } else { 158 return 0; 159 } 160 161 ncr_regs = (volatile u_int8_t *) va->va_addr; 162 163 /* *** need to generate an interrupt here 164 * From trial and error, I've determined that an INT is generated 165 * only when the following sequence of events occurs: 166 * 1) The interrupt status register (0x05) must be read. 167 * 2) SCSI bus reset interrupt must be enabled 168 * 3) SCSI bus reset command must be sent 169 * 4) NOP command must be sent 170 */ 171 172 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 173 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 174 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 175 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 176 DELAY(10000); 177 178 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 179 return (dummy & NCRINTR_SBR) != 0; 180 } 181 182 183 /* 184 * Attach this instance, and then all the sub-devices 185 */ 186 static void 187 asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 188 { 189 struct vsbus_attach_args *va = aux; 190 struct asc_vsbus_softc *asc = (void *)self; 191 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 192 int error; 193 194 asc_attached = 1; 195 /* 196 * Set up glue for MI code early; we use some of it here. 197 */ 198 sc->sc_glue = &asc_vsbus_glue; 199 200 asc->sc_bst = va->va_iot; 201 asc->sc_dmat = va->va_dmat; 202 203 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 204 ASC_REG_END, 0, &asc->sc_bsh); 205 if (error) { 206 printf(": failed to map registers: error=%d\n", error); 207 return; 208 } 209 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 210 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 211 if (error) { 212 printf(": failed to map ncr registers: error=%d\n", error); 213 return; 214 } 215 if (vax_boardtype == VAX_BTYP_46 || vax_boardtype == VAX_BTYP_48) { 216 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 217 ASC_REG_KA46_ADR, sizeof(u_int32_t), &asc->sc_adrh); 218 if (error) { 219 printf(": failed to map adr register: error=%d\n", 220 error); 221 return; 222 } 223 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, 224 ASC_REG_KA46_DIR, sizeof(u_int32_t), &asc->sc_dirh); 225 if (error) { 226 printf(": failed to map dir register: error=%d\n", 227 error); 228 return; 229 } 230 } else { 231 /* This is a gross and disgusting kludge but it'll 232 * save a bunch of ugly code. Unlike the VS4000/60, 233 * the SCSI Address and direction registers are not 234 * near the SCSI NCR registers and are inside the 235 * block of general VAXstation registers. So we grab 236 * them from there and knowing the internals of the 237 * bus_space implementation, we cast to bus_space_handles. 238 */ 239 struct vsbus_softc *vsc = (struct vsbus_softc *) parent; 240 asc->sc_adrh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_ADR); 241 asc->sc_dirh = (bus_space_handle_t) (vsc->sc_vsregs + ASC_REG_KA49_DIR); 242 #if 0 243 printf("\n%s: adrh=0x%08lx dirh=0x%08lx", self->dv_xname, 244 asc->sc_adrh, asc->sc_dirh); 245 ncr53c9x_debug = NCR_SHOWDMA|NCR_SHOWINTS|NCR_SHOWCMDS|NCR_SHOWPHASE|NCR_SHOWSTART|NCR_SHOWMSGS; 246 #endif 247 } 248 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 249 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 250 251 switch (vax_boardtype) { 252 #if VAX46 || VAXANY 253 case VAX_BTYP_46: 254 sc->sc_id = (clk_page[0xbc/2] >> clk_tweak) & 7; 255 break; 256 #endif 257 default: 258 sc->sc_id = 6; /* XXX need to get this from VMB */ 259 break; 260 } 261 262 sc->sc_freq = ASC_FREQUENCY; 263 264 /* gimme Mhz */ 265 sc->sc_freq /= 1000000; 266 267 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 268 &asc->sc_ncr53c9x, SCB_ISTACK, &asc->sc_intrcnt); 269 evcnt_attach_dynamic(&asc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 270 self->dv_xname, "intr"); 271 272 /* 273 * XXX More of this should be in ncr53c9x_attach(), but 274 * XXX should we really poke around the chip that much in 275 * XXX the MI code? Think about this more... 276 */ 277 278 /* 279 * Set up static configuration info. 280 */ 281 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 282 sc->sc_cfg2 = NCRCFG2_SCSI2; 283 sc->sc_cfg3 = 0; 284 sc->sc_rev = NCR_VARIANT_NCR53C94; 285 286 /* 287 * XXX minsync and maxxfer _should_ be set up in MI code, 288 * XXX but it appears to have some dependency on what sort 289 * XXX of DMA we're hooked up to, etc. 290 */ 291 292 /* 293 * This is the value used to start sync negotiations 294 * Note that the NCR register "SYNCTP" is programmed 295 * in "clocks per byte", and has a minimum value of 4. 296 * The SCSI period used in negotiation is one-fourth 297 * of the time (in nanoseconds) needed to transfer one byte. 298 * Since the chip's clock is given in MHz, we have the following 299 * formula: 4 * period = (1000 / freq) * 4 300 */ 301 sc->sc_minsync = (1000 / sc->sc_freq); 302 sc->sc_maxxfer = 64 * 1024; 303 304 printf("\n%s", self->dv_xname); /* Pretty print */ 305 306 /* Do the common parts of attachment. */ 307 sc->sc_adapter.adapt_minphys = minphys; 308 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 309 ncr53c9x_attach(sc); 310 } 311 312 /* 313 * Glue functions. 314 */ 315 316 static u_char 317 asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 318 { 319 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 320 321 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 322 reg * sizeof(u_int32_t)); 323 } 324 325 static void 326 asc_vsbus_write_reg(sc, reg, val) 327 struct ncr53c9x_softc *sc; 328 int reg; 329 u_char val; 330 { 331 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 332 333 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 334 reg * sizeof(u_int32_t), val); 335 } 336 337 static int 338 asc_vsbus_dma_isintr(sc) 339 struct ncr53c9x_softc *sc; 340 { 341 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 342 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 343 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 344 } 345 346 static void 347 asc_vsbus_dma_reset(sc) 348 struct ncr53c9x_softc *sc; 349 { 350 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 351 352 if (asc->sc_flags & ASC_MAPLOADED) 353 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 354 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 355 } 356 357 static int 358 asc_vsbus_dma_intr(sc) 359 struct ncr53c9x_softc *sc; 360 { 361 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 362 u_int tcl, tcm; 363 int trans, resid; 364 365 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 366 panic("asc_vsbus_dma_intr: DMA wasn't active"); 367 368 asc->sc_flags &= ~ASC_DMAACTIVE; 369 370 if (asc->sc_dmasize == 0) { 371 /* A "Transfer Pad" operation completed */ 372 tcl = NCR_READ_REG(sc, NCR_TCL); 373 tcm = NCR_READ_REG(sc, NCR_TCM); 374 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 375 tcl | (tcm << 8), tcl, tcm)); 376 return 0; 377 } 378 379 resid = 0; 380 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 381 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 382 DELAY(1); 383 } 384 if (asc->sc_flags & ASC_MAPLOADED) { 385 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 386 0, asc->sc_dmasize, 387 asc->sc_flags & ASC_FROMMEMORY 388 ? BUS_DMASYNC_POSTWRITE 389 : BUS_DMASYNC_POSTREAD); 390 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 391 } 392 asc->sc_flags &= ~ASC_MAPLOADED; 393 394 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 395 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 396 397 trans = asc->sc_dmasize - resid; 398 if (trans < 0) { /* transferred < 0 ? */ 399 printf("asc_vsbus_intr: xfer (%d) > req (%lu)\n", 400 trans, (u_long) asc->sc_dmasize); 401 trans = asc->sc_dmasize; 402 } 403 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 404 tcl, tcm, trans, resid)); 405 406 *asc->sc_dmalen -= trans; 407 *asc->sc_dmaaddr += trans; 408 409 asc->sc_xfers++; 410 return 0; 411 } 412 413 static int 414 asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 415 int datain, size_t *dmasize) 416 { 417 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 418 419 asc->sc_dmaaddr = addr; 420 asc->sc_dmalen = len; 421 if (datain) { 422 asc->sc_flags &= ~ASC_FROMMEMORY; 423 } else { 424 asc->sc_flags |= ASC_FROMMEMORY; 425 } 426 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 427 panic("asc_vsbus_dma_setup: DMA address (%p) outside of kernel", 428 *asc->sc_dmaaddr); 429 430 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 431 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 432 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 433 434 if (asc->sc_dmasize) { 435 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 436 *asc->sc_dmaaddr, asc->sc_dmasize, 437 NULL /* kernel address */, 438 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 439 panic("%s: cannot load DMA map", sc->sc_dev.dv_xname); 440 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 441 0, asc->sc_dmasize, 442 asc->sc_flags & ASC_FROMMEMORY 443 ? BUS_DMASYNC_PREWRITE 444 : BUS_DMASYNC_PREREAD); 445 bus_space_write_4(asc->sc_bst, asc->sc_adrh, 0, 446 asc->sc_dmamap->dm_segs[0].ds_addr); 447 bus_space_write_4(asc->sc_bst, asc->sc_dirh, 0, 448 asc->sc_flags & ASC_FROMMEMORY); 449 NCR_DMA(("%s: dma-load %lu@0x%08lx\n", sc->sc_dev.dv_xname, 450 asc->sc_dmamap->dm_segs[0].ds_len, 451 asc->sc_dmamap->dm_segs[0].ds_addr)); 452 asc->sc_flags |= ASC_MAPLOADED; 453 } 454 455 return 0; 456 } 457 458 static void 459 asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 460 { 461 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 462 463 asc->sc_flags |= ASC_DMAACTIVE; 464 } 465 466 static void 467 asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 468 { 469 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 470 471 if (asc->sc_flags & ASC_MAPLOADED) { 472 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 473 0, asc->sc_dmasize, 474 asc->sc_flags & ASC_FROMMEMORY 475 ? BUS_DMASYNC_POSTWRITE 476 : BUS_DMASYNC_POSTREAD); 477 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 478 } 479 480 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 481 } 482 483 static int 484 asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 485 { 486 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 487 488 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 489 } 490
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