asc_vsbus.c revision 1.8
1 /* $NetBSD: asc_vsbus.c,v 1.8 2000/04/17 16:30:40 ragge Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 41 __KERNEL_RCSID(0, "$NetBSD: asc_vsbus.c,v 1.8 2000/04/17 16:30:40 ragge Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/errno.h> 48 #include <sys/ioctl.h> 49 #include <sys/device.h> 50 #include <sys/buf.h> 51 #include <sys/proc.h> 52 #include <sys/user.h> 53 #include <sys/reboot.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/bus.h> 62 #include <machine/vmparam.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <machine/cpu.h> 68 #include <machine/sid.h> 69 #include <machine/rpb.h> 70 #include <machine/scb.h> 71 #include <machine/vsbus.h> 72 73 struct asc_vsbus_softc { 74 struct ncr53c9x_softc sc_ncr53c9x; /* Must be first */ 75 bus_space_tag_t sc_bst; /* bus space tag */ 76 bus_space_handle_t sc_bsh; /* bus space handle */ 77 bus_space_handle_t sc_ncrh; /* ncr bus space handle */ 78 bus_dma_tag_t sc_dmat; /* bus dma tag */ 79 bus_dmamap_t sc_dmamap; 80 caddr_t *sc_dmaaddr; 81 size_t *sc_dmalen; 82 size_t sc_dmasize; 83 unsigned int sc_flags; 84 #define ASC_FROMMEMORY 0x0001 /* Must be 1 */ 85 #define ASC_DMAACTIVE 0x0002 86 #define ASC_MAPLOADED 0x0004 87 unsigned long sc_xfers; 88 }; 89 90 #define ASC_REG_ADR 0x0000 91 #define ASC_REG_DIR 0x000C 92 #define ASC_REG_NCR 0x0080 93 #define ASC_REG_END 0x00B0 94 95 #define ASC_MAXXFERSIZE 65536 96 #define ASC_FREQUENCY 25000000 97 98 static int asc_vsbus_match __P((struct device *, struct cfdata *, void *)); 99 static void asc_vsbus_attach __P((struct device *, struct device *, void *)); 100 101 struct cfattach asc_vsbus_ca = { 102 sizeof(struct asc_vsbus_softc), asc_vsbus_match, asc_vsbus_attach 103 }; 104 105 static struct scsipi_device asc_vsbus_dev = { 106 NULL, /* Use the default error handler */ 107 NULL, /* have a queue, served by this */ 108 NULL, /* have no async handler */ 109 NULL, /* use the default done handler */ 110 }; 111 112 /* 113 * Functions and the switch for the MI code 114 */ 115 static u_char asc_vsbus_read_reg __P((struct ncr53c9x_softc *, int)); 116 static void asc_vsbus_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 117 static int asc_vsbus_dma_isintr __P((struct ncr53c9x_softc *)); 118 static void asc_vsbus_dma_reset __P((struct ncr53c9x_softc *)); 119 static int asc_vsbus_dma_intr __P((struct ncr53c9x_softc *)); 120 static int asc_vsbus_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 121 size_t *, int, size_t *)); 122 static void asc_vsbus_dma_go __P((struct ncr53c9x_softc *)); 123 static void asc_vsbus_dma_stop __P((struct ncr53c9x_softc *)); 124 static int asc_vsbus_dma_isactive __P((struct ncr53c9x_softc *)); 125 126 static struct ncr53c9x_glue asc_vsbus_glue = { 127 asc_vsbus_read_reg, 128 asc_vsbus_write_reg, 129 asc_vsbus_dma_isintr, 130 asc_vsbus_dma_reset, 131 asc_vsbus_dma_intr, 132 asc_vsbus_dma_setup, 133 asc_vsbus_dma_go, 134 asc_vsbus_dma_stop, 135 asc_vsbus_dma_isactive, 136 NULL, 137 }; 138 139 static int 140 asc_vsbus_match( struct device *parent, struct cfdata *cf, void *aux) 141 { 142 struct vsbus_attach_args *va = aux; 143 int dummy; 144 volatile u_int8_t *ncr_regs; 145 146 if (vax_boardtype != VAX_BTYP_46 147 && vax_boardtype != VAX_BTYP_48 148 /* && vax_boardtype != VAX_BTYP_49 */) 149 return 0; 150 151 ncr_regs = (volatile u_int8_t *) va->va_addr; 152 153 /* *** need to generate an interrupt here 154 * From trial and error, I've determined that an INT is generated 155 * only when the following sequence of events occurs: 156 * 1) The interrupt status register (0x05) must be read. 157 * 2) SCSI bus reset interrupt must be enabled 158 * 3) SCSI bus reset command must be sent 159 * 4) NOP command must be sent 160 */ 161 162 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 163 ncr_regs[NCR_CFG1 << 2] = 0x06; /* we're ID 6, turn on INT for SCSI reset */ 164 ncr_regs[NCR_CMD << 2] = NCRCMD_RSTSCSI; /* send the reset */ 165 ncr_regs[NCR_CMD << 2] = NCRCMD_NOP; /* send a NOP */ 166 DELAY(10000); 167 168 dummy = ncr_regs[NCR_INTR << 2] & 0xFF; 169 return (dummy & NCRINTR_SBR) != 0; 170 } 171 172 173 /* 174 * Attach this instance, and then all the sub-devices 175 */ 176 static void 177 asc_vsbus_attach(struct device *parent, struct device *self, void *aux) 178 { 179 struct vsbus_attach_args *va = aux; 180 struct asc_vsbus_softc *asc = (void *)self; 181 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 182 int error; 183 184 /* 185 * Set up glue for MI code early; we use some of it here. 186 */ 187 sc->sc_glue = &asc_vsbus_glue; 188 189 asc->sc_bst = va->va_iot; 190 asc->sc_dmat = va->va_dmat; 191 192 error = bus_space_map(asc->sc_bst, va->va_paddr - ASC_REG_NCR, 193 ASC_REG_END, 0, &asc->sc_bsh); 194 if (error) { 195 printf(": failed to map registers: error=%d\n", error); 196 return; 197 } 198 error = bus_space_subregion(asc->sc_bst, asc->sc_bsh, ASC_REG_NCR, 199 ASC_REG_END - ASC_REG_NCR, &asc->sc_ncrh); 200 if (error) { 201 printf(": failed to map ncr registers: error=%d\n", error); 202 return; 203 } 204 error = bus_dmamap_create(asc->sc_dmat, ASC_MAXXFERSIZE, 1, 205 ASC_MAXXFERSIZE, 0, BUS_DMA_NOWAIT, &asc->sc_dmamap); 206 207 sc->sc_id = 6; /* XXX need to get this from VMB */ 208 sc->sc_freq = ASC_FREQUENCY; 209 210 /* gimme Mhz */ 211 sc->sc_freq /= 1000000; 212 213 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr53c9x_intr, 214 &asc->sc_ncr53c9x, SCB_ISTACK); 215 216 /* 217 * XXX More of this should be in ncr53c9x_attach(), but 218 * XXX should we really poke around the chip that much in 219 * XXX the MI code? Think about this more... 220 */ 221 222 /* 223 * Set up static configuration info. 224 */ 225 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 226 sc->sc_cfg2 = NCRCFG2_SCSI2; 227 sc->sc_cfg3 = 0; 228 sc->sc_rev = NCR_VARIANT_NCR53C94; 229 230 /* 231 * XXX minsync and maxxfer _should_ be set up in MI code, 232 * XXX but it appears to have some dependency on what sort 233 * XXX of DMA we're hooked up to, etc. 234 */ 235 236 /* 237 * This is the value used to start sync negotiations 238 * Note that the NCR register "SYNCTP" is programmed 239 * in "clocks per byte", and has a minimum value of 4. 240 * The SCSI period used in negotiation is one-fourth 241 * of the time (in nanoseconds) needed to transfer one byte. 242 * Since the chip's clock is given in MHz, we have the following 243 * formula: 4 * period = (1000 / freq) * 4 244 */ 245 sc->sc_minsync = (1000 / sc->sc_freq); 246 sc->sc_maxxfer = 63 * 1024; 247 248 printf("\n%s", self->dv_xname); /* Pretty print */ 249 250 /* Do the common parts of attachment. */ 251 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 252 sc->sc_adapter.scsipi_minphys = minphys; 253 ncr53c9x_attach(sc, &asc_vsbus_dev); 254 255 /* 256 * Register this device as boot device if we booted from it. 257 * This will fail if there are more than one le in a machine, 258 * fortunately there may be only one. 259 */ 260 if (B_TYPE(bootdev) == BDEV_SD) 261 booted_from = self; 262 } 263 264 /* 265 * Glue functions. 266 */ 267 268 static u_char 269 asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg) 270 { 271 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 272 273 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 274 reg * sizeof(u_int32_t)); 275 } 276 277 static void 278 asc_vsbus_write_reg(sc, reg, val) 279 struct ncr53c9x_softc *sc; 280 int reg; 281 u_char val; 282 { 283 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 284 285 bus_space_write_1(asc->sc_bst, asc->sc_ncrh, 286 reg * sizeof(u_int32_t), val); 287 } 288 289 static int 290 asc_vsbus_dma_isintr(sc) 291 struct ncr53c9x_softc *sc; 292 { 293 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 294 return bus_space_read_1(asc->sc_bst, asc->sc_ncrh, 295 NCR_STAT * sizeof(u_int32_t)) & NCRSTAT_INT; 296 } 297 298 static void 299 asc_vsbus_dma_reset(sc) 300 struct ncr53c9x_softc *sc; 301 { 302 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 303 304 if (asc->sc_flags & ASC_MAPLOADED) 305 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 306 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 307 } 308 309 static int 310 asc_vsbus_dma_intr(sc) 311 struct ncr53c9x_softc *sc; 312 { 313 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 314 u_int tcl, tcm; 315 int trans, resid; 316 317 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 318 panic("asc_vsbus_dma_intr: DMA wasn't active"); 319 320 asc->sc_flags &= ~ASC_DMAACTIVE; 321 322 if (asc->sc_dmasize == 0) { 323 /* A "Transfer Pad" operation completed */ 324 tcl = NCR_READ_REG(sc, NCR_TCL); 325 tcm = NCR_READ_REG(sc, NCR_TCM); 326 NCR_DMA(("asc_vsbus_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 327 tcl | (tcm << 8), tcl, tcm)); 328 return 0; 329 } 330 331 resid = 0; 332 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 333 NCR_DMA(("asc_vsbus_intr: empty FIFO of %d ", resid)); 334 DELAY(1); 335 } 336 if (asc->sc_flags & ASC_MAPLOADED) { 337 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 338 0, asc->sc_dmasize, 339 asc->sc_flags & ASC_FROMMEMORY 340 ? BUS_DMASYNC_POSTWRITE 341 : BUS_DMASYNC_POSTREAD); 342 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 343 } 344 asc->sc_flags &= ~ASC_MAPLOADED; 345 346 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 347 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 348 349 trans = asc->sc_dmasize - resid; 350 if (trans < 0) { /* transferred < 0 ? */ 351 printf("asc_vsbus_intr: xfer (%d) > req (%d)\n", 352 trans, asc->sc_dmasize); 353 trans = asc->sc_dmasize; 354 } 355 NCR_DMA(("asc_vsbus_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 356 tcl, tcm, trans, resid)); 357 358 *asc->sc_dmalen -= trans; 359 *asc->sc_dmaaddr += trans; 360 361 asc->sc_xfers++; 362 return 0; 363 } 364 365 static int 366 asc_vsbus_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 367 int datain, size_t *dmasize) 368 { 369 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 370 371 asc->sc_dmaaddr = addr; 372 asc->sc_dmalen = len; 373 if (datain) { 374 asc->sc_flags &= ~ASC_FROMMEMORY; 375 } else { 376 asc->sc_flags |= ASC_FROMMEMORY; 377 } 378 if ((vaddr_t) *asc->sc_dmaaddr < VM_MIN_KERNEL_ADDRESS) 379 panic("asc_vsbus_dma_setup: dma address (%p) outside of kernel", 380 *asc->sc_dmaaddr); 381 382 NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname, 383 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, (asc->sc_flags & ASC_FROMMEMORY))); 384 *dmasize = asc->sc_dmasize = min(*dmasize, ASC_MAXXFERSIZE); 385 386 if (asc->sc_dmasize) { 387 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, 388 *asc->sc_dmaaddr, asc->sc_dmasize, 389 NULL /* kernel address */, 390 BUS_DMA_NOWAIT|VAX_BUS_DMA_SPILLPAGE)) 391 panic("%s: cannot load dma map", sc->sc_dev.dv_xname); 392 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 393 0, asc->sc_dmasize, 394 asc->sc_flags & ASC_FROMMEMORY 395 ? BUS_DMASYNC_PREWRITE 396 : BUS_DMASYNC_PREREAD); 397 bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_ADR, 398 asc->sc_dmamap->dm_segs[0].ds_addr); 399 bus_space_write_4(asc->sc_bst, asc->sc_bsh, ASC_REG_DIR, 400 asc->sc_flags & ASC_FROMMEMORY); 401 asc->sc_flags |= ASC_MAPLOADED; 402 } 403 404 return 0; 405 } 406 407 static void 408 asc_vsbus_dma_go(struct ncr53c9x_softc *sc) 409 { 410 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 411 412 asc->sc_flags |= ASC_DMAACTIVE; 413 } 414 415 static void 416 asc_vsbus_dma_stop(struct ncr53c9x_softc *sc) 417 { 418 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 419 420 if (asc->sc_flags & ASC_MAPLOADED) { 421 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 422 0, asc->sc_dmasize, 423 asc->sc_flags & ASC_FROMMEMORY 424 ? BUS_DMASYNC_POSTWRITE 425 : BUS_DMASYNC_POSTREAD); 426 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 427 } 428 429 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 430 } 431 432 static int 433 asc_vsbus_dma_isactive(struct ncr53c9x_softc *sc) 434 { 435 struct asc_vsbus_softc *asc = (struct asc_vsbus_softc *)sc; 436 437 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 438 } 439
Indexes created Tue Sep 30 11:09:46 GMT 2025