ncr.c revision 1.36 1 1.36 provos /* $NetBSD: ncr.c,v 1.36 2002/09/27 15:37:00 provos Exp $ */
2 1.1 ragge
3 1.16 ragge /*-
4 1.16 ragge * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 1.1 ragge * All rights reserved.
6 1.1 ragge *
7 1.16 ragge * This code is derived from software contributed to The NetBSD Foundation
8 1.16 ragge * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson.
9 1.16 ragge *
10 1.1 ragge * Redistribution and use in source and binary forms, with or without
11 1.1 ragge * modification, are permitted provided that the following conditions
12 1.1 ragge * are met:
13 1.1 ragge * 1. Redistributions of source code must retain the above copyright
14 1.1 ragge * notice, this list of conditions and the following disclaimer.
15 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ragge * notice, this list of conditions and the following disclaimer in the
17 1.1 ragge * documentation and/or other materials provided with the distribution.
18 1.16 ragge * 3. All advertising materials mentioning features or use of this software
19 1.1 ragge * must display the following acknowledgement:
20 1.23 ragge * This product includes software developed by the NetBSD
21 1.23 ragge * Foundation, Inc. and its contributors.
22 1.16 ragge * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.16 ragge * contributors may be used to endorse or promote products derived
24 1.16 ragge * from this software without specific prior written permission.
25 1.16 ragge *
26 1.16 ragge * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.16 ragge * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.16 ragge * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.16 ragge * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.16 ragge * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.16 ragge * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.16 ragge * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.16 ragge * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.16 ragge * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.16 ragge * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.16 ragge * POSSIBILITY OF SUCH DAMAGE.
37 1.1 ragge */
38 1.1 ragge
39 1.1 ragge /*
40 1.16 ragge * This file contains the machine-dependent parts of the NCR-5380
41 1.16 ragge * controller. The machine-independent parts are in ncr5380sbc.c.
42 1.16 ragge *
43 1.16 ragge * Jens A. Nilsson.
44 1.16 ragge *
45 1.16 ragge * Credits:
46 1.16 ragge *
47 1.16 ragge * This code is based on arch/sun3/dev/si*
48 1.16 ragge * Written by David Jones, Gordon Ross, and Adam Glass.
49 1.1 ragge */
50 1.1 ragge
51 1.1 ragge #include <sys/param.h>
52 1.1 ragge #include <sys/systm.h>
53 1.16 ragge #include <sys/errno.h>
54 1.1 ragge #include <sys/kernel.h>
55 1.16 ragge #include <sys/malloc.h>
56 1.16 ragge #include <sys/device.h>
57 1.1 ragge #include <sys/buf.h>
58 1.1 ragge #include <sys/proc.h>
59 1.1 ragge #include <sys/user.h>
60 1.1 ragge
61 1.9 bouyer #include <dev/scsipi/scsi_all.h>
62 1.9 bouyer #include <dev/scsipi/scsipi_all.h>
63 1.9 bouyer #include <dev/scsipi/scsipi_debug.h>
64 1.9 bouyer #include <dev/scsipi/scsiconf.h>
65 1.1 ragge
66 1.1 ragge #include <dev/ic/ncr5380reg.h>
67 1.1 ragge #include <dev/ic/ncr5380var.h>
68 1.1 ragge
69 1.24 matt #include <machine/cpu.h>
70 1.16 ragge #include <machine/vsbus.h>
71 1.16 ragge #include <machine/bus.h>
72 1.21 ragge #include <machine/sid.h>
73 1.24 matt #include <machine/scb.h>
74 1.27 ragge #include <machine/clock.h>
75 1.1 ragge
76 1.16 ragge #include "ioconf.h"
77 1.1 ragge
78 1.16 ragge #define MIN_DMA_LEN 128
79 1.1 ragge
80 1.1 ragge struct si_dma_handle {
81 1.16 ragge int dh_flags;
82 1.16 ragge #define SIDH_BUSY 1
83 1.16 ragge #define SIDH_OUT 2
84 1.23 ragge caddr_t dh_addr;
85 1.23 ragge int dh_len;
86 1.23 ragge struct proc *dh_proc;
87 1.1 ragge };
88 1.1 ragge
89 1.1 ragge struct si_softc {
90 1.23 ragge struct ncr5380_softc ncr_sc;
91 1.28 matt struct evcnt ncr_intrcnt;
92 1.23 ragge caddr_t ncr_addr;
93 1.23 ragge int ncr_off;
94 1.23 ragge int ncr_dmaaddr;
95 1.23 ragge int ncr_dmacount;
96 1.23 ragge int ncr_dmadir;
97 1.23 ragge struct si_dma_handle ncr_dma[SCI_OPENINGS];
98 1.32 ragge struct vsbus_dma sc_vd;
99 1.32 ragge int onlyscsi; /* This machine needs no queueing */
100 1.1 ragge };
101 1.1 ragge
102 1.32 ragge static int ncr_dmasize;
103 1.32 ragge
104 1.31 matt static int si_vsbus_match(struct device *, struct cfdata *, void *);
105 1.31 matt static void si_vsbus_attach(struct device *, struct device *, void *);
106 1.23 ragge static void si_minphys(struct buf *);
107 1.23 ragge
108 1.31 matt static void si_dma_alloc(struct ncr5380_softc *);
109 1.31 matt static void si_dma_free(struct ncr5380_softc *);
110 1.31 matt static void si_dma_setup(struct ncr5380_softc *);
111 1.31 matt static void si_dma_start(struct ncr5380_softc *);
112 1.31 matt static void si_dma_poll(struct ncr5380_softc *);
113 1.31 matt static void si_dma_eop(struct ncr5380_softc *);
114 1.31 matt static void si_dma_stop(struct ncr5380_softc *);
115 1.32 ragge static void si_dma_go(void *);
116 1.23 ragge
117 1.31 matt struct cfattach si_vsbus_ca = {
118 1.31 matt sizeof(struct si_softc), si_vsbus_match, si_vsbus_attach
119 1.1 ragge };
120 1.1 ragge
121 1.16 ragge static int
122 1.31 matt si_vsbus_match(struct device *parent, struct cfdata *cf, void *aux)
123 1.1 ragge {
124 1.16 ragge struct vsbus_attach_args *va = aux;
125 1.18 ragge volatile char *si_csr = (char *) va->va_addr;
126 1.1 ragge
127 1.31 matt if (vax_boardtype == VAX_BTYP_49 || vax_boardtype == VAX_BTYP_46
128 1.34 ragge || vax_boardtype == VAX_BTYP_48 || vax_boardtype == VAX_BTYP_53)
129 1.21 ragge return 0;
130 1.19 ragge /* This is the way Linux autoprobes the interrupt MK-990321 */
131 1.19 ragge si_csr[12] = 0;
132 1.19 ragge si_csr[16] = 0x80;
133 1.19 ragge si_csr[0] = 0x80;
134 1.19 ragge si_csr[4] = 5; /* 0xcf */
135 1.18 ragge DELAY(100000);
136 1.18 ragge return 1;
137 1.1 ragge }
138 1.1 ragge
139 1.16 ragge static void
140 1.31 matt si_vsbus_attach(struct device *parent, struct device *self, void *aux)
141 1.1 ragge {
142 1.18 ragge struct vsbus_attach_args *va = aux;
143 1.1 ragge struct si_softc *sc = (struct si_softc *) self;
144 1.16 ragge struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
145 1.27 ragge int tweak, target;
146 1.24 matt
147 1.28 matt scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc,
148 1.28 matt SCB_ISTACK, &sc->ncr_intrcnt);
149 1.30 matt evcnt_attach_dynamic(&sc->ncr_intrcnt, EVCNT_TYPE_INTR, NULL,
150 1.30 matt self->dv_xname, "intr");
151 1.24 matt
152 1.1 ragge /*
153 1.23 ragge * DMA area mapin.
154 1.23 ragge * On VS3100, split the 128K block between the two devices.
155 1.23 ragge * On VS2000, don't care for now.
156 1.1 ragge */
157 1.23 ragge #define DMASIZE (64*1024)
158 1.32 ragge if (va->va_paddr & 0x100) { /* Secondary SCSI controller */
159 1.32 ragge sc->ncr_off = DMASIZE;
160 1.32 ragge sc->onlyscsi = 1;
161 1.23 ragge }
162 1.32 ragge sc->ncr_addr = (caddr_t)va->va_dmaaddr;
163 1.32 ragge ncr_dmasize = min(va->va_dmasize, MAXPHYS);
164 1.32 ragge
165 1.32 ragge /*
166 1.32 ragge * MD function pointers used by the MI code.
167 1.32 ragge */
168 1.32 ragge ncr_sc->sc_dma_alloc = si_dma_alloc;
169 1.32 ragge ncr_sc->sc_dma_free = si_dma_free;
170 1.32 ragge ncr_sc->sc_dma_setup = si_dma_setup;
171 1.32 ragge ncr_sc->sc_dma_start = si_dma_start;
172 1.32 ragge ncr_sc->sc_dma_poll = si_dma_poll;
173 1.32 ragge ncr_sc->sc_dma_eop = si_dma_eop;
174 1.32 ragge ncr_sc->sc_dma_stop = si_dma_stop;
175 1.32 ragge
176 1.32 ragge /* DMA control register offsets */
177 1.32 ragge sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */
178 1.32 ragge sc->ncr_dmacount = 64; /* DMA count register */
179 1.32 ragge sc->ncr_dmadir = 68; /* Direction of DMA transfer */
180 1.32 ragge
181 1.16 ragge ncr_sc->sc_pio_out = ncr5380_pio_out;
182 1.16 ragge ncr_sc->sc_pio_in = ncr5380_pio_in;
183 1.16 ragge
184 1.16 ragge ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
185 1.15 thorpej
186 1.15 thorpej /*
187 1.16 ragge * Initialize fields used by the MI code.
188 1.1 ragge */
189 1.22 ragge /* ncr_sc->sc_regt = Unused on VAX */
190 1.22 ragge ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1);
191 1.22 ragge
192 1.22 ragge /* Register offsets */
193 1.22 ragge ncr_sc->sci_r0 = 0;
194 1.22 ragge ncr_sc->sci_r1 = 4;
195 1.22 ragge ncr_sc->sci_r2 = 8;
196 1.22 ragge ncr_sc->sci_r3 = 12;
197 1.22 ragge ncr_sc->sci_r4 = 16;
198 1.22 ragge ncr_sc->sci_r5 = 20;
199 1.22 ragge ncr_sc->sci_r6 = 24;
200 1.22 ragge ncr_sc->sci_r7 = 28;
201 1.26 tsutsui
202 1.26 tsutsui ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
203 1.1 ragge
204 1.20 ragge ncr_sc->sc_no_disconnect = 0xff;
205 1.25 mycroft
206 1.27 ragge /*
207 1.27 ragge * Get the SCSI chip target address out of NVRAM.
208 1.27 ragge * This do not apply to the VS2000.
209 1.27 ragge */
210 1.27 ragge tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0);
211 1.27 ragge if (vax_boardtype == VAX_BTYP_410)
212 1.27 ragge target = 7;
213 1.27 ragge else
214 1.27 ragge target = (clk_page[0xbc/2] >> tweak) & 7;
215 1.27 ragge
216 1.27 ragge printf("\n%s: NCR5380, SCSI ID %d\n", ncr_sc->sc_dev.dv_xname, target);
217 1.27 ragge
218 1.35 bouyer ncr_sc->sc_adapter.adapt_minphys = si_minphys;
219 1.35 bouyer ncr_sc->sc_channel.chan_id = target;
220 1.32 ragge
221 1.32 ragge /*
222 1.32 ragge * Init the vsbus DMA resource queue struct */
223 1.32 ragge sc->sc_vd.vd_go = si_dma_go;
224 1.32 ragge sc->sc_vd.vd_arg = sc;
225 1.32 ragge
226 1.1 ragge /*
227 1.16 ragge * Initialize si board itself.
228 1.1 ragge */
229 1.25 mycroft ncr5380_attach(ncr_sc);
230 1.1 ragge }
231 1.1 ragge
232 1.22 ragge /*
233 1.22 ragge * Adjust the max transfer size. The DMA buffer is only 16k on VS2000.
234 1.22 ragge */
235 1.16 ragge static void
236 1.1 ragge si_minphys(struct buf *bp)
237 1.1 ragge {
238 1.32 ragge if (bp->b_bcount > ncr_dmasize)
239 1.32 ragge bp->b_bcount = ncr_dmasize;
240 1.23 ragge }
241 1.23 ragge
242 1.23 ragge void
243 1.31 matt si_dma_alloc(struct ncr5380_softc *ncr_sc)
244 1.23 ragge {
245 1.23 ragge struct si_softc *sc = (struct si_softc *)ncr_sc;
246 1.23 ragge struct sci_req *sr = ncr_sc->sc_current;
247 1.23 ragge struct scsipi_xfer *xs = sr->sr_xs;
248 1.23 ragge struct si_dma_handle *dh;
249 1.23 ragge int xlen, i;
250 1.23 ragge
251 1.23 ragge #ifdef DIAGNOSTIC
252 1.23 ragge if (sr->sr_dma_hand != NULL)
253 1.23 ragge panic("si_dma_alloc: already have DMA handle");
254 1.23 ragge #endif
255 1.23 ragge
256 1.23 ragge /* Polled transfers shouldn't allocate a DMA handle. */
257 1.23 ragge if (sr->sr_flags & SR_IMMED)
258 1.23 ragge return;
259 1.23 ragge
260 1.23 ragge xlen = ncr_sc->sc_datalen;
261 1.23 ragge
262 1.23 ragge /* Make sure our caller checked sc_min_dma_len. */
263 1.23 ragge if (xlen < MIN_DMA_LEN)
264 1.36 provos panic("si_dma_alloc: len=0x%x", xlen);
265 1.23 ragge
266 1.23 ragge /*
267 1.23 ragge * Find free PDMA handle. Guaranteed to find one since we
268 1.23 ragge * have as many PDMA handles as the driver has processes.
269 1.23 ragge * (instances?)
270 1.23 ragge */
271 1.23 ragge for (i = 0; i < SCI_OPENINGS; i++) {
272 1.23 ragge if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0)
273 1.23 ragge goto found;
274 1.23 ragge }
275 1.23 ragge panic("sbc: no free PDMA handles");
276 1.23 ragge found:
277 1.23 ragge dh = &sc->ncr_dma[i];
278 1.23 ragge dh->dh_flags = SIDH_BUSY;
279 1.23 ragge dh->dh_addr = ncr_sc->sc_dataptr;
280 1.23 ragge dh->dh_len = xlen;
281 1.23 ragge dh->dh_proc = xs->bp->b_proc;
282 1.23 ragge
283 1.23 ragge /* Remember dest buffer parameters */
284 1.23 ragge if (xs->xs_control & XS_CTL_DATA_OUT)
285 1.23 ragge dh->dh_flags |= SIDH_OUT;
286 1.23 ragge
287 1.23 ragge sr->sr_dma_hand = dh;
288 1.23 ragge }
289 1.23 ragge
290 1.23 ragge void
291 1.31 matt si_dma_free(struct ncr5380_softc *ncr_sc)
292 1.23 ragge {
293 1.23 ragge struct sci_req *sr = ncr_sc->sc_current;
294 1.23 ragge struct si_dma_handle *dh = sr->sr_dma_hand;
295 1.23 ragge
296 1.23 ragge if (dh->dh_flags & SIDH_BUSY)
297 1.23 ragge dh->dh_flags = 0;
298 1.23 ragge else
299 1.23 ragge printf("si_dma_free: free'ing unused buffer\n");
300 1.23 ragge
301 1.23 ragge sr->sr_dma_hand = NULL;
302 1.23 ragge }
303 1.23 ragge
304 1.23 ragge void
305 1.31 matt si_dma_setup(struct ncr5380_softc *ncr_sc)
306 1.23 ragge {
307 1.23 ragge /* Do nothing here */
308 1.23 ragge }
309 1.23 ragge
310 1.23 ragge void
311 1.31 matt si_dma_start(struct ncr5380_softc *ncr_sc)
312 1.23 ragge {
313 1.23 ragge struct si_softc *sc = (struct si_softc *)ncr_sc;
314 1.32 ragge
315 1.32 ragge /* Just put on queue; will call go() from below */
316 1.32 ragge if (sc->onlyscsi)
317 1.32 ragge si_dma_go(ncr_sc);
318 1.32 ragge else
319 1.32 ragge vsbus_dma_start(&sc->sc_vd);
320 1.32 ragge }
321 1.32 ragge
322 1.32 ragge /*
323 1.32 ragge * go() routine called when another transfer somewhere is finished.
324 1.32 ragge */
325 1.32 ragge void
326 1.32 ragge si_dma_go(void *arg)
327 1.32 ragge {
328 1.32 ragge struct ncr5380_softc *ncr_sc = arg;
329 1.32 ragge struct si_softc *sc = (struct si_softc *)ncr_sc;
330 1.23 ragge struct sci_req *sr = ncr_sc->sc_current;
331 1.23 ragge struct si_dma_handle *dh = sr->sr_dma_hand;
332 1.23 ragge
333 1.23 ragge /*
334 1.23 ragge * Set the VAX-DMA-specific registers, and copy the data if
335 1.23 ragge * it is directed "outbound".
336 1.23 ragge */
337 1.23 ragge if (dh->dh_flags & SIDH_OUT) {
338 1.32 ragge vsbus_copyfromproc(dh->dh_proc, dh->dh_addr,
339 1.33 ragge sc->ncr_addr + sc->ncr_off, dh->dh_len);
340 1.23 ragge bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh,
341 1.23 ragge sc->ncr_dmadir, 0);
342 1.23 ragge } else {
343 1.23 ragge bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh,
344 1.23 ragge sc->ncr_dmadir, 1);
345 1.23 ragge }
346 1.23 ragge bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh,
347 1.23 ragge sc->ncr_dmacount, -dh->dh_len);
348 1.23 ragge bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh,
349 1.23 ragge sc->ncr_dmaaddr, sc->ncr_off);
350 1.23 ragge /*
351 1.23 ragge * Now from the 5380-internal DMA registers.
352 1.23 ragge */
353 1.23 ragge if (dh->dh_flags & SIDH_OUT) {
354 1.23 ragge NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
355 1.23 ragge NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
356 1.23 ragge NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
357 1.23 ragge | SCI_MODE_DMA | SCI_MODE_DMA_IE);
358 1.23 ragge NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
359 1.23 ragge } else {
360 1.23 ragge NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
361 1.23 ragge NCR5380_WRITE(ncr_sc, sci_icmd, 0);
362 1.23 ragge NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
363 1.23 ragge | SCI_MODE_DMA | SCI_MODE_DMA_IE);
364 1.23 ragge NCR5380_WRITE(ncr_sc, sci_irecv, 0);
365 1.23 ragge }
366 1.23 ragge ncr_sc->sc_state |= NCR_DOINGDMA;
367 1.23 ragge }
368 1.23 ragge
369 1.23 ragge /*
370 1.23 ragge * When?
371 1.23 ragge */
372 1.23 ragge void
373 1.31 matt si_dma_poll(struct ncr5380_softc *ncr_sc)
374 1.23 ragge {
375 1.23 ragge printf("si_dma_poll\n");
376 1.23 ragge }
377 1.23 ragge
378 1.23 ragge /*
379 1.23 ragge * When?
380 1.23 ragge */
381 1.23 ragge void
382 1.31 matt si_dma_eop(struct ncr5380_softc *ncr_sc)
383 1.23 ragge {
384 1.23 ragge printf("si_dma_eop\n");
385 1.23 ragge }
386 1.23 ragge
387 1.23 ragge void
388 1.31 matt si_dma_stop(struct ncr5380_softc *ncr_sc)
389 1.23 ragge {
390 1.23 ragge struct si_softc *sc = (struct si_softc *)ncr_sc;
391 1.23 ragge struct sci_req *sr = ncr_sc->sc_current;
392 1.23 ragge struct si_dma_handle *dh = sr->sr_dma_hand;
393 1.23 ragge int count, i;
394 1.23 ragge
395 1.23 ragge if (ncr_sc->sc_state & NCR_DOINGDMA)
396 1.23 ragge ncr_sc->sc_state &= ~NCR_DOINGDMA;
397 1.23 ragge
398 1.23 ragge /*
399 1.23 ragge * Sometimes the FIFO buffer isn't drained when the
400 1.23 ragge * interrupt is posted. Just loop here and hope that
401 1.23 ragge * it will drain soon.
402 1.23 ragge */
403 1.23 ragge for (i = 0; i < 20000; i++) {
404 1.23 ragge count = bus_space_read_4(ncr_sc->sc_regt,
405 1.23 ragge ncr_sc->sc_regh, sc->ncr_dmacount);
406 1.23 ragge if (count == 0)
407 1.23 ragge break;
408 1.23 ragge DELAY(100);
409 1.23 ragge }
410 1.23 ragge if (count == 0) {
411 1.23 ragge if (((dh->dh_flags & SIDH_OUT) == 0)) {
412 1.33 ragge vsbus_copytoproc(dh->dh_proc,
413 1.33 ragge sc->ncr_addr + sc->ncr_off,
414 1.32 ragge dh->dh_addr, dh->dh_len);
415 1.23 ragge }
416 1.23 ragge ncr_sc->sc_dataptr += dh->dh_len;
417 1.23 ragge ncr_sc->sc_datalen -= dh->dh_len;
418 1.23 ragge }
419 1.23 ragge
420 1.23 ragge NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) &
421 1.23 ragge ~(SCI_MODE_DMA | SCI_MODE_DMA_IE));
422 1.23 ragge NCR5380_WRITE(ncr_sc, sci_icmd, 0);
423 1.32 ragge if (sc->onlyscsi == 0)
424 1.32 ragge vsbus_dma_intr(); /* Try to start more transfers */
425 1.1 ragge }
426