ncr.c revision 1.23
1 /* $NetBSD: ncr.c,v 1.23 1999/10/22 21:12:20 ragge Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/vsbus.h> 76 #include <machine/bus.h> 77 #include <machine/sid.h> 78 79 #include "ioconf.h" 80 81 #define MIN_DMA_LEN 128 82 83 struct si_dma_handle { 84 int dh_flags; 85 #define SIDH_BUSY 1 86 #define SIDH_OUT 2 87 caddr_t dh_addr; 88 int dh_len; 89 struct proc *dh_proc; 90 }; 91 92 struct si_softc { 93 struct ncr5380_softc ncr_sc; 94 caddr_t ncr_addr; 95 int ncr_off; 96 int ncr_dmaaddr; 97 int ncr_dmacount; 98 int ncr_dmadir; 99 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 100 }; 101 102 /* This is copied from julian's bt driver */ 103 /* "so we have a default dev struct for our link struct." */ 104 static struct scsipi_device si_dev = { 105 NULL, /* Use default error handler. */ 106 NULL, /* Use default start handler. */ 107 NULL, /* Use default async handler. */ 108 NULL, /* Use default "done" routine. */ 109 }; 110 111 static int si_match(struct device *, struct cfdata *, void *); 112 static void si_attach(struct device *, struct device *, void *); 113 static void si_minphys(struct buf *); 114 static void si_intr(int); 115 116 static void si_dma_alloc __P((struct ncr5380_softc *)); 117 static void si_dma_free __P((struct ncr5380_softc *)); 118 static void si_dma_setup __P((struct ncr5380_softc *)); 119 static void si_dma_start __P((struct ncr5380_softc *)); 120 static void si_dma_poll __P((struct ncr5380_softc *)); 121 static void si_dma_eop __P((struct ncr5380_softc *)); 122 static void si_dma_stop __P((struct ncr5380_softc *)); 123 124 125 struct cfattach ncr_ca = { 126 sizeof(struct si_softc), si_match, si_attach 127 }; 128 129 static int 130 si_match(parent, cf, aux) 131 struct device *parent; 132 struct cfdata *cf; 133 void *aux; 134 { 135 struct vsbus_attach_args *va = aux; 136 volatile char *si_csr = (char *) va->va_addr; 137 138 if (vax_boardtype == VAX_BTYP_49) 139 return 0; 140 /* This is the way Linux autoprobes the interrupt MK-990321 */ 141 si_csr[12] = 0; 142 si_csr[16] = 0x80; 143 si_csr[0] = 0x80; 144 si_csr[4] = 5; /* 0xcf */ 145 DELAY(100000); 146 va->va_ivec = si_intr; 147 return 1; 148 } 149 150 static void 151 si_attach(parent, self, aux) 152 struct device *parent, *self; 153 void *aux; 154 { 155 struct vsbus_attach_args *va = aux; 156 struct si_softc *sc = (struct si_softc *) self; 157 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 158 159 printf("\n"); 160 /* 161 * DMA area mapin. 162 * On VS3100, split the 128K block between the two devices. 163 * On VS2000, don't care for now. 164 */ 165 #define DMASIZE (64*1024) 166 if (vax_boardtype != VAX_BTYP_410) { 167 if (va->va_paddr & 0x100) /* Magic */ 168 sc->ncr_off = DMASIZE; 169 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 170 171 ioaccess((vaddr_t)sc->ncr_addr, 172 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 173 174 /* 175 * MD function pointers used by the MI code. 176 */ 177 ncr_sc->sc_dma_alloc = si_dma_alloc; 178 ncr_sc->sc_dma_free = si_dma_free; 179 ncr_sc->sc_dma_setup = si_dma_setup; 180 ncr_sc->sc_dma_start = si_dma_start; 181 ncr_sc->sc_dma_poll = si_dma_poll; 182 ncr_sc->sc_dma_eop = si_dma_eop; 183 ncr_sc->sc_dma_stop = si_dma_stop; 184 185 /* DMA control register offsets */ 186 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 187 sc->ncr_dmacount = 64; /* DMA count register */ 188 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 189 } 190 ncr_sc->sc_pio_out = ncr5380_pio_out; 191 ncr_sc->sc_pio_in = ncr5380_pio_in; 192 193 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 194 195 /* 196 * Fill in the adapter. 197 */ 198 ncr_sc->sc_adapter.scsipi_cmd = ncr5380_scsi_cmd; 199 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 200 201 /* 202 * Fill in the prototype scsi_link. 203 */ 204 ncr_sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 205 ncr_sc->sc_link.adapter_softc = sc; 206 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 207 ncr_sc->sc_link.adapter = &ncr_sc->sc_adapter; 208 ncr_sc->sc_link.device = &si_dev; 209 ncr_sc->sc_link.type = BUS_SCSI; 210 211 /* 212 * Initialize fields used by the MI code. 213 */ 214 /* ncr_sc->sc_regt = Unused on VAX */ 215 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 216 217 /* Register offsets */ 218 ncr_sc->sci_r0 = 0; 219 ncr_sc->sci_r1 = 4; 220 ncr_sc->sci_r2 = 8; 221 ncr_sc->sci_r3 = 12; 222 ncr_sc->sci_r4 = 16; 223 ncr_sc->sci_r5 = 20; 224 ncr_sc->sci_r6 = 24; 225 ncr_sc->sci_r7 = 28; 226 227 ncr_sc->sc_no_disconnect = 0xff; 228 /* 229 * Initialize si board itself. 230 */ 231 ncr5380_init(ncr_sc); 232 ncr5380_reset_scsibus(ncr_sc); 233 234 config_found(&(ncr_sc->sc_dev), &(ncr_sc->sc_link), scsiprint); 235 } 236 237 /* 238 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 239 */ 240 static void 241 si_minphys(struct buf *bp) 242 { 243 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 244 bp->b_bcount = (16*1024); 245 else if (bp->b_bcount > MAXPHYS) 246 bp->b_bcount = MAXPHYS; 247 } 248 249 static void 250 si_intr(int arg) 251 { 252 ncr5380_intr(ncr_cd.cd_devs[arg]); 253 } 254 255 void 256 si_dma_alloc(ncr_sc) 257 struct ncr5380_softc *ncr_sc; 258 { 259 struct si_softc *sc = (struct si_softc *)ncr_sc; 260 struct sci_req *sr = ncr_sc->sc_current; 261 struct scsipi_xfer *xs = sr->sr_xs; 262 struct si_dma_handle *dh; 263 int xlen, i; 264 265 #ifdef DIAGNOSTIC 266 if (sr->sr_dma_hand != NULL) 267 panic("si_dma_alloc: already have DMA handle"); 268 #endif 269 270 /* Polled transfers shouldn't allocate a DMA handle. */ 271 if (sr->sr_flags & SR_IMMED) 272 return; 273 274 xlen = ncr_sc->sc_datalen; 275 276 /* Make sure our caller checked sc_min_dma_len. */ 277 if (xlen < MIN_DMA_LEN) 278 panic("si_dma_alloc: len=0x%x\n", xlen); 279 280 /* 281 * Find free PDMA handle. Guaranteed to find one since we 282 * have as many PDMA handles as the driver has processes. 283 * (instances?) 284 */ 285 for (i = 0; i < SCI_OPENINGS; i++) { 286 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 287 goto found; 288 } 289 panic("sbc: no free PDMA handles"); 290 found: 291 dh = &sc->ncr_dma[i]; 292 dh->dh_flags = SIDH_BUSY; 293 dh->dh_addr = ncr_sc->sc_dataptr; 294 dh->dh_len = xlen; 295 dh->dh_proc = xs->bp->b_proc; 296 297 /* Remember dest buffer parameters */ 298 if (xs->xs_control & XS_CTL_DATA_OUT) 299 dh->dh_flags |= SIDH_OUT; 300 301 sr->sr_dma_hand = dh; 302 } 303 304 void 305 si_dma_free(ncr_sc) 306 struct ncr5380_softc *ncr_sc; 307 { 308 struct sci_req *sr = ncr_sc->sc_current; 309 struct si_dma_handle *dh = sr->sr_dma_hand; 310 311 if (dh->dh_flags & SIDH_BUSY) 312 dh->dh_flags = 0; 313 else 314 printf("si_dma_free: free'ing unused buffer\n"); 315 316 sr->sr_dma_hand = NULL; 317 } 318 319 void 320 si_dma_setup(ncr_sc) 321 struct ncr5380_softc *ncr_sc; 322 { 323 /* Do nothing here */ 324 } 325 326 void 327 si_dma_start(ncr_sc) 328 struct ncr5380_softc *ncr_sc; 329 { 330 struct si_softc *sc = (struct si_softc *)ncr_sc; 331 struct sci_req *sr = ncr_sc->sc_current; 332 struct si_dma_handle *dh = sr->sr_dma_hand; 333 334 /* 335 * Set the VAX-DMA-specific registers, and copy the data if 336 * it is directed "outbound". 337 */ 338 if (dh->dh_flags & SIDH_OUT) { 339 if ((vaddr_t)dh->dh_addr & KERNBASE) 340 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 341 else 342 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 343 sc->ncr_addr, dh->dh_len); 344 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 345 sc->ncr_dmadir, 0); 346 } else { 347 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 348 sc->ncr_dmadir, 1); 349 } 350 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 351 sc->ncr_dmacount, -dh->dh_len); 352 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 353 sc->ncr_dmaaddr, sc->ncr_off); 354 /* 355 * Now from the 5380-internal DMA registers. 356 */ 357 if (dh->dh_flags & SIDH_OUT) { 358 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 359 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 360 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 361 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 362 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 363 } else { 364 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 365 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 366 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 367 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 368 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 369 } 370 ncr_sc->sc_state |= NCR_DOINGDMA; 371 } 372 373 /* 374 * When? 375 */ 376 void 377 si_dma_poll(ncr_sc) 378 struct ncr5380_softc *ncr_sc; 379 { 380 printf("si_dma_poll\n"); 381 } 382 383 /* 384 * When? 385 */ 386 void 387 si_dma_eop(ncr_sc) 388 struct ncr5380_softc *ncr_sc; 389 { 390 printf("si_dma_eop\n"); 391 } 392 393 void 394 si_dma_stop(ncr_sc) 395 struct ncr5380_softc *ncr_sc; 396 { 397 struct si_softc *sc = (struct si_softc *)ncr_sc; 398 struct sci_req *sr = ncr_sc->sc_current; 399 struct si_dma_handle *dh = sr->sr_dma_hand; 400 int count, i; 401 402 if (ncr_sc->sc_state & NCR_DOINGDMA) 403 ncr_sc->sc_state &= ~NCR_DOINGDMA; 404 405 /* 406 * Sometimes the FIFO buffer isn't drained when the 407 * interrupt is posted. Just loop here and hope that 408 * it will drain soon. 409 */ 410 for (i = 0; i < 20000; i++) { 411 count = bus_space_read_4(ncr_sc->sc_regt, 412 ncr_sc->sc_regh, sc->ncr_dmacount); 413 if (count == 0) 414 break; 415 DELAY(100); 416 } 417 if (count == 0) { 418 if (((dh->dh_flags & SIDH_OUT) == 0)) { 419 if ((vaddr_t)dh->dh_addr & KERNBASE) 420 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 421 else 422 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 423 dh->dh_addr, dh->dh_len); 424 425 } 426 ncr_sc->sc_dataptr += dh->dh_len; 427 ncr_sc->sc_datalen -= dh->dh_len; 428 } 429 430 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 431 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 432 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 433 } 434
Indexes created Tue Sep 30 20:09:53 GMT 2025