ncr.c revision 1.25
1 /* $NetBSD: ncr.c,v 1.25 2000/03/18 16:13:26 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/cpu.h> 76 #include <machine/vsbus.h> 77 #include <machine/bus.h> 78 #include <machine/sid.h> 79 #include <machine/scb.h> 80 81 #include "ioconf.h" 82 83 #define MIN_DMA_LEN 128 84 85 struct si_dma_handle { 86 int dh_flags; 87 #define SIDH_BUSY 1 88 #define SIDH_OUT 2 89 caddr_t dh_addr; 90 int dh_len; 91 struct proc *dh_proc; 92 }; 93 94 struct si_softc { 95 struct ncr5380_softc ncr_sc; 96 caddr_t ncr_addr; 97 int ncr_off; 98 int ncr_dmaaddr; 99 int ncr_dmacount; 100 int ncr_dmadir; 101 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 102 }; 103 104 static int si_match(struct device *, struct cfdata *, void *); 105 static void si_attach(struct device *, struct device *, void *); 106 static void si_minphys(struct buf *); 107 108 static void si_dma_alloc __P((struct ncr5380_softc *)); 109 static void si_dma_free __P((struct ncr5380_softc *)); 110 static void si_dma_setup __P((struct ncr5380_softc *)); 111 static void si_dma_start __P((struct ncr5380_softc *)); 112 static void si_dma_poll __P((struct ncr5380_softc *)); 113 static void si_dma_eop __P((struct ncr5380_softc *)); 114 static void si_dma_stop __P((struct ncr5380_softc *)); 115 116 117 struct cfattach ncr_ca = { 118 sizeof(struct si_softc), si_match, si_attach 119 }; 120 121 static int 122 si_match(parent, cf, aux) 123 struct device *parent; 124 struct cfdata *cf; 125 void *aux; 126 { 127 struct vsbus_attach_args *va = aux; 128 volatile char *si_csr = (char *) va->va_addr; 129 130 if (vax_boardtype == VAX_BTYP_49) 131 return 0; 132 /* This is the way Linux autoprobes the interrupt MK-990321 */ 133 si_csr[12] = 0; 134 si_csr[16] = 0x80; 135 si_csr[0] = 0x80; 136 si_csr[4] = 5; /* 0xcf */ 137 DELAY(100000); 138 return 1; 139 } 140 141 static void 142 si_attach(parent, self, aux) 143 struct device *parent, *self; 144 void *aux; 145 { 146 struct vsbus_attach_args *va = aux; 147 struct si_softc *sc = (struct si_softc *) self; 148 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 149 150 printf("\n"); 151 152 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, SCB_ISTACK); 153 154 /* 155 * DMA area mapin. 156 * On VS3100, split the 128K block between the two devices. 157 * On VS2000, don't care for now. 158 */ 159 #define DMASIZE (64*1024) 160 if (vax_boardtype != VAX_BTYP_410) { 161 if (va->va_paddr & 0x100) /* Magic */ 162 sc->ncr_off = DMASIZE; 163 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 164 165 ioaccess((vaddr_t)sc->ncr_addr, 166 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 167 168 /* 169 * MD function pointers used by the MI code. 170 */ 171 ncr_sc->sc_dma_alloc = si_dma_alloc; 172 ncr_sc->sc_dma_free = si_dma_free; 173 ncr_sc->sc_dma_setup = si_dma_setup; 174 ncr_sc->sc_dma_start = si_dma_start; 175 ncr_sc->sc_dma_poll = si_dma_poll; 176 ncr_sc->sc_dma_eop = si_dma_eop; 177 ncr_sc->sc_dma_stop = si_dma_stop; 178 179 /* DMA control register offsets */ 180 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 181 sc->ncr_dmacount = 64; /* DMA count register */ 182 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 183 } 184 ncr_sc->sc_pio_out = ncr5380_pio_out; 185 ncr_sc->sc_pio_in = ncr5380_pio_in; 186 187 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 188 189 /* 190 * Initialize fields used by the MI code. 191 */ 192 /* ncr_sc->sc_regt = Unused on VAX */ 193 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 194 195 /* Register offsets */ 196 ncr_sc->sci_r0 = 0; 197 ncr_sc->sci_r1 = 4; 198 ncr_sc->sci_r2 = 8; 199 ncr_sc->sci_r3 = 12; 200 ncr_sc->sci_r4 = 16; 201 ncr_sc->sci_r5 = 20; 202 ncr_sc->sci_r6 = 24; 203 ncr_sc->sci_r7 = 28; 204 205 ncr_sc->sc_no_disconnect = 0xff; 206 207 ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 208 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 209 210 /* 211 * Initialize si board itself. 212 */ 213 ncr5380_attach(ncr_sc); 214 } 215 216 /* 217 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 218 */ 219 static void 220 si_minphys(struct buf *bp) 221 { 222 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 223 bp->b_bcount = (16*1024); 224 else if (bp->b_bcount > MAXPHYS) 225 bp->b_bcount = MAXPHYS; 226 } 227 228 void 229 si_dma_alloc(ncr_sc) 230 struct ncr5380_softc *ncr_sc; 231 { 232 struct si_softc *sc = (struct si_softc *)ncr_sc; 233 struct sci_req *sr = ncr_sc->sc_current; 234 struct scsipi_xfer *xs = sr->sr_xs; 235 struct si_dma_handle *dh; 236 int xlen, i; 237 238 #ifdef DIAGNOSTIC 239 if (sr->sr_dma_hand != NULL) 240 panic("si_dma_alloc: already have DMA handle"); 241 #endif 242 243 /* Polled transfers shouldn't allocate a DMA handle. */ 244 if (sr->sr_flags & SR_IMMED) 245 return; 246 247 xlen = ncr_sc->sc_datalen; 248 249 /* Make sure our caller checked sc_min_dma_len. */ 250 if (xlen < MIN_DMA_LEN) 251 panic("si_dma_alloc: len=0x%x\n", xlen); 252 253 /* 254 * Find free PDMA handle. Guaranteed to find one since we 255 * have as many PDMA handles as the driver has processes. 256 * (instances?) 257 */ 258 for (i = 0; i < SCI_OPENINGS; i++) { 259 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 260 goto found; 261 } 262 panic("sbc: no free PDMA handles"); 263 found: 264 dh = &sc->ncr_dma[i]; 265 dh->dh_flags = SIDH_BUSY; 266 dh->dh_addr = ncr_sc->sc_dataptr; 267 dh->dh_len = xlen; 268 dh->dh_proc = xs->bp->b_proc; 269 270 /* Remember dest buffer parameters */ 271 if (xs->xs_control & XS_CTL_DATA_OUT) 272 dh->dh_flags |= SIDH_OUT; 273 274 sr->sr_dma_hand = dh; 275 } 276 277 void 278 si_dma_free(ncr_sc) 279 struct ncr5380_softc *ncr_sc; 280 { 281 struct sci_req *sr = ncr_sc->sc_current; 282 struct si_dma_handle *dh = sr->sr_dma_hand; 283 284 if (dh->dh_flags & SIDH_BUSY) 285 dh->dh_flags = 0; 286 else 287 printf("si_dma_free: free'ing unused buffer\n"); 288 289 sr->sr_dma_hand = NULL; 290 } 291 292 void 293 si_dma_setup(ncr_sc) 294 struct ncr5380_softc *ncr_sc; 295 { 296 /* Do nothing here */ 297 } 298 299 void 300 si_dma_start(ncr_sc) 301 struct ncr5380_softc *ncr_sc; 302 { 303 struct si_softc *sc = (struct si_softc *)ncr_sc; 304 struct sci_req *sr = ncr_sc->sc_current; 305 struct si_dma_handle *dh = sr->sr_dma_hand; 306 307 /* 308 * Set the VAX-DMA-specific registers, and copy the data if 309 * it is directed "outbound". 310 */ 311 if (dh->dh_flags & SIDH_OUT) { 312 if ((vaddr_t)dh->dh_addr & KERNBASE) 313 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 314 else 315 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 316 sc->ncr_addr, dh->dh_len); 317 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 318 sc->ncr_dmadir, 0); 319 } else { 320 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 321 sc->ncr_dmadir, 1); 322 } 323 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 324 sc->ncr_dmacount, -dh->dh_len); 325 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 326 sc->ncr_dmaaddr, sc->ncr_off); 327 /* 328 * Now from the 5380-internal DMA registers. 329 */ 330 if (dh->dh_flags & SIDH_OUT) { 331 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 332 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 333 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 334 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 335 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 336 } else { 337 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 338 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 339 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 340 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 341 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 342 } 343 ncr_sc->sc_state |= NCR_DOINGDMA; 344 } 345 346 /* 347 * When? 348 */ 349 void 350 si_dma_poll(ncr_sc) 351 struct ncr5380_softc *ncr_sc; 352 { 353 printf("si_dma_poll\n"); 354 } 355 356 /* 357 * When? 358 */ 359 void 360 si_dma_eop(ncr_sc) 361 struct ncr5380_softc *ncr_sc; 362 { 363 printf("si_dma_eop\n"); 364 } 365 366 void 367 si_dma_stop(ncr_sc) 368 struct ncr5380_softc *ncr_sc; 369 { 370 struct si_softc *sc = (struct si_softc *)ncr_sc; 371 struct sci_req *sr = ncr_sc->sc_current; 372 struct si_dma_handle *dh = sr->sr_dma_hand; 373 int count, i; 374 375 if (ncr_sc->sc_state & NCR_DOINGDMA) 376 ncr_sc->sc_state &= ~NCR_DOINGDMA; 377 378 /* 379 * Sometimes the FIFO buffer isn't drained when the 380 * interrupt is posted. Just loop here and hope that 381 * it will drain soon. 382 */ 383 for (i = 0; i < 20000; i++) { 384 count = bus_space_read_4(ncr_sc->sc_regt, 385 ncr_sc->sc_regh, sc->ncr_dmacount); 386 if (count == 0) 387 break; 388 DELAY(100); 389 } 390 if (count == 0) { 391 if (((dh->dh_flags & SIDH_OUT) == 0)) { 392 if ((vaddr_t)dh->dh_addr & KERNBASE) 393 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 394 else 395 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 396 dh->dh_addr, dh->dh_len); 397 398 } 399 ncr_sc->sc_dataptr += dh->dh_len; 400 ncr_sc->sc_datalen -= dh->dh_len; 401 } 402 403 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 404 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 405 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 406 } 407
Indexes created Tue Sep 30 20:09:53 GMT 2025