ncr.c revision 1.27
1 /* $NetBSD: ncr.c,v 1.27 2000/05/27 10:12:45 ragge Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/cpu.h> 76 #include <machine/vsbus.h> 77 #include <machine/bus.h> 78 #include <machine/sid.h> 79 #include <machine/scb.h> 80 #include <machine/clock.h> 81 82 #include "ioconf.h" 83 84 #define MIN_DMA_LEN 128 85 86 struct si_dma_handle { 87 int dh_flags; 88 #define SIDH_BUSY 1 89 #define SIDH_OUT 2 90 caddr_t dh_addr; 91 int dh_len; 92 struct proc *dh_proc; 93 }; 94 95 struct si_softc { 96 struct ncr5380_softc ncr_sc; 97 caddr_t ncr_addr; 98 int ncr_off; 99 int ncr_dmaaddr; 100 int ncr_dmacount; 101 int ncr_dmadir; 102 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 103 }; 104 105 static int si_match(struct device *, struct cfdata *, void *); 106 static void si_attach(struct device *, struct device *, void *); 107 static void si_minphys(struct buf *); 108 109 static void si_dma_alloc __P((struct ncr5380_softc *)); 110 static void si_dma_free __P((struct ncr5380_softc *)); 111 static void si_dma_setup __P((struct ncr5380_softc *)); 112 static void si_dma_start __P((struct ncr5380_softc *)); 113 static void si_dma_poll __P((struct ncr5380_softc *)); 114 static void si_dma_eop __P((struct ncr5380_softc *)); 115 static void si_dma_stop __P((struct ncr5380_softc *)); 116 117 118 struct cfattach ncr_ca = { 119 sizeof(struct si_softc), si_match, si_attach 120 }; 121 122 static int 123 si_match(parent, cf, aux) 124 struct device *parent; 125 struct cfdata *cf; 126 void *aux; 127 { 128 struct vsbus_attach_args *va = aux; 129 volatile char *si_csr = (char *) va->va_addr; 130 131 if (vax_boardtype == VAX_BTYP_49) 132 return 0; 133 /* This is the way Linux autoprobes the interrupt MK-990321 */ 134 si_csr[12] = 0; 135 si_csr[16] = 0x80; 136 si_csr[0] = 0x80; 137 si_csr[4] = 5; /* 0xcf */ 138 DELAY(100000); 139 return 1; 140 } 141 142 static void 143 si_attach(parent, self, aux) 144 struct device *parent, *self; 145 void *aux; 146 { 147 struct vsbus_attach_args *va = aux; 148 struct si_softc *sc = (struct si_softc *) self; 149 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 150 int tweak, target; 151 152 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, SCB_ISTACK); 153 154 /* 155 * DMA area mapin. 156 * On VS3100, split the 128K block between the two devices. 157 * On VS2000, don't care for now. 158 */ 159 #define DMASIZE (64*1024) 160 if (vax_boardtype != VAX_BTYP_410) { 161 if (va->va_paddr & 0x100) /* Magic */ 162 sc->ncr_off = DMASIZE; 163 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 164 165 ioaccess((vaddr_t)sc->ncr_addr, 166 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 167 168 /* 169 * MD function pointers used by the MI code. 170 */ 171 ncr_sc->sc_dma_alloc = si_dma_alloc; 172 ncr_sc->sc_dma_free = si_dma_free; 173 ncr_sc->sc_dma_setup = si_dma_setup; 174 ncr_sc->sc_dma_start = si_dma_start; 175 ncr_sc->sc_dma_poll = si_dma_poll; 176 ncr_sc->sc_dma_eop = si_dma_eop; 177 ncr_sc->sc_dma_stop = si_dma_stop; 178 179 /* DMA control register offsets */ 180 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 181 sc->ncr_dmacount = 64; /* DMA count register */ 182 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 183 } 184 ncr_sc->sc_pio_out = ncr5380_pio_out; 185 ncr_sc->sc_pio_in = ncr5380_pio_in; 186 187 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 188 189 /* 190 * Initialize fields used by the MI code. 191 */ 192 /* ncr_sc->sc_regt = Unused on VAX */ 193 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 194 195 /* Register offsets */ 196 ncr_sc->sci_r0 = 0; 197 ncr_sc->sci_r1 = 4; 198 ncr_sc->sci_r2 = 8; 199 ncr_sc->sci_r3 = 12; 200 ncr_sc->sci_r4 = 16; 201 ncr_sc->sci_r5 = 20; 202 ncr_sc->sci_r6 = 24; 203 ncr_sc->sci_r7 = 28; 204 205 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 206 207 ncr_sc->sc_no_disconnect = 0xff; 208 209 /* 210 * Get the SCSI chip target address out of NVRAM. 211 * This do not apply to the VS2000. 212 */ 213 tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0); 214 if (vax_boardtype == VAX_BTYP_410) 215 target = 7; 216 else 217 target = (clk_page[0xbc/2] >> tweak) & 7; 218 219 printf("\n%s: NCR5380, SCSI ID %d\n", ncr_sc->sc_dev.dv_xname, target); 220 221 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 222 ncr_sc->sc_link.scsipi_scsi.adapter_target = target; 223 /* 224 * Initialize si board itself. 225 */ 226 ncr5380_attach(ncr_sc); 227 } 228 229 /* 230 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 231 */ 232 static void 233 si_minphys(struct buf *bp) 234 { 235 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 236 bp->b_bcount = (16*1024); 237 else if (bp->b_bcount > MAXPHYS) 238 bp->b_bcount = MAXPHYS; 239 } 240 241 void 242 si_dma_alloc(ncr_sc) 243 struct ncr5380_softc *ncr_sc; 244 { 245 struct si_softc *sc = (struct si_softc *)ncr_sc; 246 struct sci_req *sr = ncr_sc->sc_current; 247 struct scsipi_xfer *xs = sr->sr_xs; 248 struct si_dma_handle *dh; 249 int xlen, i; 250 251 #ifdef DIAGNOSTIC 252 if (sr->sr_dma_hand != NULL) 253 panic("si_dma_alloc: already have DMA handle"); 254 #endif 255 256 /* Polled transfers shouldn't allocate a DMA handle. */ 257 if (sr->sr_flags & SR_IMMED) 258 return; 259 260 xlen = ncr_sc->sc_datalen; 261 262 /* Make sure our caller checked sc_min_dma_len. */ 263 if (xlen < MIN_DMA_LEN) 264 panic("si_dma_alloc: len=0x%x\n", xlen); 265 266 /* 267 * Find free PDMA handle. Guaranteed to find one since we 268 * have as many PDMA handles as the driver has processes. 269 * (instances?) 270 */ 271 for (i = 0; i < SCI_OPENINGS; i++) { 272 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 273 goto found; 274 } 275 panic("sbc: no free PDMA handles"); 276 found: 277 dh = &sc->ncr_dma[i]; 278 dh->dh_flags = SIDH_BUSY; 279 dh->dh_addr = ncr_sc->sc_dataptr; 280 dh->dh_len = xlen; 281 dh->dh_proc = xs->bp->b_proc; 282 283 /* Remember dest buffer parameters */ 284 if (xs->xs_control & XS_CTL_DATA_OUT) 285 dh->dh_flags |= SIDH_OUT; 286 287 sr->sr_dma_hand = dh; 288 } 289 290 void 291 si_dma_free(ncr_sc) 292 struct ncr5380_softc *ncr_sc; 293 { 294 struct sci_req *sr = ncr_sc->sc_current; 295 struct si_dma_handle *dh = sr->sr_dma_hand; 296 297 if (dh->dh_flags & SIDH_BUSY) 298 dh->dh_flags = 0; 299 else 300 printf("si_dma_free: free'ing unused buffer\n"); 301 302 sr->sr_dma_hand = NULL; 303 } 304 305 void 306 si_dma_setup(ncr_sc) 307 struct ncr5380_softc *ncr_sc; 308 { 309 /* Do nothing here */ 310 } 311 312 void 313 si_dma_start(ncr_sc) 314 struct ncr5380_softc *ncr_sc; 315 { 316 struct si_softc *sc = (struct si_softc *)ncr_sc; 317 struct sci_req *sr = ncr_sc->sc_current; 318 struct si_dma_handle *dh = sr->sr_dma_hand; 319 320 /* 321 * Set the VAX-DMA-specific registers, and copy the data if 322 * it is directed "outbound". 323 */ 324 if (dh->dh_flags & SIDH_OUT) { 325 if ((vaddr_t)dh->dh_addr & KERNBASE) 326 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 327 else 328 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 329 sc->ncr_addr, dh->dh_len); 330 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 331 sc->ncr_dmadir, 0); 332 } else { 333 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 334 sc->ncr_dmadir, 1); 335 } 336 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 337 sc->ncr_dmacount, -dh->dh_len); 338 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 339 sc->ncr_dmaaddr, sc->ncr_off); 340 /* 341 * Now from the 5380-internal DMA registers. 342 */ 343 if (dh->dh_flags & SIDH_OUT) { 344 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 345 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 346 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 347 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 348 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 349 } else { 350 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 351 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 352 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 353 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 354 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 355 } 356 ncr_sc->sc_state |= NCR_DOINGDMA; 357 } 358 359 /* 360 * When? 361 */ 362 void 363 si_dma_poll(ncr_sc) 364 struct ncr5380_softc *ncr_sc; 365 { 366 printf("si_dma_poll\n"); 367 } 368 369 /* 370 * When? 371 */ 372 void 373 si_dma_eop(ncr_sc) 374 struct ncr5380_softc *ncr_sc; 375 { 376 printf("si_dma_eop\n"); 377 } 378 379 void 380 si_dma_stop(ncr_sc) 381 struct ncr5380_softc *ncr_sc; 382 { 383 struct si_softc *sc = (struct si_softc *)ncr_sc; 384 struct sci_req *sr = ncr_sc->sc_current; 385 struct si_dma_handle *dh = sr->sr_dma_hand; 386 int count, i; 387 388 if (ncr_sc->sc_state & NCR_DOINGDMA) 389 ncr_sc->sc_state &= ~NCR_DOINGDMA; 390 391 /* 392 * Sometimes the FIFO buffer isn't drained when the 393 * interrupt is posted. Just loop here and hope that 394 * it will drain soon. 395 */ 396 for (i = 0; i < 20000; i++) { 397 count = bus_space_read_4(ncr_sc->sc_regt, 398 ncr_sc->sc_regh, sc->ncr_dmacount); 399 if (count == 0) 400 break; 401 DELAY(100); 402 } 403 if (count == 0) { 404 if (((dh->dh_flags & SIDH_OUT) == 0)) { 405 if ((vaddr_t)dh->dh_addr & KERNBASE) 406 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 407 else 408 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 409 dh->dh_addr, dh->dh_len); 410 411 } 412 ncr_sc->sc_dataptr += dh->dh_len; 413 ncr_sc->sc_datalen -= dh->dh_len; 414 } 415 416 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 417 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 418 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 419 } 420
Indexes created Tue Sep 30 20:09:53 GMT 2025