ncr.c revision 1.28
1 /* $NetBSD: ncr.c,v 1.28 2000/06/04 02:19:29 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/cpu.h> 76 #include <machine/vsbus.h> 77 #include <machine/bus.h> 78 #include <machine/sid.h> 79 #include <machine/scb.h> 80 #include <machine/clock.h> 81 82 #include "ioconf.h" 83 84 #define MIN_DMA_LEN 128 85 86 struct si_dma_handle { 87 int dh_flags; 88 #define SIDH_BUSY 1 89 #define SIDH_OUT 2 90 caddr_t dh_addr; 91 int dh_len; 92 struct proc *dh_proc; 93 }; 94 95 struct si_softc { 96 struct ncr5380_softc ncr_sc; 97 struct evcnt ncr_intrcnt; 98 caddr_t ncr_addr; 99 int ncr_off; 100 int ncr_dmaaddr; 101 int ncr_dmacount; 102 int ncr_dmadir; 103 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 104 }; 105 106 static int si_match(struct device *, struct cfdata *, void *); 107 static void si_attach(struct device *, struct device *, void *); 108 static void si_minphys(struct buf *); 109 110 static void si_dma_alloc __P((struct ncr5380_softc *)); 111 static void si_dma_free __P((struct ncr5380_softc *)); 112 static void si_dma_setup __P((struct ncr5380_softc *)); 113 static void si_dma_start __P((struct ncr5380_softc *)); 114 static void si_dma_poll __P((struct ncr5380_softc *)); 115 static void si_dma_eop __P((struct ncr5380_softc *)); 116 static void si_dma_stop __P((struct ncr5380_softc *)); 117 118 119 struct cfattach ncr_ca = { 120 sizeof(struct si_softc), si_match, si_attach 121 }; 122 123 static int 124 si_match(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 struct vsbus_attach_args *va = aux; 130 volatile char *si_csr = (char *) va->va_addr; 131 132 if (vax_boardtype == VAX_BTYP_49) 133 return 0; 134 /* This is the way Linux autoprobes the interrupt MK-990321 */ 135 si_csr[12] = 0; 136 si_csr[16] = 0x80; 137 si_csr[0] = 0x80; 138 si_csr[4] = 5; /* 0xcf */ 139 DELAY(100000); 140 return 1; 141 } 142 143 static void 144 si_attach(parent, self, aux) 145 struct device *parent, *self; 146 void *aux; 147 { 148 struct vsbus_attach_args *va = aux; 149 struct si_softc *sc = (struct si_softc *) self; 150 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 151 int tweak, target; 152 153 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, 154 SCB_ISTACK, &sc->ncr_intrcnt); 155 156 /* 157 * DMA area mapin. 158 * On VS3100, split the 128K block between the two devices. 159 * On VS2000, don't care for now. 160 */ 161 #define DMASIZE (64*1024) 162 if (vax_boardtype != VAX_BTYP_410) { 163 if (va->va_paddr & 0x100) /* Magic */ 164 sc->ncr_off = DMASIZE; 165 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 166 167 ioaccess((vaddr_t)sc->ncr_addr, 168 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 169 170 /* 171 * MD function pointers used by the MI code. 172 */ 173 ncr_sc->sc_dma_alloc = si_dma_alloc; 174 ncr_sc->sc_dma_free = si_dma_free; 175 ncr_sc->sc_dma_setup = si_dma_setup; 176 ncr_sc->sc_dma_start = si_dma_start; 177 ncr_sc->sc_dma_poll = si_dma_poll; 178 ncr_sc->sc_dma_eop = si_dma_eop; 179 ncr_sc->sc_dma_stop = si_dma_stop; 180 181 /* DMA control register offsets */ 182 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 183 sc->ncr_dmacount = 64; /* DMA count register */ 184 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 185 } 186 ncr_sc->sc_pio_out = ncr5380_pio_out; 187 ncr_sc->sc_pio_in = ncr5380_pio_in; 188 189 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 190 191 /* 192 * Initialize fields used by the MI code. 193 */ 194 /* ncr_sc->sc_regt = Unused on VAX */ 195 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 196 197 /* Register offsets */ 198 ncr_sc->sci_r0 = 0; 199 ncr_sc->sci_r1 = 4; 200 ncr_sc->sci_r2 = 8; 201 ncr_sc->sci_r3 = 12; 202 ncr_sc->sci_r4 = 16; 203 ncr_sc->sci_r5 = 20; 204 ncr_sc->sci_r6 = 24; 205 ncr_sc->sci_r7 = 28; 206 207 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 208 209 ncr_sc->sc_no_disconnect = 0xff; 210 211 /* 212 * Get the SCSI chip target address out of NVRAM. 213 * This do not apply to the VS2000. 214 */ 215 tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0); 216 if (vax_boardtype == VAX_BTYP_410) 217 target = 7; 218 else 219 target = (clk_page[0xbc/2] >> tweak) & 7; 220 221 printf("\n%s: NCR5380, SCSI ID %d\n", ncr_sc->sc_dev.dv_xname, target); 222 223 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 224 ncr_sc->sc_link.scsipi_scsi.adapter_target = target; 225 /* 226 * Initialize si board itself. 227 */ 228 ncr5380_attach(ncr_sc); 229 } 230 231 /* 232 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 233 */ 234 static void 235 si_minphys(struct buf *bp) 236 { 237 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 238 bp->b_bcount = (16*1024); 239 else if (bp->b_bcount > MAXPHYS) 240 bp->b_bcount = MAXPHYS; 241 } 242 243 void 244 si_dma_alloc(ncr_sc) 245 struct ncr5380_softc *ncr_sc; 246 { 247 struct si_softc *sc = (struct si_softc *)ncr_sc; 248 struct sci_req *sr = ncr_sc->sc_current; 249 struct scsipi_xfer *xs = sr->sr_xs; 250 struct si_dma_handle *dh; 251 int xlen, i; 252 253 #ifdef DIAGNOSTIC 254 if (sr->sr_dma_hand != NULL) 255 panic("si_dma_alloc: already have DMA handle"); 256 #endif 257 258 /* Polled transfers shouldn't allocate a DMA handle. */ 259 if (sr->sr_flags & SR_IMMED) 260 return; 261 262 xlen = ncr_sc->sc_datalen; 263 264 /* Make sure our caller checked sc_min_dma_len. */ 265 if (xlen < MIN_DMA_LEN) 266 panic("si_dma_alloc: len=0x%x\n", xlen); 267 268 /* 269 * Find free PDMA handle. Guaranteed to find one since we 270 * have as many PDMA handles as the driver has processes. 271 * (instances?) 272 */ 273 for (i = 0; i < SCI_OPENINGS; i++) { 274 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 275 goto found; 276 } 277 panic("sbc: no free PDMA handles"); 278 found: 279 dh = &sc->ncr_dma[i]; 280 dh->dh_flags = SIDH_BUSY; 281 dh->dh_addr = ncr_sc->sc_dataptr; 282 dh->dh_len = xlen; 283 dh->dh_proc = xs->bp->b_proc; 284 285 /* Remember dest buffer parameters */ 286 if (xs->xs_control & XS_CTL_DATA_OUT) 287 dh->dh_flags |= SIDH_OUT; 288 289 sr->sr_dma_hand = dh; 290 } 291 292 void 293 si_dma_free(ncr_sc) 294 struct ncr5380_softc *ncr_sc; 295 { 296 struct sci_req *sr = ncr_sc->sc_current; 297 struct si_dma_handle *dh = sr->sr_dma_hand; 298 299 if (dh->dh_flags & SIDH_BUSY) 300 dh->dh_flags = 0; 301 else 302 printf("si_dma_free: free'ing unused buffer\n"); 303 304 sr->sr_dma_hand = NULL; 305 } 306 307 void 308 si_dma_setup(ncr_sc) 309 struct ncr5380_softc *ncr_sc; 310 { 311 /* Do nothing here */ 312 } 313 314 void 315 si_dma_start(ncr_sc) 316 struct ncr5380_softc *ncr_sc; 317 { 318 struct si_softc *sc = (struct si_softc *)ncr_sc; 319 struct sci_req *sr = ncr_sc->sc_current; 320 struct si_dma_handle *dh = sr->sr_dma_hand; 321 322 /* 323 * Set the VAX-DMA-specific registers, and copy the data if 324 * it is directed "outbound". 325 */ 326 if (dh->dh_flags & SIDH_OUT) { 327 if ((vaddr_t)dh->dh_addr & KERNBASE) 328 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 329 else 330 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 331 sc->ncr_addr, dh->dh_len); 332 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 333 sc->ncr_dmadir, 0); 334 } else { 335 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 336 sc->ncr_dmadir, 1); 337 } 338 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 339 sc->ncr_dmacount, -dh->dh_len); 340 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 341 sc->ncr_dmaaddr, sc->ncr_off); 342 /* 343 * Now from the 5380-internal DMA registers. 344 */ 345 if (dh->dh_flags & SIDH_OUT) { 346 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 347 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 348 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 349 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 350 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 351 } else { 352 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 353 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 354 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 355 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 356 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 357 } 358 ncr_sc->sc_state |= NCR_DOINGDMA; 359 } 360 361 /* 362 * When? 363 */ 364 void 365 si_dma_poll(ncr_sc) 366 struct ncr5380_softc *ncr_sc; 367 { 368 printf("si_dma_poll\n"); 369 } 370 371 /* 372 * When? 373 */ 374 void 375 si_dma_eop(ncr_sc) 376 struct ncr5380_softc *ncr_sc; 377 { 378 printf("si_dma_eop\n"); 379 } 380 381 void 382 si_dma_stop(ncr_sc) 383 struct ncr5380_softc *ncr_sc; 384 { 385 struct si_softc *sc = (struct si_softc *)ncr_sc; 386 struct sci_req *sr = ncr_sc->sc_current; 387 struct si_dma_handle *dh = sr->sr_dma_hand; 388 int count, i; 389 390 if (ncr_sc->sc_state & NCR_DOINGDMA) 391 ncr_sc->sc_state &= ~NCR_DOINGDMA; 392 393 /* 394 * Sometimes the FIFO buffer isn't drained when the 395 * interrupt is posted. Just loop here and hope that 396 * it will drain soon. 397 */ 398 for (i = 0; i < 20000; i++) { 399 count = bus_space_read_4(ncr_sc->sc_regt, 400 ncr_sc->sc_regh, sc->ncr_dmacount); 401 if (count == 0) 402 break; 403 DELAY(100); 404 } 405 if (count == 0) { 406 if (((dh->dh_flags & SIDH_OUT) == 0)) { 407 if ((vaddr_t)dh->dh_addr & KERNBASE) 408 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 409 else 410 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 411 dh->dh_addr, dh->dh_len); 412 413 } 414 ncr_sc->sc_dataptr += dh->dh_len; 415 ncr_sc->sc_datalen -= dh->dh_len; 416 } 417 418 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 419 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 420 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 421 } 422
Indexes created Tue Sep 30 20:09:53 GMT 2025