ncr.c revision 1.30
1 /* $NetBSD: ncr.c,v 1.30 2000/06/05 00:09:21 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/cpu.h> 76 #include <machine/vsbus.h> 77 #include <machine/bus.h> 78 #include <machine/sid.h> 79 #include <machine/scb.h> 80 #include <machine/clock.h> 81 82 #include "ioconf.h" 83 84 #define MIN_DMA_LEN 128 85 86 struct si_dma_handle { 87 int dh_flags; 88 #define SIDH_BUSY 1 89 #define SIDH_OUT 2 90 caddr_t dh_addr; 91 int dh_len; 92 struct proc *dh_proc; 93 }; 94 95 struct si_softc { 96 struct ncr5380_softc ncr_sc; 97 struct evcnt ncr_intrcnt; 98 caddr_t ncr_addr; 99 int ncr_off; 100 int ncr_dmaaddr; 101 int ncr_dmacount; 102 int ncr_dmadir; 103 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 104 }; 105 106 static int si_match(struct device *, struct cfdata *, void *); 107 static void si_attach(struct device *, struct device *, void *); 108 static void si_minphys(struct buf *); 109 110 static void si_dma_alloc __P((struct ncr5380_softc *)); 111 static void si_dma_free __P((struct ncr5380_softc *)); 112 static void si_dma_setup __P((struct ncr5380_softc *)); 113 static void si_dma_start __P((struct ncr5380_softc *)); 114 static void si_dma_poll __P((struct ncr5380_softc *)); 115 static void si_dma_eop __P((struct ncr5380_softc *)); 116 static void si_dma_stop __P((struct ncr5380_softc *)); 117 118 119 struct cfattach ncr_ca = { 120 sizeof(struct si_softc), si_match, si_attach 121 }; 122 123 static int 124 si_match(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 struct vsbus_attach_args *va = aux; 130 volatile char *si_csr = (char *) va->va_addr; 131 132 if (vax_boardtype == VAX_BTYP_49) 133 return 0; 134 /* This is the way Linux autoprobes the interrupt MK-990321 */ 135 si_csr[12] = 0; 136 si_csr[16] = 0x80; 137 si_csr[0] = 0x80; 138 si_csr[4] = 5; /* 0xcf */ 139 DELAY(100000); 140 return 1; 141 } 142 143 static void 144 si_attach(parent, self, aux) 145 struct device *parent, *self; 146 void *aux; 147 { 148 struct vsbus_attach_args *va = aux; 149 struct si_softc *sc = (struct si_softc *) self; 150 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 151 int tweak, target; 152 153 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, 154 SCB_ISTACK, &sc->ncr_intrcnt); 155 evcnt_attach_dynamic(&sc->ncr_intrcnt, EVCNT_TYPE_INTR, NULL, 156 self->dv_xname, "intr"); 157 158 /* 159 * DMA area mapin. 160 * On VS3100, split the 128K block between the two devices. 161 * On VS2000, don't care for now. 162 */ 163 #define DMASIZE (64*1024) 164 if (vax_boardtype != VAX_BTYP_410) { 165 if (va->va_paddr & 0x100) /* Magic */ 166 sc->ncr_off = DMASIZE; 167 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 168 169 ioaccess((vaddr_t)sc->ncr_addr, 170 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 171 172 /* 173 * MD function pointers used by the MI code. 174 */ 175 ncr_sc->sc_dma_alloc = si_dma_alloc; 176 ncr_sc->sc_dma_free = si_dma_free; 177 ncr_sc->sc_dma_setup = si_dma_setup; 178 ncr_sc->sc_dma_start = si_dma_start; 179 ncr_sc->sc_dma_poll = si_dma_poll; 180 ncr_sc->sc_dma_eop = si_dma_eop; 181 ncr_sc->sc_dma_stop = si_dma_stop; 182 183 /* DMA control register offsets */ 184 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 185 sc->ncr_dmacount = 64; /* DMA count register */ 186 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 187 } 188 ncr_sc->sc_pio_out = ncr5380_pio_out; 189 ncr_sc->sc_pio_in = ncr5380_pio_in; 190 191 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 192 193 /* 194 * Initialize fields used by the MI code. 195 */ 196 /* ncr_sc->sc_regt = Unused on VAX */ 197 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 198 199 /* Register offsets */ 200 ncr_sc->sci_r0 = 0; 201 ncr_sc->sci_r1 = 4; 202 ncr_sc->sci_r2 = 8; 203 ncr_sc->sci_r3 = 12; 204 ncr_sc->sci_r4 = 16; 205 ncr_sc->sci_r5 = 20; 206 ncr_sc->sci_r6 = 24; 207 ncr_sc->sci_r7 = 28; 208 209 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 210 211 ncr_sc->sc_no_disconnect = 0xff; 212 213 /* 214 * Get the SCSI chip target address out of NVRAM. 215 * This do not apply to the VS2000. 216 */ 217 tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0); 218 if (vax_boardtype == VAX_BTYP_410) 219 target = 7; 220 else 221 target = (clk_page[0xbc/2] >> tweak) & 7; 222 223 printf("\n%s: NCR5380, SCSI ID %d\n", ncr_sc->sc_dev.dv_xname, target); 224 225 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 226 ncr_sc->sc_link.scsipi_scsi.adapter_target = target; 227 /* 228 * Initialize si board itself. 229 */ 230 ncr5380_attach(ncr_sc); 231 } 232 233 /* 234 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 235 */ 236 static void 237 si_minphys(struct buf *bp) 238 { 239 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 240 bp->b_bcount = (16*1024); 241 else if (bp->b_bcount > MAXPHYS) 242 bp->b_bcount = MAXPHYS; 243 } 244 245 void 246 si_dma_alloc(ncr_sc) 247 struct ncr5380_softc *ncr_sc; 248 { 249 struct si_softc *sc = (struct si_softc *)ncr_sc; 250 struct sci_req *sr = ncr_sc->sc_current; 251 struct scsipi_xfer *xs = sr->sr_xs; 252 struct si_dma_handle *dh; 253 int xlen, i; 254 255 #ifdef DIAGNOSTIC 256 if (sr->sr_dma_hand != NULL) 257 panic("si_dma_alloc: already have DMA handle"); 258 #endif 259 260 /* Polled transfers shouldn't allocate a DMA handle. */ 261 if (sr->sr_flags & SR_IMMED) 262 return; 263 264 xlen = ncr_sc->sc_datalen; 265 266 /* Make sure our caller checked sc_min_dma_len. */ 267 if (xlen < MIN_DMA_LEN) 268 panic("si_dma_alloc: len=0x%x\n", xlen); 269 270 /* 271 * Find free PDMA handle. Guaranteed to find one since we 272 * have as many PDMA handles as the driver has processes. 273 * (instances?) 274 */ 275 for (i = 0; i < SCI_OPENINGS; i++) { 276 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 277 goto found; 278 } 279 panic("sbc: no free PDMA handles"); 280 found: 281 dh = &sc->ncr_dma[i]; 282 dh->dh_flags = SIDH_BUSY; 283 dh->dh_addr = ncr_sc->sc_dataptr; 284 dh->dh_len = xlen; 285 dh->dh_proc = xs->bp->b_proc; 286 287 /* Remember dest buffer parameters */ 288 if (xs->xs_control & XS_CTL_DATA_OUT) 289 dh->dh_flags |= SIDH_OUT; 290 291 sr->sr_dma_hand = dh; 292 } 293 294 void 295 si_dma_free(ncr_sc) 296 struct ncr5380_softc *ncr_sc; 297 { 298 struct sci_req *sr = ncr_sc->sc_current; 299 struct si_dma_handle *dh = sr->sr_dma_hand; 300 301 if (dh->dh_flags & SIDH_BUSY) 302 dh->dh_flags = 0; 303 else 304 printf("si_dma_free: free'ing unused buffer\n"); 305 306 sr->sr_dma_hand = NULL; 307 } 308 309 void 310 si_dma_setup(ncr_sc) 311 struct ncr5380_softc *ncr_sc; 312 { 313 /* Do nothing here */ 314 } 315 316 void 317 si_dma_start(ncr_sc) 318 struct ncr5380_softc *ncr_sc; 319 { 320 struct si_softc *sc = (struct si_softc *)ncr_sc; 321 struct sci_req *sr = ncr_sc->sc_current; 322 struct si_dma_handle *dh = sr->sr_dma_hand; 323 324 /* 325 * Set the VAX-DMA-specific registers, and copy the data if 326 * it is directed "outbound". 327 */ 328 if (dh->dh_flags & SIDH_OUT) { 329 if ((vaddr_t)dh->dh_addr & KERNBASE) 330 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 331 else 332 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 333 sc->ncr_addr, dh->dh_len); 334 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 335 sc->ncr_dmadir, 0); 336 } else { 337 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 338 sc->ncr_dmadir, 1); 339 } 340 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 341 sc->ncr_dmacount, -dh->dh_len); 342 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 343 sc->ncr_dmaaddr, sc->ncr_off); 344 /* 345 * Now from the 5380-internal DMA registers. 346 */ 347 if (dh->dh_flags & SIDH_OUT) { 348 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 349 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 350 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 351 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 352 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 353 } else { 354 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 355 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 356 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 357 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 358 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 359 } 360 ncr_sc->sc_state |= NCR_DOINGDMA; 361 } 362 363 /* 364 * When? 365 */ 366 void 367 si_dma_poll(ncr_sc) 368 struct ncr5380_softc *ncr_sc; 369 { 370 printf("si_dma_poll\n"); 371 } 372 373 /* 374 * When? 375 */ 376 void 377 si_dma_eop(ncr_sc) 378 struct ncr5380_softc *ncr_sc; 379 { 380 printf("si_dma_eop\n"); 381 } 382 383 void 384 si_dma_stop(ncr_sc) 385 struct ncr5380_softc *ncr_sc; 386 { 387 struct si_softc *sc = (struct si_softc *)ncr_sc; 388 struct sci_req *sr = ncr_sc->sc_current; 389 struct si_dma_handle *dh = sr->sr_dma_hand; 390 int count, i; 391 392 if (ncr_sc->sc_state & NCR_DOINGDMA) 393 ncr_sc->sc_state &= ~NCR_DOINGDMA; 394 395 /* 396 * Sometimes the FIFO buffer isn't drained when the 397 * interrupt is posted. Just loop here and hope that 398 * it will drain soon. 399 */ 400 for (i = 0; i < 20000; i++) { 401 count = bus_space_read_4(ncr_sc->sc_regt, 402 ncr_sc->sc_regh, sc->ncr_dmacount); 403 if (count == 0) 404 break; 405 DELAY(100); 406 } 407 if (count == 0) { 408 if (((dh->dh_flags & SIDH_OUT) == 0)) { 409 if ((vaddr_t)dh->dh_addr & KERNBASE) 410 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 411 else 412 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 413 dh->dh_addr, dh->dh_len); 414 415 } 416 ncr_sc->sc_dataptr += dh->dh_len; 417 ncr_sc->sc_datalen -= dh->dh_len; 418 } 419 420 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 421 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 422 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 423 } 424
Indexes created Tue Sep 30 20:09:53 GMT 2025