ncr.c revision 1.31
1 /* $NetBSD: ncr.c,v 1.31 2000/06/19 04:22:17 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Note: Only PIO transfers for now which implicates very bad 44 * performance. DMA support will come soon. 45 * 46 * Jens A. Nilsson. 47 * 48 * Credits: 49 * 50 * This code is based on arch/sun3/dev/si* 51 * Written by David Jones, Gordon Ross, and Adam Glass. 52 */ 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <vm/vm.h> 65 #include <vm/vm_kern.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsipi_debug.h> 70 #include <dev/scsipi/scsiconf.h> 71 72 #include <dev/ic/ncr5380reg.h> 73 #include <dev/ic/ncr5380var.h> 74 75 #include <machine/cpu.h> 76 #include <machine/vsbus.h> 77 #include <machine/bus.h> 78 #include <machine/sid.h> 79 #include <machine/scb.h> 80 #include <machine/clock.h> 81 82 #include "ioconf.h" 83 84 #define MIN_DMA_LEN 128 85 86 struct si_dma_handle { 87 int dh_flags; 88 #define SIDH_BUSY 1 89 #define SIDH_OUT 2 90 caddr_t dh_addr; 91 int dh_len; 92 struct proc *dh_proc; 93 }; 94 95 struct si_softc { 96 struct ncr5380_softc ncr_sc; 97 struct evcnt ncr_intrcnt; 98 caddr_t ncr_addr; 99 int ncr_off; 100 int ncr_dmaaddr; 101 int ncr_dmacount; 102 int ncr_dmadir; 103 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 104 }; 105 106 static int si_vsbus_match(struct device *, struct cfdata *, void *); 107 static void si_vsbus_attach(struct device *, struct device *, void *); 108 static void si_minphys(struct buf *); 109 110 static void si_dma_alloc(struct ncr5380_softc *); 111 static void si_dma_free(struct ncr5380_softc *); 112 static void si_dma_setup(struct ncr5380_softc *); 113 static void si_dma_start(struct ncr5380_softc *); 114 static void si_dma_poll(struct ncr5380_softc *); 115 static void si_dma_eop(struct ncr5380_softc *); 116 static void si_dma_stop(struct ncr5380_softc *); 117 118 struct cfattach si_vsbus_ca = { 119 sizeof(struct si_softc), si_vsbus_match, si_vsbus_attach 120 }; 121 122 static int 123 si_vsbus_match(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 struct vsbus_attach_args *va = aux; 126 volatile char *si_csr = (char *) va->va_addr; 127 128 if (vax_boardtype == VAX_BTYP_49 || vax_boardtype == VAX_BTYP_46 129 || vax_boardtype == VAX_BTYP_48) 130 return 0; 131 /* This is the way Linux autoprobes the interrupt MK-990321 */ 132 si_csr[12] = 0; 133 si_csr[16] = 0x80; 134 si_csr[0] = 0x80; 135 si_csr[4] = 5; /* 0xcf */ 136 DELAY(100000); 137 return 1; 138 } 139 140 static void 141 si_vsbus_attach(struct device *parent, struct device *self, void *aux) 142 { 143 struct vsbus_attach_args *va = aux; 144 struct si_softc *sc = (struct si_softc *) self; 145 struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 146 int tweak, target; 147 148 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, 149 SCB_ISTACK, &sc->ncr_intrcnt); 150 evcnt_attach_dynamic(&sc->ncr_intrcnt, EVCNT_TYPE_INTR, NULL, 151 self->dv_xname, "intr"); 152 153 /* 154 * DMA area mapin. 155 * On VS3100, split the 128K block between the two devices. 156 * On VS2000, don't care for now. 157 */ 158 #define DMASIZE (64*1024) 159 if (vax_boardtype != VAX_BTYP_410) { 160 if (va->va_paddr & 0x100) /* Magic */ 161 sc->ncr_off = DMASIZE; 162 sc->ncr_addr = (caddr_t)uvm_km_valloc(kernel_map, DMASIZE); 163 164 ioaccess((vaddr_t)sc->ncr_addr, 165 0x202d0000 + sc->ncr_off, DMASIZE/VAX_NBPG); 166 167 /* 168 * MD function pointers used by the MI code. 169 */ 170 ncr_sc->sc_dma_alloc = si_dma_alloc; 171 ncr_sc->sc_dma_free = si_dma_free; 172 ncr_sc->sc_dma_setup = si_dma_setup; 173 ncr_sc->sc_dma_start = si_dma_start; 174 ncr_sc->sc_dma_poll = si_dma_poll; 175 ncr_sc->sc_dma_eop = si_dma_eop; 176 ncr_sc->sc_dma_stop = si_dma_stop; 177 178 /* DMA control register offsets */ 179 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 180 sc->ncr_dmacount = 64; /* DMA count register */ 181 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 182 } 183 ncr_sc->sc_pio_out = ncr5380_pio_out; 184 ncr_sc->sc_pio_in = ncr5380_pio_in; 185 186 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 187 188 /* 189 * Initialize fields used by the MI code. 190 */ 191 /* ncr_sc->sc_regt = Unused on VAX */ 192 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 193 194 /* Register offsets */ 195 ncr_sc->sci_r0 = 0; 196 ncr_sc->sci_r1 = 4; 197 ncr_sc->sci_r2 = 8; 198 ncr_sc->sci_r3 = 12; 199 ncr_sc->sci_r4 = 16; 200 ncr_sc->sci_r5 = 20; 201 ncr_sc->sci_r6 = 24; 202 ncr_sc->sci_r7 = 28; 203 204 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 205 206 ncr_sc->sc_no_disconnect = 0xff; 207 208 /* 209 * Get the SCSI chip target address out of NVRAM. 210 * This do not apply to the VS2000. 211 */ 212 tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0); 213 if (vax_boardtype == VAX_BTYP_410) 214 target = 7; 215 else 216 target = (clk_page[0xbc/2] >> tweak) & 7; 217 218 printf("\n%s: NCR5380, SCSI ID %d\n", ncr_sc->sc_dev.dv_xname, target); 219 220 ncr_sc->sc_adapter.scsipi_minphys = si_minphys; 221 ncr_sc->sc_link.scsipi_scsi.adapter_target = target; 222 /* 223 * Initialize si board itself. 224 */ 225 ncr5380_attach(ncr_sc); 226 } 227 228 /* 229 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 230 */ 231 static void 232 si_minphys(struct buf *bp) 233 { 234 if ((vax_boardtype == VAX_BTYP_410) && (bp->b_bcount > (16*1024))) 235 bp->b_bcount = (16*1024); 236 else if (bp->b_bcount > MAXPHYS) 237 bp->b_bcount = MAXPHYS; 238 } 239 240 void 241 si_dma_alloc(struct ncr5380_softc *ncr_sc) 242 { 243 struct si_softc *sc = (struct si_softc *)ncr_sc; 244 struct sci_req *sr = ncr_sc->sc_current; 245 struct scsipi_xfer *xs = sr->sr_xs; 246 struct si_dma_handle *dh; 247 int xlen, i; 248 249 #ifdef DIAGNOSTIC 250 if (sr->sr_dma_hand != NULL) 251 panic("si_dma_alloc: already have DMA handle"); 252 #endif 253 254 /* Polled transfers shouldn't allocate a DMA handle. */ 255 if (sr->sr_flags & SR_IMMED) 256 return; 257 258 xlen = ncr_sc->sc_datalen; 259 260 /* Make sure our caller checked sc_min_dma_len. */ 261 if (xlen < MIN_DMA_LEN) 262 panic("si_dma_alloc: len=0x%x\n", xlen); 263 264 /* 265 * Find free PDMA handle. Guaranteed to find one since we 266 * have as many PDMA handles as the driver has processes. 267 * (instances?) 268 */ 269 for (i = 0; i < SCI_OPENINGS; i++) { 270 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 271 goto found; 272 } 273 panic("sbc: no free PDMA handles"); 274 found: 275 dh = &sc->ncr_dma[i]; 276 dh->dh_flags = SIDH_BUSY; 277 dh->dh_addr = ncr_sc->sc_dataptr; 278 dh->dh_len = xlen; 279 dh->dh_proc = xs->bp->b_proc; 280 281 /* Remember dest buffer parameters */ 282 if (xs->xs_control & XS_CTL_DATA_OUT) 283 dh->dh_flags |= SIDH_OUT; 284 285 sr->sr_dma_hand = dh; 286 } 287 288 void 289 si_dma_free(struct ncr5380_softc *ncr_sc) 290 { 291 struct sci_req *sr = ncr_sc->sc_current; 292 struct si_dma_handle *dh = sr->sr_dma_hand; 293 294 if (dh->dh_flags & SIDH_BUSY) 295 dh->dh_flags = 0; 296 else 297 printf("si_dma_free: free'ing unused buffer\n"); 298 299 sr->sr_dma_hand = NULL; 300 } 301 302 void 303 si_dma_setup(struct ncr5380_softc *ncr_sc) 304 { 305 /* Do nothing here */ 306 } 307 308 void 309 si_dma_start(struct ncr5380_softc *ncr_sc) 310 { 311 struct si_softc *sc = (struct si_softc *)ncr_sc; 312 struct sci_req *sr = ncr_sc->sc_current; 313 struct si_dma_handle *dh = sr->sr_dma_hand; 314 315 /* 316 * Set the VAX-DMA-specific registers, and copy the data if 317 * it is directed "outbound". 318 */ 319 if (dh->dh_flags & SIDH_OUT) { 320 if ((vaddr_t)dh->dh_addr & KERNBASE) 321 bcopy(dh->dh_addr, sc->ncr_addr, dh->dh_len); 322 else 323 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 324 sc->ncr_addr, dh->dh_len); 325 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 326 sc->ncr_dmadir, 0); 327 } else { 328 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 329 sc->ncr_dmadir, 1); 330 } 331 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 332 sc->ncr_dmacount, -dh->dh_len); 333 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 334 sc->ncr_dmaaddr, sc->ncr_off); 335 /* 336 * Now from the 5380-internal DMA registers. 337 */ 338 if (dh->dh_flags & SIDH_OUT) { 339 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 340 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 341 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 342 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 343 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 344 } else { 345 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 346 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 347 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 348 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 349 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 350 } 351 ncr_sc->sc_state |= NCR_DOINGDMA; 352 } 353 354 /* 355 * When? 356 */ 357 void 358 si_dma_poll(struct ncr5380_softc *ncr_sc) 359 { 360 printf("si_dma_poll\n"); 361 } 362 363 /* 364 * When? 365 */ 366 void 367 si_dma_eop(struct ncr5380_softc *ncr_sc) 368 { 369 printf("si_dma_eop\n"); 370 } 371 372 void 373 si_dma_stop(struct ncr5380_softc *ncr_sc) 374 { 375 struct si_softc *sc = (struct si_softc *)ncr_sc; 376 struct sci_req *sr = ncr_sc->sc_current; 377 struct si_dma_handle *dh = sr->sr_dma_hand; 378 int count, i; 379 380 if (ncr_sc->sc_state & NCR_DOINGDMA) 381 ncr_sc->sc_state &= ~NCR_DOINGDMA; 382 383 /* 384 * Sometimes the FIFO buffer isn't drained when the 385 * interrupt is posted. Just loop here and hope that 386 * it will drain soon. 387 */ 388 for (i = 0; i < 20000; i++) { 389 count = bus_space_read_4(ncr_sc->sc_regt, 390 ncr_sc->sc_regh, sc->ncr_dmacount); 391 if (count == 0) 392 break; 393 DELAY(100); 394 } 395 if (count == 0) { 396 if (((dh->dh_flags & SIDH_OUT) == 0)) { 397 if ((vaddr_t)dh->dh_addr & KERNBASE) 398 bcopy(sc->ncr_addr, dh->dh_addr, dh->dh_len); 399 else 400 vsbus_copytoproc(dh->dh_proc, sc->ncr_addr, 401 dh->dh_addr, dh->dh_len); 402 403 } 404 ncr_sc->sc_dataptr += dh->dh_len; 405 ncr_sc->sc_datalen -= dh->dh_len; 406 } 407 408 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 409 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 410 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 411 } 412
Indexes created Tue Sep 30 20:09:53 GMT 2025