ncr.c revision 1.45
1 /* $NetBSD: ncr.c,v 1.45 2008/04/04 16:00:58 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Adam Glass, David Jones, Gordon W. Ross, and Jens A. Nilsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * This file contains the machine-dependent parts of the NCR-5380 41 * controller. The machine-independent parts are in ncr5380sbc.c. 42 * 43 * Jens A. Nilsson. 44 * 45 * Credits: 46 * 47 * This code is based on arch/sun3/dev/si* 48 * Written by David Jones, Gordon Ross, and Adam Glass. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ncr.c,v 1.45 2008/04/04 16:00:58 tsutsui Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/buf.h> 61 #include <sys/proc.h> 62 #include <sys/user.h> 63 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsipi_debug.h> 67 #include <dev/scsipi/scsiconf.h> 68 69 #include <dev/ic/ncr5380reg.h> 70 #include <dev/ic/ncr5380var.h> 71 72 #include <machine/cpu.h> 73 #include <machine/vsbus.h> 74 #include <machine/bus.h> 75 #include <machine/sid.h> 76 #include <machine/scb.h> 77 #include <machine/clock.h> 78 79 #include "ioconf.h" 80 81 #define MIN_DMA_LEN 128 82 83 struct si_dma_handle { 84 int dh_flags; 85 #define SIDH_BUSY 1 86 #define SIDH_OUT 2 87 void *dh_addr; 88 int dh_len; 89 struct proc *dh_proc; 90 }; 91 92 struct si_softc { 93 struct ncr5380_softc ncr_sc; 94 struct evcnt ncr_intrcnt; 95 void *ncr_addr; 96 int ncr_off; 97 int ncr_dmaaddr; 98 int ncr_dmacount; 99 int ncr_dmadir; 100 struct si_dma_handle ncr_dma[SCI_OPENINGS]; 101 struct vsbus_dma sc_vd; 102 int onlyscsi; /* This machine needs no queueing */ 103 }; 104 105 static int ncr_dmasize; 106 107 static int si_vsbus_match(device_t, cfdata_t, void *); 108 static void si_vsbus_attach(device_t, device_t, void *); 109 static void si_minphys(struct buf *); 110 111 static void si_dma_alloc(struct ncr5380_softc *); 112 static void si_dma_free(struct ncr5380_softc *); 113 static void si_dma_setup(struct ncr5380_softc *); 114 static void si_dma_start(struct ncr5380_softc *); 115 static void si_dma_poll(struct ncr5380_softc *); 116 static void si_dma_eop(struct ncr5380_softc *); 117 static void si_dma_stop(struct ncr5380_softc *); 118 static void si_dma_go(void *); 119 120 CFATTACH_DECL_NEW(si_vsbus, sizeof(struct si_softc), 121 si_vsbus_match, si_vsbus_attach, NULL, NULL); 122 123 static int 124 si_vsbus_match(device_t parent, cfdata_t cf, void *aux) 125 { 126 struct vsbus_attach_args * const va = aux; 127 volatile char *si_csr = (char *) va->va_addr; 128 129 if (vax_boardtype == VAX_BTYP_49 || vax_boardtype == VAX_BTYP_46 130 || vax_boardtype == VAX_BTYP_48 || vax_boardtype == VAX_BTYP_53) 131 return 0; 132 /* This is the way Linux autoprobes the interrupt MK-990321 */ 133 si_csr[12] = 0; 134 si_csr[16] = 0x80; 135 si_csr[0] = 0x80; 136 si_csr[4] = 5; /* 0xcf */ 137 DELAY(100000); 138 return 1; 139 } 140 141 static void 142 si_vsbus_attach(device_t parent, device_t self, void *aux) 143 { 144 struct vsbus_attach_args * const va = aux; 145 struct si_softc * const sc = device_private(self); 146 struct ncr5380_softc * const ncr_sc = &sc->ncr_sc; 147 int tweak, target; 148 149 ncr_sc->sc_dev = self; 150 151 scb_vecalloc(va->va_cvec, (void (*)(void *)) ncr5380_intr, sc, 152 SCB_ISTACK, &sc->ncr_intrcnt); 153 evcnt_attach_dynamic(&sc->ncr_intrcnt, EVCNT_TYPE_INTR, NULL, 154 device_xname(self), "intr"); 155 156 /* 157 * DMA area mapin. 158 * On VS3100, split the 128K block between the two devices. 159 * On VS2000, don't care for now. 160 */ 161 #define DMASIZE (64*1024) 162 if (va->va_paddr & 0x100) { /* Secondary SCSI controller */ 163 sc->ncr_off = DMASIZE; 164 sc->onlyscsi = 1; 165 } 166 sc->ncr_addr = (void *)va->va_dmaaddr; 167 ncr_dmasize = min(va->va_dmasize, MAXPHYS); 168 169 /* 170 * MD function pointers used by the MI code. 171 */ 172 ncr_sc->sc_dma_alloc = si_dma_alloc; 173 ncr_sc->sc_dma_free = si_dma_free; 174 ncr_sc->sc_dma_setup = si_dma_setup; 175 ncr_sc->sc_dma_start = si_dma_start; 176 ncr_sc->sc_dma_poll = si_dma_poll; 177 ncr_sc->sc_dma_eop = si_dma_eop; 178 ncr_sc->sc_dma_stop = si_dma_stop; 179 180 /* DMA control register offsets */ 181 sc->ncr_dmaaddr = 32; /* DMA address in buffer, longword */ 182 sc->ncr_dmacount = 64; /* DMA count register */ 183 sc->ncr_dmadir = 68; /* Direction of DMA transfer */ 184 185 ncr_sc->sc_pio_out = ncr5380_pio_out; 186 ncr_sc->sc_pio_in = ncr5380_pio_in; 187 188 ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 189 190 /* 191 * Initialize fields used by the MI code. 192 */ 193 /* ncr_sc->sc_regt = Unused on VAX */ 194 ncr_sc->sc_regh = vax_map_physmem(va->va_paddr, 1); 195 196 /* Register offsets */ 197 ncr_sc->sci_r0 = 0; 198 ncr_sc->sci_r1 = 4; 199 ncr_sc->sci_r2 = 8; 200 ncr_sc->sci_r3 = 12; 201 ncr_sc->sci_r4 = 16; 202 ncr_sc->sci_r5 = 20; 203 ncr_sc->sci_r6 = 24; 204 ncr_sc->sci_r7 = 28; 205 206 ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 207 208 ncr_sc->sc_no_disconnect = 0xff; 209 210 /* 211 * Get the SCSI chip target address out of NVRAM. 212 * This do not apply to the VS2000. 213 */ 214 tweak = clk_tweak + (va->va_paddr & 0x100 ? 3 : 0); 215 if (vax_boardtype == VAX_BTYP_410) 216 target = 7; 217 else 218 target = (clk_page[0xbc/2] >> tweak) & 7; 219 220 aprint_normal("\n"); 221 aprint_normal_dev(self, "NCR5380, SCSI ID %d\n", target); 222 223 ncr_sc->sc_adapter.adapt_minphys = si_minphys; 224 ncr_sc->sc_channel.chan_id = target; 225 226 /* 227 * Init the vsbus DMA resource queue struct */ 228 sc->sc_vd.vd_go = si_dma_go; 229 sc->sc_vd.vd_arg = sc; 230 231 /* 232 * Initialize si board itself. 233 */ 234 ncr5380_attach(ncr_sc); 235 } 236 237 /* 238 * Adjust the max transfer size. The DMA buffer is only 16k on VS2000. 239 */ 240 static void 241 si_minphys(struct buf *bp) 242 { 243 if (bp->b_bcount > ncr_dmasize) 244 bp->b_bcount = ncr_dmasize; 245 } 246 247 void 248 si_dma_alloc(struct ncr5380_softc *ncr_sc) 249 { 250 struct si_softc *sc = (struct si_softc *)ncr_sc; 251 struct sci_req *sr = ncr_sc->sc_current; 252 struct scsipi_xfer *xs = sr->sr_xs; 253 struct si_dma_handle *dh; 254 int xlen, i; 255 256 #ifdef DIAGNOSTIC 257 if (sr->sr_dma_hand != NULL) 258 panic("si_dma_alloc: already have DMA handle"); 259 #endif 260 261 /* Polled transfers shouldn't allocate a DMA handle. */ 262 if (sr->sr_flags & SR_IMMED) 263 return; 264 265 xlen = ncr_sc->sc_datalen; 266 267 /* Make sure our caller checked sc_min_dma_len. */ 268 if (xlen < MIN_DMA_LEN) 269 panic("si_dma_alloc: len=0x%x", xlen); 270 271 /* 272 * Find free PDMA handle. Guaranteed to find one since we 273 * have as many PDMA handles as the driver has processes. 274 * (instances?) 275 */ 276 for (i = 0; i < SCI_OPENINGS; i++) { 277 if ((sc->ncr_dma[i].dh_flags & SIDH_BUSY) == 0) 278 goto found; 279 } 280 panic("sbc: no free PDMA handles"); 281 found: 282 dh = &sc->ncr_dma[i]; 283 dh->dh_flags = SIDH_BUSY; 284 dh->dh_addr = ncr_sc->sc_dataptr; 285 dh->dh_len = xlen; 286 dh->dh_proc = xs->bp->b_proc; 287 288 /* Remember dest buffer parameters */ 289 if (xs->xs_control & XS_CTL_DATA_OUT) 290 dh->dh_flags |= SIDH_OUT; 291 292 sr->sr_dma_hand = dh; 293 } 294 295 void 296 si_dma_free(struct ncr5380_softc *ncr_sc) 297 { 298 struct sci_req *sr = ncr_sc->sc_current; 299 struct si_dma_handle *dh = sr->sr_dma_hand; 300 301 if (dh->dh_flags & SIDH_BUSY) 302 dh->dh_flags = 0; 303 else 304 printf("si_dma_free: free'ing unused buffer\n"); 305 306 sr->sr_dma_hand = NULL; 307 } 308 309 void 310 si_dma_setup(struct ncr5380_softc *ncr_sc) 311 { 312 /* Do nothing here */ 313 } 314 315 void 316 si_dma_start(struct ncr5380_softc *ncr_sc) 317 { 318 struct si_softc *sc = (struct si_softc *)ncr_sc; 319 320 /* Just put on queue; will call go() from below */ 321 if (sc->onlyscsi) 322 si_dma_go(ncr_sc); 323 else 324 vsbus_dma_start(&sc->sc_vd); 325 } 326 327 /* 328 * go() routine called when another transfer somewhere is finished. 329 */ 330 void 331 si_dma_go(void *arg) 332 { 333 struct ncr5380_softc *ncr_sc = arg; 334 struct si_softc *sc = (struct si_softc *)ncr_sc; 335 struct sci_req *sr = ncr_sc->sc_current; 336 struct si_dma_handle *dh = sr->sr_dma_hand; 337 338 /* 339 * Set the VAX-DMA-specific registers, and copy the data if 340 * it is directed "outbound". 341 */ 342 if (dh->dh_flags & SIDH_OUT) { 343 vsbus_copyfromproc(dh->dh_proc, dh->dh_addr, 344 (char *)sc->ncr_addr + sc->ncr_off, dh->dh_len); 345 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 346 sc->ncr_dmadir, 0); 347 } else { 348 bus_space_write_1(ncr_sc->sc_regt, ncr_sc->sc_regh, 349 sc->ncr_dmadir, 1); 350 } 351 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 352 sc->ncr_dmacount, -dh->dh_len); 353 bus_space_write_4(ncr_sc->sc_regt, ncr_sc->sc_regh, 354 sc->ncr_dmaaddr, sc->ncr_off); 355 /* 356 * Now from the 5380-internal DMA registers. 357 */ 358 if (dh->dh_flags & SIDH_OUT) { 359 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 360 NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 361 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 362 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 363 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 364 } else { 365 NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 366 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 367 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) 368 | SCI_MODE_DMA | SCI_MODE_DMA_IE); 369 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 370 } 371 ncr_sc->sc_state |= NCR_DOINGDMA; 372 } 373 374 /* 375 * When? 376 */ 377 void 378 si_dma_poll(struct ncr5380_softc *ncr_sc) 379 { 380 printf("si_dma_poll\n"); 381 } 382 383 /* 384 * When? 385 */ 386 void 387 si_dma_eop(struct ncr5380_softc *ncr_sc) 388 { 389 printf("si_dma_eop\n"); 390 } 391 392 void 393 si_dma_stop(struct ncr5380_softc *ncr_sc) 394 { 395 struct si_softc *sc = (struct si_softc *)ncr_sc; 396 struct sci_req *sr = ncr_sc->sc_current; 397 struct si_dma_handle *dh = sr->sr_dma_hand; 398 int count, i; 399 400 if (ncr_sc->sc_state & NCR_DOINGDMA) 401 ncr_sc->sc_state &= ~NCR_DOINGDMA; 402 403 /* 404 * Sometimes the FIFO buffer isn't drained when the 405 * interrupt is posted. Just loop here and hope that 406 * it will drain soon. 407 */ 408 for (i = 0; i < 20000; i++) { 409 count = bus_space_read_4(ncr_sc->sc_regt, 410 ncr_sc->sc_regh, sc->ncr_dmacount); 411 if (count == 0) 412 break; 413 DELAY(100); 414 } 415 if (count == 0) { 416 if (((dh->dh_flags & SIDH_OUT) == 0)) { 417 vsbus_copytoproc(dh->dh_proc, 418 (char *)sc->ncr_addr + sc->ncr_off, 419 dh->dh_addr, dh->dh_len); 420 } 421 ncr_sc->sc_dataptr += dh->dh_len; 422 ncr_sc->sc_datalen -= dh->dh_len; 423 } 424 425 NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) & 426 ~(SCI_MODE_DMA | SCI_MODE_DMA_IE)); 427 NCR5380_WRITE(ncr_sc, sci_icmd, 0); 428 if (sc->onlyscsi == 0) 429 vsbus_dma_intr(); /* Try to start more transfers */ 430 } 431
Indexes created Tue Sep 30 20:09:53 GMT 2025