1 1.12 isaki /* $NetBSD: dmacvar.h,v 1.12 2017/08/11 07:30:01 isaki Exp $ */ 2 1.2 minoura 3 1.2 minoura /*- 4 1.2 minoura * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 1.2 minoura * All rights reserved. 6 1.2 minoura * 7 1.2 minoura * This code is derived from software contributed to The NetBSD Foundation 8 1.2 minoura * by Minoura Makoto. 9 1.2 minoura * 10 1.2 minoura * Redistribution and use in source and binary forms, with or without 11 1.2 minoura * modification, are permitted provided that the following conditions 12 1.2 minoura * are met: 13 1.2 minoura * 1. Redistributions of source code must retain the above copyright 14 1.2 minoura * notice, this list of conditions and the following disclaimer. 15 1.2 minoura * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 minoura * notice, this list of conditions and the following disclaimer in the 17 1.2 minoura * documentation and/or other materials provided with the distribution. 18 1.2 minoura * 19 1.2 minoura * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 minoura * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 minoura * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 minoura * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 minoura * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 minoura * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 minoura * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 minoura * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 minoura * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 minoura * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 minoura * POSSIBILITY OF SUCH DAMAGE. 30 1.2 minoura */ 31 1.2 minoura 32 1.2 minoura /* 33 1.2 minoura * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 34 1.2 minoura */ 35 1.2 minoura 36 1.2 minoura #include <dev/ic/mc68450reg.h> 37 1.3 minoura #include <machine/bus.h> 38 1.2 minoura 39 1.3 minoura #define DMAC_MAPSIZE 64 40 1.2 minoura 41 1.5 chs typedef int (*dmac_intr_handler_t)(void *); 42 1.2 minoura 43 1.2 minoura /* 44 1.3 minoura * Structure that describes a single transfer. 45 1.3 minoura */ 46 1.3 minoura struct dmac_channel_stat; 47 1.3 minoura struct dmac_dma_xfer { 48 1.3 minoura struct dmac_channel_stat *dx_channel; 49 1.3 minoura bus_dmamap_t dx_dmamap; /* dmamap tag */ 50 1.3 minoura bus_dma_tag_t dx_tag; /* dma tag for the transfer */ 51 1.3 minoura int dx_ocr; /* direction */ 52 1.3 minoura int dx_scr; /* SCR value */ 53 1.3 minoura void *dx_device; /* (initial) device address */ 54 1.4 minoura #ifdef DMAC_ARRAYCHAIN 55 1.3 minoura struct dmac_sg_array *dx_array; /* DMAC array chain */ 56 1.3 minoura int dx_done; 57 1.4 minoura #endif 58 1.3 minoura }; 59 1.3 minoura 60 1.3 minoura /* 61 1.2 minoura * Struct that holds the channel status. 62 1.2 minoura * Embedded in the device softc for each channel. 63 1.2 minoura */ 64 1.2 minoura struct dmac_channel_stat { 65 1.2 minoura int ch_channel; /* channel number */ 66 1.2 minoura char ch_name[8]; /* user device name */ 67 1.2 minoura bus_space_handle_t ch_bht; /* bus_space handle */ 68 1.2 minoura int ch_dcr; /* device description */ 69 1.2 minoura int ch_ocr; /* operation size, request mode */ 70 1.2 minoura int ch_normalv; /* normal interrupt vector */ 71 1.2 minoura int ch_errorv; /* error interrupt vector */ 72 1.2 minoura dmac_intr_handler_t ch_normal; /* normal interrupt handler */ 73 1.2 minoura dmac_intr_handler_t ch_error; /* error interrupt handler */ 74 1.2 minoura void *ch_normalarg; 75 1.2 minoura void *ch_errorarg; 76 1.3 minoura struct dmac_dma_xfer ch_xfer; 77 1.3 minoura struct dmac_sg_array *ch_map; /* transfer map for arraychain mode */ 78 1.3 minoura bus_dma_segment_t ch_seg[1]; 79 1.10 isaki struct dmac_softc *ch_softc; /* device softc link */ 80 1.2 minoura }; 81 1.2 minoura 82 1.2 minoura /* 83 1.2 minoura * DMAC softc 84 1.2 minoura */ 85 1.2 minoura struct dmac_softc { 86 1.9 isaki device_t sc_dev; 87 1.2 minoura 88 1.2 minoura bus_space_tag_t sc_bst; 89 1.2 minoura bus_space_handle_t sc_bht; 90 1.2 minoura 91 1.2 minoura struct dmac_channel_stat sc_channels[DMAC_NCHAN]; 92 1.2 minoura }; 93 1.2 minoura 94 1.2 minoura 95 1.2 minoura #define DMAC_ADDR 0xe84000 96 1.2 minoura 97 1.2 minoura #define DMAC_MAXSEGSZ 0xff00 98 1.2 minoura #define DMAC_BOUNDARY 0 99 1.2 minoura 100 1.11 isaki struct dmac_channel_stat *dmac_alloc_channel(device_t, 101 1.11 isaki int, /* ch */ 102 1.11 isaki const char *, /* name */ 103 1.11 isaki int, dmac_intr_handler_t, void *, /* normal handler */ 104 1.11 isaki int, dmac_intr_handler_t, void *, /* error handler */ 105 1.11 isaki uint8_t, /* dcr */ 106 1.11 isaki uint8_t /* ocr */ 107 1.11 isaki ); 108 1.9 isaki int dmac_free_channel(device_t, int, void *); 109 1.2 minoura /* ch, channel */ 110 1.5 chs struct dmac_dma_xfer *dmac_alloc_xfer(struct dmac_channel_stat *, 111 1.5 chs bus_dma_tag_t, bus_dmamap_t); 112 1.10 isaki int dmac_load_xfer(struct dmac_softc *, struct dmac_dma_xfer *); 113 1.5 chs 114 1.10 isaki int dmac_start_xfer(struct dmac_softc *, struct dmac_dma_xfer *); 115 1.10 isaki int dmac_start_xfer_offset(struct dmac_softc *, struct dmac_dma_xfer *, 116 1.10 isaki u_int, u_int); 117 1.10 isaki int dmac_abort_xfer(struct dmac_softc *, struct dmac_dma_xfer *); 118 1.4 minoura /* Compatibility function: alloc, fill defaults, load */ 119 1.5 chs struct dmac_dma_xfer *dmac_prepare_xfer(struct dmac_channel_stat *, 120 1.5 chs bus_dma_tag_t, bus_dmamap_t, int, int, void *); 121 1.2 minoura /* chan, dmat, map, dir, sequence, dar */ 122
Indexes created Wed Sep 24 05:09:52 GMT 2025