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dmacvar.h revision 1.3
      1  1.3  minoura /*	$NetBSD: dmacvar.h,v 1.3 2001/04/30 05:47:31 minoura Exp $	*/
      2  1.2  minoura 
      3  1.2  minoura /*-
      4  1.2  minoura  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
      5  1.2  minoura  * All rights reserved.
      6  1.2  minoura  *
      7  1.2  minoura  * This code is derived from software contributed to The NetBSD Foundation
      8  1.2  minoura  * by Minoura Makoto.
      9  1.2  minoura  *
     10  1.2  minoura  * Redistribution and use in source and binary forms, with or without
     11  1.2  minoura  * modification, are permitted provided that the following conditions
     12  1.2  minoura  * are met:
     13  1.2  minoura  * 1. Redistributions of source code must retain the above copyright
     14  1.2  minoura  *    notice, this list of conditions and the following disclaimer.
     15  1.2  minoura  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.2  minoura  *    notice, this list of conditions and the following disclaimer in the
     17  1.2  minoura  *    documentation and/or other materials provided with the distribution.
     18  1.2  minoura  * 3. All advertising materials mentioning features or use of this software
     19  1.2  minoura  *    must display the following acknowledgement:
     20  1.2  minoura  *	This product includes software developed by the NetBSD
     21  1.2  minoura  *	Foundation, Inc. and its contributors.
     22  1.2  minoura  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.2  minoura  *    contributors may be used to endorse or promote products derived
     24  1.2  minoura  *    from this software without specific prior written permission.
     25  1.2  minoura  *
     26  1.2  minoura  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.2  minoura  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.2  minoura  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.2  minoura  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.2  minoura  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.2  minoura  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.2  minoura  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.2  minoura  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.2  minoura  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.2  minoura  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.2  minoura  * POSSIBILITY OF SUCH DAMAGE.
     37  1.2  minoura  */
     38  1.2  minoura 
     39  1.2  minoura /*
     40  1.2  minoura  * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k.
     41  1.2  minoura  */
     42  1.2  minoura 
     43  1.2  minoura #include <dev/ic/mc68450reg.h>
     44  1.3  minoura #include <machine/bus.h>
     45  1.2  minoura 
     46  1.3  minoura #define DMAC_MAPSIZE 64
     47  1.2  minoura 
     48  1.2  minoura typedef int (*dmac_intr_handler_t) __P((void*));
     49  1.2  minoura 
     50  1.2  minoura /*
     51  1.3  minoura  * Structure that describes a single transfer.
     52  1.3  minoura  */
     53  1.3  minoura struct dmac_channel_stat;
     54  1.3  minoura struct dmac_dma_xfer {
     55  1.3  minoura 	struct dmac_channel_stat *dx_channel;
     56  1.3  minoura 	bus_dmamap_t	dx_dmamap;	/* dmamap tag */
     57  1.3  minoura 	bus_dma_tag_t	dx_tag;		/* dma tag for the transfer */
     58  1.3  minoura 	int		dx_ocr;		/* direction */
     59  1.3  minoura 	int		dx_scr;		/* SCR value */
     60  1.3  minoura 	void		*dx_device;	/* (initial) device address */
     61  1.3  minoura 	bus_dma_segment_t dx_seg;	/* b_d_s_t for the array chain */
     62  1.3  minoura 	struct dmac_sg_array *dx_array;	/* DMAC array chain */
     63  1.3  minoura 	int		dx_arraysize;	/* size of above */
     64  1.3  minoura 	int		dx_done;
     65  1.3  minoura };
     66  1.3  minoura 
     67  1.3  minoura /*
     68  1.2  minoura  * Struct that holds the channel status.
     69  1.2  minoura  * Embedded in the device softc for each channel.
     70  1.2  minoura  */
     71  1.2  minoura struct dmac_channel_stat {
     72  1.2  minoura 	int			ch_channel; /* channel number */
     73  1.2  minoura 	char			ch_name[8]; /* user device name */
     74  1.2  minoura 	bus_space_handle_t	ch_bht;	/* bus_space handle */
     75  1.2  minoura 	int			ch_dcr;	/* device description */
     76  1.2  minoura 	int			ch_ocr;	/* operation size, request mode */
     77  1.2  minoura 	int			ch_normalv; /* normal interrupt vector */
     78  1.2  minoura 	int			ch_errorv; /* error interrupt vector */
     79  1.2  minoura 	dmac_intr_handler_t	ch_normal; /* normal interrupt handler */
     80  1.2  minoura 	dmac_intr_handler_t	ch_error; /* error interrupt handler */
     81  1.2  minoura 	void			*ch_normalarg;
     82  1.2  minoura 	void			*ch_errorarg;
     83  1.3  minoura 	struct dmac_dma_xfer	ch_xfer;
     84  1.3  minoura 	struct dmac_sg_array	*ch_map; /* transfer map for arraychain mode */
     85  1.3  minoura 	bus_dma_segment_t	ch_seg[1];
     86  1.2  minoura 	struct device		*ch_softc; /* device softc link */
     87  1.2  minoura };
     88  1.2  minoura 
     89  1.2  minoura /*
     90  1.2  minoura  * DMAC softc
     91  1.2  minoura  */
     92  1.2  minoura struct dmac_softc {
     93  1.2  minoura 	struct device		sc_dev;
     94  1.2  minoura 
     95  1.2  minoura 	bus_space_tag_t		sc_bst;
     96  1.2  minoura 	bus_space_handle_t	sc_bht;
     97  1.2  minoura 
     98  1.2  minoura 	struct dmac_channel_stat sc_channels[DMAC_NCHAN];
     99  1.2  minoura };
    100  1.2  minoura 
    101  1.2  minoura 
    102  1.2  minoura #define DMAC_ADDR	0xe84000
    103  1.2  minoura 
    104  1.2  minoura #define DMAC_MAXSEGSZ	0xff00
    105  1.2  minoura #define DMAC_BOUNDARY	0
    106  1.2  minoura 
    107  1.2  minoura struct dmac_channel_stat *dmac_alloc_channel __P((struct device*, int, char*,
    108  1.2  minoura 						  int,
    109  1.2  minoura 						  dmac_intr_handler_t, void*,
    110  1.2  minoura 						  int,
    111  1.2  minoura 						  dmac_intr_handler_t, void*));
    112  1.2  minoura 		/* ch, name, normalv, normal, errorv, error */
    113  1.2  minoura int dmac_free_channel __P((struct device*, int, void*));
    114  1.2  minoura 		/* ch, channel */
    115  1.2  minoura struct dmac_dma_xfer *dmac_prepare_xfer __P((struct dmac_channel_stat*,
    116  1.2  minoura 					     bus_dma_tag_t,
    117  1.2  minoura 					     bus_dmamap_t,
    118  1.2  minoura 					     int, int, void*));
    119  1.2  minoura 	/* chan, dmat, map, dir, sequence, dar */
    120  1.2  minoura #define dmac_finish_xfer(xfer) free(xfer, M_DEVBUF)
    121  1.2  minoura int dmac_start_xfer __P((struct device*, struct dmac_dma_xfer*));
    122