intio_dmac.c revision 1.1.2.2
1 /* $NetBSD: intio_dmac.c,v 1.1.2.2 1999/02/02 23:45:40 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/extent.h> 48 #include <vm/vm.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #define DMAC_DEBUG 58 59 #ifdef DMAC_DEBUG 60 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 61 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 62 int dmacdebug = 0; 63 #else 64 #define DPRINTF(n,x) 65 #define DDUMPREGS(n,x) 66 #endif 67 68 static void dmac_init_channels __P((struct dmac_softc*)); 69 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*)); 70 static int dmac_done __P((void*)); 71 static int dmac_error __P((void*)); 72 73 static int dmac_dump_regs __P((void)); 74 75 /* 76 * autoconf stuff 77 */ 78 static int dmac_match __P((struct device *, struct cfdata *, void *)); 79 static void dmac_attach __P((struct device *, struct device *, void *)); 80 81 struct cfattach dmac_ca = { 82 sizeof(struct dmac_softc), dmac_match, dmac_attach 83 }; 84 85 static int 86 dmac_match(parent, cf, aux) 87 struct device *parent; 88 struct cfdata *cf; 89 void *aux; 90 { 91 struct intio_attach_args *ia = aux; 92 93 if (strcmp (ia->ia_name, "dmac") != 0) 94 return (0); 95 if (cf->cf_unit != 0) 96 return (0); 97 98 /* fixed address */ 99 if (ia->ia_addr != DMAC_ADDR) 100 return (0); 101 if (ia->ia_intr != -1) 102 return (0); 103 104 return 1; 105 } 106 107 static void 108 dmac_attach(parent, self, aux) 109 struct device *parent, *self; 110 void *aux; 111 { 112 struct dmac_softc *sc = (struct dmac_softc *)self; 113 struct intio_attach_args *ia = aux; 114 int r; 115 116 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 117 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 118 #ifdef DIAGNOSTIC 119 if (r) 120 panic ("IO map for DMAC corruption??"); 121 #endif 122 123 ((struct intio_softc*) parent)->sc_dmac = self; 124 sc->sc_bst = ia->ia_bst; 125 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 126 dmac_init_channels(sc); 127 128 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 129 } 130 131 #define DMAC_MAPSIZE 64 132 /* Allocate statically in order to make sure the DMAC can reach the maps. */ 133 static struct dmac_sg_array dmac_map[DMAC_NCHAN][DMAC_MAPSIZE]; 134 135 static void 136 dmac_init_channels(sc) 137 struct dmac_softc *sc; 138 { 139 int i; 140 pmap_t pmap = pmap_kernel(); 141 142 for (i=0; i<DMAC_NCHAN; i++) { 143 sc->sc_channels[i].ch_channel = i; 144 sc->sc_channels[i].ch_name[0] = 0; 145 sc->sc_channels[i].ch_softc = &sc->sc_dev; 146 sc->sc_channels[i].ch_map = 147 (void*) pmap_extract (pmap, (vaddr_t) &dmac_map[i]); 148 bus_space_subregion(sc->sc_bst, sc->sc_bht, 149 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 150 &sc->sc_channels[i].ch_bht); 151 } 152 153 return; 154 } 155 156 157 /* 158 * Channel initialization/deinitialization per user device. 159 */ 160 struct dmac_channel_stat * 161 dmac_alloc_channel(self, ch, name, 162 normalv, normal, normalarg, 163 errorv, error, errorarg) 164 struct device *self; 165 int ch; 166 char *name; 167 int normalv, errorv; 168 dmac_intr_handler_t normal, error; 169 void *normalarg, *errorarg; 170 { 171 struct intio_softc *intio = (void*) self; 172 struct dmac_softc *sc = (void*) intio->sc_dmac; 173 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 174 char intrname[16]; 175 176 #ifdef DIAGNOSTIC 177 if (ch < 0 || ch >= DMAC_NCHAN) 178 panic ("Invalid DMAC channel."); 179 if (chan->ch_name[0]) 180 panic ("DMAC: channel in use."); 181 if (strlen(name) > 8) 182 panic ("DMAC: wrong user name."); 183 #endif 184 185 /* fill the channel status structure. */ 186 strcpy(chan->ch_name, name); 187 chan->ch_dcr = (DMAC_DCR_XRM_CSWOH | DMAC_DCR_OTYP_EASYNC | 188 DMAC_DCR_OPS_8BIT); 189 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_CHAIN_ARRAY | 190 DMAC_OCR_REQG_EXTERNAL); 191 chan->ch_normalv = normalv; 192 chan->ch_errorv = errorv; 193 chan->ch_normal = normal; 194 chan->ch_error = error; 195 chan->ch_normalarg = normalarg; 196 chan->ch_errorarg = errorarg; 197 chan->ch_xfer_in_progress = 0; 198 199 /* setup the device-specific registers */ 200 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 201 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 202 DMAC_REG_DCR, chan->ch_dcr); 203 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 204 205 /* 206 * X68k physical user space is a subset of the kernel space; 207 * the memory is always included in the physical user space, 208 * while the device is not. 209 */ 210 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 211 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 212 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 213 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 214 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 215 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 216 217 /* setup the interrupt handlers */ 218 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 219 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 220 221 strcpy(intrname, name); 222 strcat(intrname, "dma"); 223 intio_intr_establish (normalv, intrname, dmac_done, chan); 224 225 strcpy(intrname, name); 226 strcat(intrname, "dmaerr"); 227 intio_intr_establish (errorv, intrname, dmac_error, chan); 228 229 return chan; 230 } 231 232 int 233 dmac_free_channel(self, ch, channel) 234 struct device *self; 235 int ch; 236 void *channel; 237 { 238 struct dmac_softc *sc = (void*) self; 239 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 240 241 if (chan != channel) 242 return -1; 243 if (ch != chan->ch_channel) 244 return -1; 245 #if DIAGNOSTIC 246 if (chan->ch_xfer_in_progress) 247 panic ("dmac_free_channel: DMA transfer in progress"); 248 #endif 249 250 chan->ch_name[0] = 0; 251 intio_intr_disestablish(chan->ch_normalv, channel); 252 intio_intr_disestablish(chan->ch_errorv, channel); 253 254 return 0; 255 } 256 257 /* 258 * Initialization / deinitialization per transfer. 259 */ 260 struct dmac_dma_xfer * 261 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 262 struct dmac_channel_stat *chan; 263 bus_dma_tag_t dmat; 264 bus_dmamap_t dmamap; 265 int dir, scr; 266 void *dar; 267 { 268 struct dmac_dma_xfer *r = malloc (sizeof (struct dmac_dma_xfer), 269 M_DEVBUF, M_WAITOK); 270 271 r->dx_channel = chan; 272 r->dx_dmamap = dmamap; 273 r->dx_tag = dmat; 274 r->dx_ocr = dir & DMAC_OCR_DIR_MASK; 275 r->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 276 r->dx_device = dar; 277 r->dx_done = 0; 278 279 return r; 280 } 281 282 #ifdef DMAC_DEBUG 283 static struct dmac_channel_stat *debugchan = 0; 284 #endif 285 286 /* 287 * Do the actual transfer. 288 */ 289 int 290 dmac_start_xfer(self, xf) 291 struct device *self; 292 struct dmac_dma_xfer *xf; 293 { 294 struct dmac_softc *sc = (void*) self; 295 struct dmac_channel_stat *chan = xf->dx_channel; 296 int c; 297 298 299 #ifdef DMAC_DEBUG 300 debugchan=chan; 301 #endif 302 bus_space_write_1(sc->sc_bst, chan->ch_bht, 303 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 304 bus_space_write_1(sc->sc_bst, chan->ch_bht, 305 DMAC_REG_SCR, xf->dx_scr); 306 307 /* program DMAC in array chainning mode */ 308 xf->dx_done = 0; 309 DPRINTF (3, ("First program:\n")); 310 c = dmac_program_arraychain(self, xf); 311 312 /* setup the address/count registers */ 313 bus_space_write_4(sc->sc_bst, chan->ch_bht, 314 DMAC_REG_BAR, (int) chan->ch_map); 315 bus_space_write_4(sc->sc_bst, chan->ch_bht, 316 DMAC_REG_DAR, (int) xf->dx_device); 317 bus_space_write_1(sc->sc_bst, chan->ch_bht, 318 DMAC_REG_CSR, 0xff); 319 bus_space_write_2(sc->sc_bst, chan->ch_bht, 320 DMAC_REG_BTCR, c); 321 322 /* START!! */ 323 #if defined(M68040) || defined(M68060) 324 if (mmutype == MMU_68040) 325 DCIA(); /* XXX: granularity */ 326 #endif 327 DDUMPREGS (3, ("first start\n")); 328 bus_space_write_1(sc->sc_bst, chan->ch_bht, 329 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 330 chan->ch_xfer_in_progress = xf; 331 332 return 0; 333 } 334 335 static int 336 dmac_program_arraychain(self, xf) 337 struct device *self; 338 struct dmac_dma_xfer *xf; 339 { 340 struct dmac_softc *sc = (void*) self; 341 struct dmac_channel_stat *chan = xf->dx_channel; 342 int ch = chan->ch_channel; 343 struct x68k_bus_dmamap *map = xf->dx_dmamap; 344 int i, j; 345 346 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 347 i++, j++) { 348 dmac_map[ch][i].da_addr = (void*) map->dm_segs[j].ds_addr; 349 #ifdef DIAGNOSTIC 350 if (map->dm_segs[j].ds_len > 0xff00) 351 panic ("dmac_program_arraychain: wrong map: %d", map->dm_segs[j].ds_len); 352 #endif 353 dmac_map[ch][i].da_count = map->dm_segs[j].ds_len; 354 } 355 xf->dx_done = j; 356 357 return i; 358 } 359 360 /* 361 * interrupt handlers. 362 */ 363 static int 364 dmac_done(arg) 365 void *arg; 366 { 367 struct dmac_channel_stat *chan = arg; 368 struct dmac_softc *sc = (void*) chan->ch_softc; 369 struct dmac_dma_xfer *xf = chan->ch_xfer_in_progress; 370 struct x68k_bus_dmamap *map = xf->dx_dmamap; 371 int c; 372 373 DPRINTF (3, ("dmac_done\n")); 374 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 375 #if defined(M68040) || defined(M68060) 376 if (mmutype == MMU_68040) 377 DCIA(); /* XXX: granularity */ 378 #endif 379 380 if (xf->dx_done == map->dm_nsegs) { 381 /* Done */ 382 chan->ch_xfer_in_progress = 0; 383 return (*chan->ch_normal) (chan->ch_normalarg); 384 } 385 386 /* Continue transfer */ 387 DPRINTF (3, ("reprograming\n")); 388 c = dmac_program_arraychain (&sc->sc_dev, xf); 389 390 bus_space_write_4(sc->sc_bst, chan->ch_bht, 391 DMAC_REG_BAR, (int) chan->ch_map); 392 bus_space_write_4(sc->sc_bst, chan->ch_bht, 393 DMAC_REG_DAR, (int) xf->dx_device); 394 bus_space_write_1(sc->sc_bst, chan->ch_bht, 395 DMAC_REG_CSR, 0xff); 396 bus_space_write_2(sc->sc_bst, chan->ch_bht, 397 DMAC_REG_BTCR, c); 398 399 /* START!! */ 400 DDUMPREGS (3, ("restart\n")); 401 bus_space_write_1(sc->sc_bst, chan->ch_bht, 402 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 403 404 return 1; 405 } 406 407 static int 408 dmac_error(arg) 409 void *arg; 410 { 411 struct dmac_channel_stat *chan = arg; 412 struct dmac_softc *sc = (void*) chan->ch_softc; 413 414 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 415 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 416 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 417 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 418 DDUMPREGS(3, ("dmac_error\n")); 419 420 return (*chan->ch_error) (chan->ch_errorarg); 421 } 422 423 424 #ifdef DMAC_DEBUG 425 static int 426 dmac_dump_regs(void) 427 { 428 struct dmac_channel_stat *chan = debugchan; 429 struct dmac_softc *sc; 430 431 if ((chan == 0) || (dmacdebug & 0xf0)) return; 432 sc = (void*) chan->ch_softc; 433 434 printf ("DMAC channel %d registers\n", chan->ch_channel); 435 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 436 "CCR=%02x, CPR=%02x, GCR=%02x\n", 437 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 438 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 439 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 440 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 441 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 442 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 443 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 444 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 445 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 446 "MFCR=%02x, BFCR=%02x\n", 447 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 448 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 449 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 450 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 451 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 452 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 453 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 454 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 455 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 456 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 457 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 458 459 return 0; 460 } 461 #endif 462
Indexes created Thu Oct 02 14:10:14 GMT 2025