intio_dmac.c revision 1.1.2.3
1 /* $NetBSD: intio_dmac.c,v 1.1.2.3 1999/02/10 16:02:26 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/extent.h> 48 #include <vm/vm.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*)); 68 static int dmac_done __P((void*)); 69 static int dmac_error __P((void*)); 70 71 static int dmac_dump_regs __P((void)); 72 73 /* 74 * autoconf stuff 75 */ 76 static int dmac_match __P((struct device *, struct cfdata *, void *)); 77 static void dmac_attach __P((struct device *, struct device *, void *)); 78 79 struct cfattach dmac_ca = { 80 sizeof(struct dmac_softc), dmac_match, dmac_attach 81 }; 82 83 static int 84 dmac_match(parent, cf, aux) 85 struct device *parent; 86 struct cfdata *cf; 87 void *aux; 88 { 89 struct intio_attach_args *ia = aux; 90 91 if (strcmp (ia->ia_name, "dmac") != 0) 92 return (0); 93 if (cf->cf_unit != 0) 94 return (0); 95 96 /* fixed address */ 97 if (ia->ia_addr != DMAC_ADDR) 98 return (0); 99 if (ia->ia_intr != -1) 100 return (0); 101 102 return 1; 103 } 104 105 static void 106 dmac_attach(parent, self, aux) 107 struct device *parent, *self; 108 void *aux; 109 { 110 struct dmac_softc *sc = (struct dmac_softc *)self; 111 struct intio_attach_args *ia = aux; 112 int r; 113 114 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 115 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 116 #ifdef DIAGNOSTIC 117 if (r) 118 panic ("IO map for DMAC corruption??"); 119 #endif 120 121 ((struct intio_softc*) parent)->sc_dmac = self; 122 sc->sc_bst = ia->ia_bst; 123 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 124 dmac_init_channels(sc); 125 126 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 127 } 128 129 #define DMAC_MAPSIZE 64 130 /* Allocate statically in order to make sure the DMAC can reach the maps. */ 131 static struct dmac_sg_array dmac_map[DMAC_NCHAN][DMAC_MAPSIZE]; 132 133 static void 134 dmac_init_channels(sc) 135 struct dmac_softc *sc; 136 { 137 int i; 138 pmap_t pmap = pmap_kernel(); 139 140 for (i=0; i<DMAC_NCHAN; i++) { 141 sc->sc_channels[i].ch_channel = i; 142 sc->sc_channels[i].ch_name[0] = 0; 143 sc->sc_channels[i].ch_softc = &sc->sc_dev; 144 sc->sc_channels[i].ch_map = 145 (void*) pmap_extract (pmap, (vaddr_t) &dmac_map[i]); 146 bus_space_subregion(sc->sc_bst, sc->sc_bht, 147 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 148 &sc->sc_channels[i].ch_bht); 149 } 150 151 return; 152 } 153 154 155 /* 156 * Channel initialization/deinitialization per user device. 157 */ 158 struct dmac_channel_stat * 159 dmac_alloc_channel(self, ch, name, 160 normalv, normal, normalarg, 161 errorv, error, errorarg) 162 struct device *self; 163 int ch; 164 char *name; 165 int normalv, errorv; 166 dmac_intr_handler_t normal, error; 167 void *normalarg, *errorarg; 168 { 169 struct intio_softc *intio = (void*) self; 170 struct dmac_softc *sc = (void*) intio->sc_dmac; 171 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 172 char intrname[16]; 173 174 #ifdef DIAGNOSTIC 175 if (ch < 0 || ch >= DMAC_NCHAN) 176 panic ("Invalid DMAC channel."); 177 if (chan->ch_name[0]) 178 panic ("DMAC: channel in use."); 179 if (strlen(name) > 8) 180 panic ("DMAC: wrong user name."); 181 #endif 182 183 /* fill the channel status structure. */ 184 strcpy(chan->ch_name, name); 185 chan->ch_dcr = (DMAC_DCR_XRM_CSWOH | DMAC_DCR_OTYP_EASYNC | 186 DMAC_DCR_OPS_8BIT); 187 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_CHAIN_ARRAY | 188 DMAC_OCR_REQG_EXTERNAL); 189 chan->ch_normalv = normalv; 190 chan->ch_errorv = errorv; 191 chan->ch_normal = normal; 192 chan->ch_error = error; 193 chan->ch_normalarg = normalarg; 194 chan->ch_errorarg = errorarg; 195 chan->ch_xfer_in_progress = 0; 196 197 /* setup the device-specific registers */ 198 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 199 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 200 DMAC_REG_DCR, chan->ch_dcr); 201 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 202 203 /* 204 * X68k physical user space is a subset of the kernel space; 205 * the memory is always included in the physical user space, 206 * while the device is not. 207 */ 208 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 209 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 210 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 211 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 212 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 213 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 214 215 /* setup the interrupt handlers */ 216 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 217 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 218 219 strcpy(intrname, name); 220 strcat(intrname, "dma"); 221 intio_intr_establish (normalv, intrname, dmac_done, chan); 222 223 strcpy(intrname, name); 224 strcat(intrname, "dmaerr"); 225 intio_intr_establish (errorv, intrname, dmac_error, chan); 226 227 return chan; 228 } 229 230 int 231 dmac_free_channel(self, ch, channel) 232 struct device *self; 233 int ch; 234 void *channel; 235 { 236 struct dmac_softc *sc = (void*) self; 237 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 238 239 if (chan != channel) 240 return -1; 241 if (ch != chan->ch_channel) 242 return -1; 243 #if DIAGNOSTIC 244 if (chan->ch_xfer_in_progress) 245 panic ("dmac_free_channel: DMA transfer in progress"); 246 #endif 247 248 chan->ch_name[0] = 0; 249 intio_intr_disestablish(chan->ch_normalv, channel); 250 intio_intr_disestablish(chan->ch_errorv, channel); 251 252 return 0; 253 } 254 255 /* 256 * Initialization / deinitialization per transfer. 257 */ 258 struct dmac_dma_xfer * 259 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 260 struct dmac_channel_stat *chan; 261 bus_dma_tag_t dmat; 262 bus_dmamap_t dmamap; 263 int dir, scr; 264 void *dar; 265 { 266 struct dmac_dma_xfer *r = malloc (sizeof (struct dmac_dma_xfer), 267 M_DEVBUF, M_WAITOK); 268 269 r->dx_channel = chan; 270 r->dx_dmamap = dmamap; 271 r->dx_tag = dmat; 272 r->dx_ocr = dir & DMAC_OCR_DIR_MASK; 273 r->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 274 r->dx_device = dar; 275 r->dx_done = 0; 276 277 return r; 278 } 279 280 #ifdef DMAC_DEBUG 281 static struct dmac_channel_stat *debugchan = 0; 282 #endif 283 284 #ifdef DMAC_DEBUG 285 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 286 dnivr, deivr, ddfcr, dmfcr, dbfcr; 287 static u_int16_t dmtcr, dbtcr; 288 static u_int32_t ddar, dmar, dbar; 289 #endif 290 /* 291 * Do the actual transfer. 292 */ 293 int 294 dmac_start_xfer(self, xf) 295 struct device *self; 296 struct dmac_dma_xfer *xf; 297 { 298 struct dmac_softc *sc = (void*) self; 299 struct dmac_channel_stat *chan = xf->dx_channel; 300 int c; 301 302 303 #ifdef DMAC_DEBUG 304 debugchan=chan; 305 #endif 306 bus_space_write_1(sc->sc_bst, chan->ch_bht, 307 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 308 bus_space_write_1(sc->sc_bst, chan->ch_bht, 309 DMAC_REG_SCR, xf->dx_scr); 310 311 /* program DMAC in array chainning mode */ 312 xf->dx_done = 0; 313 DPRINTF (3, ("First program:\n")); 314 c = dmac_program_arraychain(self, xf); 315 316 /* setup the address/count registers */ 317 bus_space_write_4(sc->sc_bst, chan->ch_bht, 318 DMAC_REG_BAR, (int) chan->ch_map); 319 bus_space_write_4(sc->sc_bst, chan->ch_bht, 320 DMAC_REG_DAR, (int) xf->dx_device); 321 bus_space_write_1(sc->sc_bst, chan->ch_bht, 322 DMAC_REG_CSR, 0xff); 323 bus_space_write_2(sc->sc_bst, chan->ch_bht, 324 DMAC_REG_BTCR, c); 325 326 /* START!! */ 327 DDUMPREGS (3, ("first start\n")); 328 #ifdef DMAC_DEBUG 329 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 330 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 331 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 332 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 333 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 334 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 335 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 336 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 337 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 338 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 339 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 340 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 341 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 342 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 343 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 344 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 345 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 346 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 347 #endif 348 #if defined(M68040) || defined(M68060) 349 if (mmutype == MMU_68040) 350 dma_cachectl((caddr_t) &dmac_map[chan->ch_channel], 351 sizeof(struct dmac_sg_array)*DMAC_MAPSIZE); 352 #endif 353 bus_space_write_1(sc->sc_bst, chan->ch_bht, 354 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 355 chan->ch_xfer_in_progress = xf; 356 357 return 0; 358 } 359 360 static int 361 dmac_program_arraychain(self, xf) 362 struct device *self; 363 struct dmac_dma_xfer *xf; 364 { 365 struct dmac_softc *sc = (void*) self; 366 struct dmac_channel_stat *chan = xf->dx_channel; 367 int ch = chan->ch_channel; 368 struct x68k_bus_dmamap *map = xf->dx_dmamap; 369 int i, j; 370 371 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 372 i++, j++) { 373 dmac_map[ch][i].da_addr = map->dm_segs[j].ds_addr; 374 #ifdef DIAGNOSTIC 375 if (map->dm_segs[j].ds_len > 0xff00) 376 panic ("dmac_program_arraychain: wrong map: %d", map->dm_segs[j].ds_len); 377 #endif 378 dmac_map[ch][i].da_count = map->dm_segs[j].ds_len; 379 } 380 xf->dx_done = j; 381 382 return i; 383 } 384 385 /* 386 * interrupt handlers. 387 */ 388 static int 389 dmac_done(arg) 390 void *arg; 391 { 392 struct dmac_channel_stat *chan = arg; 393 struct dmac_softc *sc = (void*) chan->ch_softc; 394 struct dmac_dma_xfer *xf = chan->ch_xfer_in_progress; 395 struct x68k_bus_dmamap *map = xf->dx_dmamap; 396 int c; 397 398 DPRINTF (3, ("dmac_done\n")); 399 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 400 401 if (xf->dx_done == map->dm_nsegs) { 402 /* Done */ 403 chan->ch_xfer_in_progress = 0; 404 return (*chan->ch_normal) (chan->ch_normalarg); 405 } 406 407 /* Continue transfer */ 408 DPRINTF (3, ("reprograming\n")); 409 c = dmac_program_arraychain (&sc->sc_dev, xf); 410 411 bus_space_write_4(sc->sc_bst, chan->ch_bht, 412 DMAC_REG_BAR, (int) chan->ch_map); 413 bus_space_write_4(sc->sc_bst, chan->ch_bht, 414 DMAC_REG_DAR, (int) xf->dx_device); 415 bus_space_write_1(sc->sc_bst, chan->ch_bht, 416 DMAC_REG_CSR, 0xff); 417 bus_space_write_2(sc->sc_bst, chan->ch_bht, 418 DMAC_REG_BTCR, c); 419 420 /* START!! */ 421 DDUMPREGS (3, ("restart\n")); 422 bus_space_write_1(sc->sc_bst, chan->ch_bht, 423 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 424 425 return 1; 426 } 427 428 static int 429 dmac_error(arg) 430 void *arg; 431 { 432 struct dmac_channel_stat *chan = arg; 433 struct dmac_softc *sc = (void*) chan->ch_softc; 434 435 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 436 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 437 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 438 DPRINTF(5, ("registers were:\n")); 439 #ifdef DMAC_DEBUG 440 if ((dmacdebug & 0x0f) > 5) { 441 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 442 "CCR=%02x, CPR=%02x, GCR=%02x\n", 443 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 444 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 445 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 446 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 447 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 448 ddar, dmar, dbar); 449 } 450 #endif 451 452 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 453 DDUMPREGS(3, ("dmac_error\n")); 454 455 return (*chan->ch_error) (chan->ch_errorarg); 456 } 457 458 459 #ifdef DMAC_DEBUG 460 static int 461 dmac_dump_regs(void) 462 { 463 struct dmac_channel_stat *chan = debugchan; 464 struct dmac_softc *sc; 465 466 if ((chan == 0) || (dmacdebug & 0xf0)) return; 467 sc = (void*) chan->ch_softc; 468 469 printf ("DMAC channel %d registers\n", chan->ch_channel); 470 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 471 "CCR=%02x, CPR=%02x, GCR=%02x\n", 472 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 473 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 474 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 475 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 476 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 477 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 478 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 479 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 480 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 481 "MFCR=%02x, BFCR=%02x\n", 482 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 483 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 484 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 485 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 486 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 487 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 488 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 489 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 490 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 491 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 492 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 493 494 return 0; 495 } 496 #endif 497
Indexes created Thu Oct 02 14:10:14 GMT 2025