intio_dmac.c revision 1.11
1 /* $NetBSD: intio_dmac.c,v 1.11 2001/05/27 02:18:07 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include "opt_m680x0.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 #ifdef DMAC_ARRAYCHAIN 68 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*, 69 u_int, u_int)); 70 #endif 71 static int dmac_done __P((void*)); 72 static int dmac_error __P((void*)); 73 74 #ifdef DMAC_DEBUG 75 static int dmac_dump_regs __P((void)); 76 #endif 77 78 /* 79 * autoconf stuff 80 */ 81 static int dmac_match __P((struct device *, struct cfdata *, void *)); 82 static void dmac_attach __P((struct device *, struct device *, void *)); 83 84 struct cfattach dmac_ca = { 85 sizeof(struct dmac_softc), dmac_match, dmac_attach 86 }; 87 88 static int 89 dmac_match(parent, cf, aux) 90 struct device *parent; 91 struct cfdata *cf; 92 void *aux; 93 { 94 struct intio_attach_args *ia = aux; 95 96 if (strcmp (ia->ia_name, "dmac") != 0) 97 return (0); 98 if (cf->cf_unit != 0) 99 return (0); 100 101 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 102 ia->ia_addr = DMAC_ADDR; 103 104 /* fixed address */ 105 if (ia->ia_addr != DMAC_ADDR) 106 return (0); 107 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 108 return (0); 109 110 return 1; 111 } 112 113 static void 114 dmac_attach(parent, self, aux) 115 struct device *parent, *self; 116 void *aux; 117 { 118 struct dmac_softc *sc = (struct dmac_softc *)self; 119 struct intio_attach_args *ia = aux; 120 int r; 121 122 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 123 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 124 #ifdef DIAGNOSTIC 125 if (r) 126 panic ("IO map for DMAC corruption??"); 127 #endif 128 129 ((struct intio_softc*) parent)->sc_dmac = self; 130 sc->sc_bst = ia->ia_bst; 131 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 132 dmac_init_channels(sc); 133 134 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 135 } 136 137 static void 138 dmac_init_channels(sc) 139 struct dmac_softc *sc; 140 { 141 int i; 142 pmap_t pmap = pmap_kernel(); 143 144 DPRINTF (3, ("dmac_init_channels\n")); 145 for (i=0; i<DMAC_NCHAN; i++) { 146 sc->sc_channels[i].ch_channel = i; 147 sc->sc_channels[i].ch_name[0] = 0; 148 sc->sc_channels[i].ch_softc = &sc->sc_dev; 149 bus_space_subregion(sc->sc_bst, sc->sc_bht, 150 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 151 &sc->sc_channels[i].ch_bht); 152 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 153 /* reset the status register */ 154 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 155 DMAC_REG_CSR, 0xff); 156 } 157 158 return; 159 } 160 161 162 /* 163 * Channel initialization/deinitialization per user device. 164 */ 165 struct dmac_channel_stat * 166 dmac_alloc_channel(self, ch, name, 167 normalv, normal, normalarg, 168 errorv, error, errorarg) 169 struct device *self; 170 int ch; 171 char *name; 172 int normalv, errorv; 173 dmac_intr_handler_t normal, error; 174 void *normalarg, *errorarg; 175 { 176 struct intio_softc *intio = (void*) self; 177 struct dmac_softc *sc = (void*) intio->sc_dmac; 178 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 179 char intrname[16]; 180 int r, dummy; 181 182 printf ("%s: allocating ch %d for %s.\n", 183 sc->sc_dev.dv_xname, ch, name); 184 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 185 #ifdef DIAGNOSTIC 186 if (ch < 0 || ch >= DMAC_NCHAN) 187 panic ("Invalid DMAC channel."); 188 if (chan->ch_name[0]) 189 panic ("DMAC: channel in use."); 190 if (strlen(name) > 8) 191 panic ("DMAC: wrong user name."); 192 #endif 193 194 #ifdef DMAC_ARRAYCHAIN 195 /* allocate the DMAC arraychaining map */ 196 r = bus_dmamem_alloc(intio->sc_dmat, 197 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 198 4, 0, &chan->ch_seg[0], 1, &dummy, 199 BUS_DMA_NOWAIT); 200 if (r) 201 panic ("DMAC: cannot alloc DMA safe memory"); 202 r = bus_dmamem_map(intio->sc_dmat, 203 &chan->ch_seg[0], 1, 204 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 205 (caddr_t*) &chan->ch_map, 206 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 207 if (r) 208 panic ("DMAC: cannot map DMA safe memory"); 209 #endif 210 211 /* fill the channel status structure by the default values. */ 212 strcpy(chan->ch_name, name); 213 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 214 DMAC_DCR_OPS_8BIT); 215 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 216 chan->ch_normalv = normalv; 217 chan->ch_errorv = errorv; 218 chan->ch_normal = normal; 219 chan->ch_error = error; 220 chan->ch_normalarg = normalarg; 221 chan->ch_errorarg = errorarg; 222 chan->ch_xfer.dx_dmamap = 0; 223 224 /* setup the device-specific registers */ 225 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 226 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 227 DMAC_REG_DCR, chan->ch_dcr); 228 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 229 230 /* 231 * X68k physical user space is a subset of the kernel space; 232 * the memory is always included in the physical user space, 233 * while the device is not. 234 */ 235 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 236 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 237 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 238 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 239 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 240 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 241 242 /* setup the interrupt handlers */ 243 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 244 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 245 246 strcpy(intrname, name); 247 strcat(intrname, "dma"); 248 intio_intr_establish (normalv, intrname, dmac_done, chan); 249 250 strcpy(intrname, name); 251 strcat(intrname, "dmaerr"); 252 intio_intr_establish (errorv, intrname, dmac_error, chan); 253 254 return chan; 255 } 256 257 int 258 dmac_free_channel(self, ch, channel) 259 struct device *self; 260 int ch; 261 void *channel; 262 { 263 struct intio_softc *intio = (void*) self; 264 struct dmac_softc *sc = (void*) intio->sc_dmac; 265 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 266 267 DPRINTF (3, ("dmac_free_channel, %d\n", ch)); 268 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 269 if (chan != channel) 270 return -1; 271 if (ch != chan->ch_channel) 272 return -1; 273 274 #ifdef DMAC_ARRAYCHAIN 275 bus_dmamem_unmap(intio->sc_dmat, (caddr_t) chan->ch_map, 276 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 277 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 278 #endif 279 chan->ch_name[0] = 0; 280 intio_intr_disestablish(chan->ch_normalv, channel); 281 intio_intr_disestablish(chan->ch_errorv, channel); 282 283 return 0; 284 } 285 286 /* 287 * Initialization / deinitialization per transfer. 288 */ 289 struct dmac_dma_xfer * 290 dmac_alloc_xfer (chan, dmat, dmamap) 291 struct dmac_channel_stat *chan; 292 bus_dma_tag_t dmat; 293 bus_dmamap_t dmamap; 294 { 295 struct dmac_dma_xfer *xf = &chan->ch_xfer; 296 struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc; 297 298 DPRINTF (3, ("dmac_alloc_xfer\n")); 299 xf->dx_channel = chan; 300 xf->dx_dmamap = dmamap; 301 xf->dx_tag = dmat; 302 #ifdef DMAC_ARRAYCHAIN 303 xf->dx_array = chan->ch_map; 304 xf->dx_done = 0; 305 #endif 306 xf->dx_nextoff = xf->dx_nextsize = -1; 307 return xf; 308 } 309 310 int 311 dmac_load_xfer (self, xf) 312 struct device *self; 313 struct dmac_dma_xfer *xf; 314 { 315 struct dmac_softc *sc = (void*) self; 316 struct dmac_channel_stat *chan = xf->dx_channel; 317 318 DPRINTF (3, ("dmac_load_xfer\n")); 319 320 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 321 if (xf->dx_dmamap->dm_nsegs == 1) 322 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 323 else { 324 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 325 xf->dx_nextoff = ~0; 326 xf->dx_nextsize = ~0; 327 } 328 329 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 330 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 331 bus_space_write_1(sc->sc_bst, chan->ch_bht, 332 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 333 bus_space_write_4(sc->sc_bst, chan->ch_bht, 334 DMAC_REG_DAR, (int) xf->dx_device); 335 336 return 0; 337 } 338 339 struct dmac_dma_xfer * 340 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 341 struct dmac_channel_stat *chan; 342 bus_dma_tag_t dmat; 343 bus_dmamap_t dmamap; 344 int dir, scr; 345 void *dar; 346 { 347 struct dmac_dma_xfer *xf; 348 struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc; 349 350 xf = dmac_alloc_xfer(chan, dmat, dmamap); 351 352 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 353 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 354 xf->dx_device = dar; 355 356 dmac_load_xfer(&sc->sc_dev, xf); 357 358 return xf; 359 } 360 361 #ifdef DMAC_DEBUG 362 static struct dmac_channel_stat *debugchan = 0; 363 #endif 364 365 #ifdef DMAC_DEBUG 366 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 367 dnivr, deivr, ddfcr, dmfcr, dbfcr; 368 static u_int16_t dmtcr, dbtcr; 369 static u_int32_t ddar, dmar, dbar; 370 #endif 371 /* 372 * Do the actual transfer. 373 */ 374 int 375 dmac_start_xfer(self, xf) 376 struct device *self; 377 struct dmac_dma_xfer *xf; 378 { 379 return dmac_start_xfer_offset(self, xf, 0, 0); 380 } 381 382 int 383 dmac_start_xfer_offset(self, xf, offset, size) 384 struct device *self; 385 struct dmac_dma_xfer *xf; 386 u_int offset; 387 u_int size; 388 { 389 struct dmac_softc *sc = (void*) self; 390 struct dmac_channel_stat *chan = xf->dx_channel; 391 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 392 int c, go = DMAC_CCR_STR|DMAC_CCR_INT; 393 394 DPRINTF (3, ("dmac_start_xfer\n")); 395 #ifdef DMAC_DEBUG 396 debugchan=chan; 397 #endif 398 399 if (size == 0) { 400 #ifdef DIAGNOSTIC 401 if (offset != 0) 402 panic ("dmac_start_xfer_offset: invalid offset %x", 403 offset); 404 #endif 405 size = dmamap->dm_mapsize; 406 } 407 408 #ifdef DMAC_ARRAYCHAIN 409 #ifdef DIAGNOSTIC 410 if (xf->dx_done) 411 panic("dmac_start_xfer: DMA transfer in progress"); 412 #endif 413 #endif 414 DPRINTF (3, ("First program:\n")); 415 #ifdef DIAGNOSTIC 416 if ((offset >= dmamap->dm_mapsize) || 417 (offset + size > dmamap->dm_mapsize)) 418 panic ("dmac_start_xfer_offset: invalid offset: " 419 "offset=%d, size=%d, mapsize=%d", 420 offset, size, dmamap->dm_mapsize); 421 #endif 422 /* program DMAC in single block mode or array chainning mode */ 423 if (dmamap->dm_nsegs == 1) { 424 DPRINTF(3, ("single block mode\n")); 425 #ifdef DIAGNOSTIC 426 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 427 panic ("dmac_start_xfer_offset: dmamap curruption"); 428 #endif 429 if (offset == xf->dx_nextoff && 430 size == xf->dx_nextsize) { 431 /* Use continued operation */ 432 go |= DMAC_CCR_CNT; 433 xf->dx_nextoff += size; 434 } else { 435 bus_space_write_4(sc->sc_bst, chan->ch_bht, 436 DMAC_REG_MAR, 437 (int) dmamap->dm_segs[0].ds_addr 438 + offset); 439 bus_space_write_2(sc->sc_bst, chan->ch_bht, 440 DMAC_REG_MTCR, (int) size); 441 xf->dx_nextoff = offset; 442 xf->dx_nextsize = size; 443 } 444 #ifdef DMAC_ARRAYCHAIN 445 xf->dx_done = 1; 446 #endif 447 } else { 448 #ifdef DMAC_ARRAYCHAIN 449 c = dmac_program_arraychain(self, xf, offset, size); 450 bus_space_write_4(sc->sc_bst, chan->ch_bht, 451 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 452 bus_space_write_2(sc->sc_bst, chan->ch_bht, 453 DMAC_REG_BTCR, c); 454 #else 455 panic ("DMAC: unexpected use of arraychaining mode"); 456 #endif 457 } 458 459 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 460 461 /* START!! */ 462 DDUMPREGS (3, ("first start\n")); 463 #ifdef DMAC_DEBUG 464 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 465 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 466 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 467 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 468 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 469 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 470 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 471 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 472 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 473 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 474 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 475 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 476 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 477 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 478 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 479 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 480 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 481 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 482 #endif 483 #ifdef DMAC_ARRAYCHAIN 484 #if defined(M68040) || defined(M68060) 485 /* flush data cache for the map */ 486 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 487 dma_cachectl((caddr_t) xf->dx_array, 488 sizeof(struct dmac_sg_array) * c); 489 #endif 490 #endif 491 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 492 493 if (xf->dx_nextoff != ~0) { 494 bus_space_write_4(sc->sc_bst, chan->ch_bht, 495 DMAC_REG_BAR, xf->dx_nextoff); 496 bus_space_write_2(sc->sc_bst, chan->ch_bht, 497 DMAC_REG_BTCR, xf->dx_nextsize); 498 } 499 500 return 0; 501 } 502 503 #ifdef DMAC_ARRAYCHAIN 504 static int 505 dmac_program_arraychain(self, xf, offset, size) 506 struct device *self; 507 struct dmac_dma_xfer *xf; 508 u_int offset; 509 u_int size; 510 { 511 struct dmac_channel_stat *chan = xf->dx_channel; 512 int ch = chan->ch_channel; 513 struct x68k_bus_dmamap *map = xf->dx_dmamap; 514 int i, j; 515 516 /* XXX not yet!! */ 517 if (offset != 0 || size != map->dm_mapsize) 518 panic ("dmac_program_arraychain: unsupported offset/size"); 519 520 DPRINTF (3, ("dmac_program_arraychain\n")); 521 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 522 i++, j++) { 523 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 524 #ifdef DIAGNOSTIC 525 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 526 panic ("dmac_program_arraychain: wrong map: %ld", 527 map->dm_segs[j].ds_len); 528 #endif 529 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 530 } 531 xf->dx_done = j; 532 533 return i; 534 } 535 #endif 536 537 /* 538 * interrupt handlers. 539 */ 540 static int 541 dmac_done(arg) 542 void *arg; 543 { 544 struct dmac_channel_stat *chan = arg; 545 struct dmac_softc *sc = (void*) chan->ch_softc; 546 struct dmac_dma_xfer *xf = &chan->ch_xfer; 547 struct x68k_bus_dmamap *map = xf->dx_dmamap; 548 int c; 549 550 DPRINTF (3, ("dmac_done\n")); 551 552 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 553 554 #ifdef DMAC_ARRAYCHAIN 555 if (xf->dx_done == map->dm_nsegs) { 556 xf->dx_done = 0; 557 #endif 558 /* Done */ 559 return (*chan->ch_normal) (chan->ch_normalarg); 560 #ifdef DMAC_ARRAYCHAIN 561 } 562 #endif 563 564 #ifdef DMAC_ARRAYCHAIN 565 /* Continue transfer */ 566 DPRINTF (3, ("reprograming\n")); 567 c = dmac_program_arraychain (&sc->sc_dev, xf, 0, map->dm_mapsize); 568 569 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 570 bus_space_write_4(sc->sc_bst, chan->ch_bht, 571 DMAC_REG_BAR, (int) chan->ch_map); 572 bus_space_write_4(sc->sc_bst, chan->ch_bht, 573 DMAC_REG_DAR, (int) xf->dx_device); 574 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 575 576 /* START!! */ 577 DDUMPREGS (3, ("restart\n")); 578 bus_space_write_1(sc->sc_bst, chan->ch_bht, 579 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 580 581 return 1; 582 #endif 583 } 584 585 static int 586 dmac_error(arg) 587 void *arg; 588 { 589 struct dmac_channel_stat *chan = arg; 590 struct dmac_softc *sc = (void*) chan->ch_softc; 591 592 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 593 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 594 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 595 DPRINTF(5, ("registers were:\n")); 596 #ifdef DMAC_DEBUG 597 if ((dmacdebug & 0x0f) > 5) { 598 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 599 "CCR=%02x, CPR=%02x, GCR=%02x\n", 600 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 601 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 602 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 603 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 604 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 605 ddar, dmar, dbar); 606 } 607 #endif 608 609 /* Clear the status bits */ 610 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 611 DDUMPREGS(3, ("dmac_error\n")); 612 613 #ifdef DMAC_ARRAYCHAIN 614 chan->ch_xfer.dx_done = 0; 615 #endif 616 617 return (*chan->ch_error) (chan->ch_errorarg); 618 } 619 620 int 621 dmac_abort_xfer(self, xf) 622 struct device *self; 623 struct dmac_dma_xfer *xf; 624 { 625 struct dmac_softc *sc = (void*) self; 626 struct dmac_channel_stat *chan = xf->dx_channel; 627 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 628 629 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 630 DMAC_CCR_INT | DMAC_CCR_HLT); 631 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 632 xf->dx_nextoff = xf->dx_nextsize = -1; 633 634 return 0; 635 } 636 637 #ifdef DMAC_DEBUG 638 static int 639 dmac_dump_regs(void) 640 { 641 struct dmac_channel_stat *chan = debugchan; 642 struct dmac_softc *sc; 643 644 if ((chan == 0) || (dmacdebug & 0xf0)) return; 645 sc = (void*) chan->ch_softc; 646 647 printf ("DMAC channel %d registers\n", chan->ch_channel); 648 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 649 "CCR=%02x, CPR=%02x, GCR=%02x\n", 650 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 651 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 652 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 653 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 654 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 655 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 656 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 657 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 658 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 659 "MFCR=%02x, BFCR=%02x\n", 660 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 661 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 662 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 663 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 664 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 665 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 666 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 667 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 668 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 669 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 670 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 671 672 return 0; 673 } 674 #endif 675
Indexes created Thu Sep 25 16:09:42 GMT 2025