intio_dmac.c revision 1.13
1 /* $NetBSD: intio_dmac.c,v 1.13 2002/08/03 06:38:41 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include "opt_m680x0.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 #ifdef DMAC_ARRAYCHAIN 68 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*, 69 u_int, u_int)); 70 #endif 71 static int dmac_done __P((void*)); 72 static int dmac_error __P((void*)); 73 74 #ifdef DMAC_DEBUG 75 static int dmac_dump_regs __P((void)); 76 #endif 77 78 /* 79 * autoconf stuff 80 */ 81 static int dmac_match __P((struct device *, struct cfdata *, void *)); 82 static void dmac_attach __P((struct device *, struct device *, void *)); 83 84 struct cfattach dmac_ca = { 85 sizeof(struct dmac_softc), dmac_match, dmac_attach 86 }; 87 88 static int 89 dmac_match(parent, cf, aux) 90 struct device *parent; 91 struct cfdata *cf; 92 void *aux; 93 { 94 struct intio_attach_args *ia = aux; 95 96 if (strcmp (ia->ia_name, "dmac") != 0) 97 return (0); 98 if (cf->cf_unit != 0) 99 return (0); 100 101 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 102 ia->ia_addr = DMAC_ADDR; 103 104 /* fixed address */ 105 if (ia->ia_addr != DMAC_ADDR) 106 return (0); 107 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 108 return (0); 109 110 return 1; 111 } 112 113 static void 114 dmac_attach(parent, self, aux) 115 struct device *parent, *self; 116 void *aux; 117 { 118 struct dmac_softc *sc = (struct dmac_softc *)self; 119 struct intio_attach_args *ia = aux; 120 int r; 121 122 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 123 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 124 #ifdef DIAGNOSTIC 125 if (r) 126 panic ("IO map for DMAC corruption??"); 127 #endif 128 129 ((struct intio_softc*) parent)->sc_dmac = self; 130 sc->sc_bst = ia->ia_bst; 131 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 132 dmac_init_channels(sc); 133 134 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 135 } 136 137 static void 138 dmac_init_channels(sc) 139 struct dmac_softc *sc; 140 { 141 int i; 142 143 DPRINTF (3, ("dmac_init_channels\n")); 144 for (i=0; i<DMAC_NCHAN; i++) { 145 sc->sc_channels[i].ch_channel = i; 146 sc->sc_channels[i].ch_name[0] = 0; 147 sc->sc_channels[i].ch_softc = &sc->sc_dev; 148 bus_space_subregion(sc->sc_bst, sc->sc_bht, 149 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 150 &sc->sc_channels[i].ch_bht); 151 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 152 /* reset the status register */ 153 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 154 DMAC_REG_CSR, 0xff); 155 } 156 157 return; 158 } 159 160 161 /* 162 * Channel initialization/deinitialization per user device. 163 */ 164 struct dmac_channel_stat * 165 dmac_alloc_channel(self, ch, name, 166 normalv, normal, normalarg, 167 errorv, error, errorarg) 168 struct device *self; 169 int ch; 170 char *name; 171 int normalv, errorv; 172 dmac_intr_handler_t normal, error; 173 void *normalarg, *errorarg; 174 { 175 struct intio_softc *intio = (void*) self; 176 struct dmac_softc *sc = (void*) intio->sc_dmac; 177 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 178 char intrname[16]; 179 #ifdef DMAC_ARRAYCHAIN 180 int r, dummy; 181 #endif 182 183 printf ("%s: allocating ch %d for %s.\n", 184 sc->sc_dev.dv_xname, ch, name); 185 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 186 #ifdef DIAGNOSTIC 187 if (ch < 0 || ch >= DMAC_NCHAN) 188 panic ("Invalid DMAC channel."); 189 if (chan->ch_name[0]) 190 panic ("DMAC: channel in use."); 191 if (strlen(name) > 8) 192 panic ("DMAC: wrong user name."); 193 #endif 194 195 #ifdef DMAC_ARRAYCHAIN 196 /* allocate the DMAC arraychaining map */ 197 r = bus_dmamem_alloc(intio->sc_dmat, 198 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 199 4, 0, &chan->ch_seg[0], 1, &dummy, 200 BUS_DMA_NOWAIT); 201 if (r) 202 panic ("DMAC: cannot alloc DMA safe memory"); 203 r = bus_dmamem_map(intio->sc_dmat, 204 &chan->ch_seg[0], 1, 205 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 206 (caddr_t*) &chan->ch_map, 207 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 208 if (r) 209 panic ("DMAC: cannot map DMA safe memory"); 210 #endif 211 212 /* fill the channel status structure by the default values. */ 213 strcpy(chan->ch_name, name); 214 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 215 DMAC_DCR_OPS_8BIT); 216 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 217 chan->ch_normalv = normalv; 218 chan->ch_errorv = errorv; 219 chan->ch_normal = normal; 220 chan->ch_error = error; 221 chan->ch_normalarg = normalarg; 222 chan->ch_errorarg = errorarg; 223 chan->ch_xfer.dx_dmamap = 0; 224 225 /* setup the device-specific registers */ 226 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 227 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 228 DMAC_REG_DCR, chan->ch_dcr); 229 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 230 231 /* 232 * X68k physical user space is a subset of the kernel space; 233 * the memory is always included in the physical user space, 234 * while the device is not. 235 */ 236 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 237 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 238 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 239 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 240 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 241 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 242 243 /* setup the interrupt handlers */ 244 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 245 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 246 247 strcpy(intrname, name); 248 strcat(intrname, "dma"); 249 intio_intr_establish (normalv, intrname, dmac_done, chan); 250 251 strcpy(intrname, name); 252 strcat(intrname, "dmaerr"); 253 intio_intr_establish (errorv, intrname, dmac_error, chan); 254 255 return chan; 256 } 257 258 int 259 dmac_free_channel(self, ch, channel) 260 struct device *self; 261 int ch; 262 void *channel; 263 { 264 struct intio_softc *intio = (void*) self; 265 struct dmac_softc *sc = (void*) intio->sc_dmac; 266 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 267 268 DPRINTF (3, ("dmac_free_channel, %d\n", ch)); 269 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 270 if (chan != channel) 271 return -1; 272 if (ch != chan->ch_channel) 273 return -1; 274 275 #ifdef DMAC_ARRAYCHAIN 276 bus_dmamem_unmap(intio->sc_dmat, (caddr_t) chan->ch_map, 277 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 278 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 279 #endif 280 chan->ch_name[0] = 0; 281 intio_intr_disestablish(chan->ch_normalv, channel); 282 intio_intr_disestablish(chan->ch_errorv, channel); 283 284 return 0; 285 } 286 287 /* 288 * Initialization / deinitialization per transfer. 289 */ 290 struct dmac_dma_xfer * 291 dmac_alloc_xfer (chan, dmat, dmamap) 292 struct dmac_channel_stat *chan; 293 bus_dma_tag_t dmat; 294 bus_dmamap_t dmamap; 295 { 296 struct dmac_dma_xfer *xf = &chan->ch_xfer; 297 298 DPRINTF (3, ("dmac_alloc_xfer\n")); 299 xf->dx_channel = chan; 300 xf->dx_dmamap = dmamap; 301 xf->dx_tag = dmat; 302 #ifdef DMAC_ARRAYCHAIN 303 xf->dx_array = chan->ch_map; 304 xf->dx_done = 0; 305 #endif 306 xf->dx_nextoff = xf->dx_nextsize = -1; 307 return xf; 308 } 309 310 int 311 dmac_load_xfer (self, xf) 312 struct device *self; 313 struct dmac_dma_xfer *xf; 314 { 315 struct dmac_softc *sc = (void*) self; 316 struct dmac_channel_stat *chan = xf->dx_channel; 317 318 DPRINTF (3, ("dmac_load_xfer\n")); 319 320 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 321 if (xf->dx_dmamap->dm_nsegs == 1) 322 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 323 else { 324 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 325 xf->dx_nextoff = ~0; 326 xf->dx_nextsize = ~0; 327 } 328 329 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 330 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 331 bus_space_write_1(sc->sc_bst, chan->ch_bht, 332 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 333 bus_space_write_4(sc->sc_bst, chan->ch_bht, 334 DMAC_REG_DAR, (int) xf->dx_device); 335 336 return 0; 337 } 338 339 struct dmac_dma_xfer * 340 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 341 struct dmac_channel_stat *chan; 342 bus_dma_tag_t dmat; 343 bus_dmamap_t dmamap; 344 int dir, scr; 345 void *dar; 346 { 347 struct dmac_dma_xfer *xf; 348 struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc; 349 350 xf = dmac_alloc_xfer(chan, dmat, dmamap); 351 352 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 353 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 354 xf->dx_device = dar; 355 356 dmac_load_xfer(&sc->sc_dev, xf); 357 358 return xf; 359 } 360 361 #ifdef DMAC_DEBUG 362 static struct dmac_channel_stat *debugchan = 0; 363 #endif 364 365 #ifdef DMAC_DEBUG 366 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 367 dnivr, deivr, ddfcr, dmfcr, dbfcr; 368 static u_int16_t dmtcr, dbtcr; 369 static u_int32_t ddar, dmar, dbar; 370 #endif 371 /* 372 * Do the actual transfer. 373 */ 374 int 375 dmac_start_xfer(self, xf) 376 struct device *self; 377 struct dmac_dma_xfer *xf; 378 { 379 return dmac_start_xfer_offset(self, xf, 0, 0); 380 } 381 382 int 383 dmac_start_xfer_offset(self, xf, offset, size) 384 struct device *self; 385 struct dmac_dma_xfer *xf; 386 u_int offset; 387 u_int size; 388 { 389 struct dmac_softc *sc = (void*) self; 390 struct dmac_channel_stat *chan = xf->dx_channel; 391 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 392 int go = DMAC_CCR_STR|DMAC_CCR_INT; 393 #ifdef DMAC_ARRAYCHAIN 394 int c; 395 #endif 396 397 DPRINTF (3, ("dmac_start_xfer\n")); 398 #ifdef DMAC_DEBUG 399 debugchan=chan; 400 #endif 401 402 if (size == 0) { 403 #ifdef DIAGNOSTIC 404 if (offset != 0) 405 panic ("dmac_start_xfer_offset: invalid offset %x", 406 offset); 407 #endif 408 size = dmamap->dm_mapsize; 409 } 410 411 #ifdef DMAC_ARRAYCHAIN 412 #ifdef DIAGNOSTIC 413 if (xf->dx_done) 414 panic("dmac_start_xfer: DMA transfer in progress"); 415 #endif 416 #endif 417 DPRINTF (3, ("First program:\n")); 418 #ifdef DIAGNOSTIC 419 if ((offset >= dmamap->dm_mapsize) || 420 (offset + size > dmamap->dm_mapsize)) 421 panic ("dmac_start_xfer_offset: invalid offset: " 422 "offset=%d, size=%d, mapsize=%d", 423 offset, size, dmamap->dm_mapsize); 424 #endif 425 /* program DMAC in single block mode or array chainning mode */ 426 if (dmamap->dm_nsegs == 1) { 427 DPRINTF(3, ("single block mode\n")); 428 #ifdef DIAGNOSTIC 429 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 430 panic ("dmac_start_xfer_offset: dmamap curruption"); 431 #endif 432 if (offset == xf->dx_nextoff && 433 size == xf->dx_nextsize) { 434 /* Use continued operation */ 435 go |= DMAC_CCR_CNT; 436 xf->dx_nextoff += size; 437 } else { 438 bus_space_write_4(sc->sc_bst, chan->ch_bht, 439 DMAC_REG_MAR, 440 (int) dmamap->dm_segs[0].ds_addr 441 + offset); 442 bus_space_write_2(sc->sc_bst, chan->ch_bht, 443 DMAC_REG_MTCR, (int) size); 444 xf->dx_nextoff = offset; 445 xf->dx_nextsize = size; 446 } 447 #ifdef DMAC_ARRAYCHAIN 448 xf->dx_done = 1; 449 #endif 450 } else { 451 #ifdef DMAC_ARRAYCHAIN 452 c = dmac_program_arraychain(self, xf, offset, size); 453 bus_space_write_4(sc->sc_bst, chan->ch_bht, 454 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 455 bus_space_write_2(sc->sc_bst, chan->ch_bht, 456 DMAC_REG_BTCR, c); 457 #else 458 panic ("DMAC: unexpected use of arraychaining mode"); 459 #endif 460 } 461 462 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 463 464 /* START!! */ 465 DDUMPREGS (3, ("first start\n")); 466 #ifdef DMAC_DEBUG 467 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 468 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 469 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 470 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 471 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 472 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 473 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 474 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 475 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 476 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 477 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 478 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 479 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 480 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 481 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 482 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 483 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 484 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 485 #endif 486 #ifdef DMAC_ARRAYCHAIN 487 #if defined(M68040) || defined(M68060) 488 /* flush data cache for the map */ 489 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 490 dma_cachectl((caddr_t) xf->dx_array, 491 sizeof(struct dmac_sg_array) * c); 492 #endif 493 #endif 494 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 495 496 if (xf->dx_nextoff != ~0) { 497 bus_space_write_4(sc->sc_bst, chan->ch_bht, 498 DMAC_REG_BAR, xf->dx_nextoff); 499 bus_space_write_2(sc->sc_bst, chan->ch_bht, 500 DMAC_REG_BTCR, xf->dx_nextsize); 501 } 502 503 return 0; 504 } 505 506 #ifdef DMAC_ARRAYCHAIN 507 static int 508 dmac_program_arraychain(self, xf, offset, size) 509 struct device *self; 510 struct dmac_dma_xfer *xf; 511 u_int offset; 512 u_int size; 513 { 514 struct dmac_channel_stat *chan = xf->dx_channel; 515 int ch = chan->ch_channel; 516 struct x68k_bus_dmamap *map = xf->dx_dmamap; 517 int i, j; 518 519 /* XXX not yet!! */ 520 if (offset != 0 || size != map->dm_mapsize) 521 panic ("dmac_program_arraychain: unsupported offset/size"); 522 523 DPRINTF (3, ("dmac_program_arraychain\n")); 524 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 525 i++, j++) { 526 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 527 #ifdef DIAGNOSTIC 528 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 529 panic ("dmac_program_arraychain: wrong map: %ld", 530 map->dm_segs[j].ds_len); 531 #endif 532 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 533 } 534 xf->dx_done = j; 535 536 return i; 537 } 538 #endif 539 540 /* 541 * interrupt handlers. 542 */ 543 static int 544 dmac_done(arg) 545 void *arg; 546 { 547 struct dmac_channel_stat *chan = arg; 548 struct dmac_softc *sc = (void*) chan->ch_softc; 549 #ifdef DMAC_ARRAYCHAIN 550 struct dmac_dma_xfer *xf = &chan->ch_xfer; 551 struct x68k_bus_dmamap *map = xf->dx_dmamap; 552 int c; 553 #endif 554 555 DPRINTF (3, ("dmac_done\n")); 556 557 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 558 559 #ifdef DMAC_ARRAYCHAIN 560 if (xf->dx_done == map->dm_nsegs) { 561 xf->dx_done = 0; 562 #endif 563 /* Done */ 564 return (*chan->ch_normal) (chan->ch_normalarg); 565 #ifdef DMAC_ARRAYCHAIN 566 } 567 #endif 568 569 #ifdef DMAC_ARRAYCHAIN 570 /* Continue transfer */ 571 DPRINTF (3, ("reprograming\n")); 572 c = dmac_program_arraychain (&sc->sc_dev, xf, 0, map->dm_mapsize); 573 574 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 575 bus_space_write_4(sc->sc_bst, chan->ch_bht, 576 DMAC_REG_BAR, (int) chan->ch_map); 577 bus_space_write_4(sc->sc_bst, chan->ch_bht, 578 DMAC_REG_DAR, (int) xf->dx_device); 579 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 580 581 /* START!! */ 582 DDUMPREGS (3, ("restart\n")); 583 bus_space_write_1(sc->sc_bst, chan->ch_bht, 584 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 585 586 return 1; 587 #endif 588 } 589 590 static int 591 dmac_error(arg) 592 void *arg; 593 { 594 struct dmac_channel_stat *chan = arg; 595 struct dmac_softc *sc = (void*) chan->ch_softc; 596 597 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 598 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 599 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 600 DPRINTF(5, ("registers were:\n")); 601 #ifdef DMAC_DEBUG 602 if ((dmacdebug & 0x0f) > 5) { 603 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 604 "CCR=%02x, CPR=%02x, GCR=%02x\n", 605 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 606 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 607 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 608 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 609 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 610 ddar, dmar, dbar); 611 } 612 #endif 613 614 /* Clear the status bits */ 615 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 616 DDUMPREGS(3, ("dmac_error\n")); 617 618 #ifdef DMAC_ARRAYCHAIN 619 chan->ch_xfer.dx_done = 0; 620 #endif 621 622 return (*chan->ch_error) (chan->ch_errorarg); 623 } 624 625 int 626 dmac_abort_xfer(self, xf) 627 struct device *self; 628 struct dmac_dma_xfer *xf; 629 { 630 struct dmac_softc *sc = (void*) self; 631 struct dmac_channel_stat *chan = xf->dx_channel; 632 633 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 634 DMAC_CCR_INT | DMAC_CCR_HLT); 635 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 636 xf->dx_nextoff = xf->dx_nextsize = -1; 637 638 return 0; 639 } 640 641 #ifdef DMAC_DEBUG 642 static int 643 dmac_dump_regs(void) 644 { 645 struct dmac_channel_stat *chan = debugchan; 646 struct dmac_softc *sc; 647 648 if ((chan == 0) || (dmacdebug & 0xf0)) 649 return 0; 650 sc = (void*) chan->ch_softc; 651 652 printf ("DMAC channel %d registers\n", chan->ch_channel); 653 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 654 "CCR=%02x, CPR=%02x, GCR=%02x\n", 655 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 656 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 657 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 658 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 659 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 660 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 661 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 662 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 663 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 664 "MFCR=%02x, BFCR=%02x\n", 665 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 666 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 667 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 668 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 669 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 670 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 671 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 672 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 673 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 674 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 675 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 676 677 return 0; 678 } 679 #endif 680
Indexes created Wed Sep 24 05:09:52 GMT 2025