intio_dmac.c revision 1.17
1 /* $NetBSD: intio_dmac.c,v 1.17 2002/10/02 16:02:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include "opt_m680x0.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 #ifdef DMAC_ARRAYCHAIN 68 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*, 69 u_int, u_int)); 70 #endif 71 static int dmac_done __P((void*)); 72 static int dmac_error __P((void*)); 73 74 #ifdef DMAC_DEBUG 75 static int dmac_dump_regs __P((void)); 76 #endif 77 78 /* 79 * autoconf stuff 80 */ 81 static int dmac_match __P((struct device *, struct cfdata *, void *)); 82 static void dmac_attach __P((struct device *, struct device *, void *)); 83 84 CFATTACH_DECL(dmac, sizeof(struct dmac_softc), 85 dmac_match, dmac_attach, NULL, NULL); 86 87 static int 88 dmac_match(parent, cf, aux) 89 struct device *parent; 90 struct cfdata *cf; 91 void *aux; 92 { 93 struct intio_attach_args *ia = aux; 94 95 if (strcmp (ia->ia_name, "dmac") != 0) 96 return (0); 97 if (cf->cf_unit != 0) 98 return (0); 99 100 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 101 ia->ia_addr = DMAC_ADDR; 102 103 /* fixed address */ 104 if (ia->ia_addr != DMAC_ADDR) 105 return (0); 106 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 107 return (0); 108 109 return 1; 110 } 111 112 static void 113 dmac_attach(parent, self, aux) 114 struct device *parent, *self; 115 void *aux; 116 { 117 struct dmac_softc *sc = (struct dmac_softc *)self; 118 struct intio_attach_args *ia = aux; 119 int r; 120 121 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 122 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 123 #ifdef DIAGNOSTIC 124 if (r) 125 panic ("IO map for DMAC corruption??"); 126 #endif 127 128 ((struct intio_softc*) parent)->sc_dmac = self; 129 sc->sc_bst = ia->ia_bst; 130 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 131 dmac_init_channels(sc); 132 133 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 134 } 135 136 static void 137 dmac_init_channels(sc) 138 struct dmac_softc *sc; 139 { 140 int i; 141 142 DPRINTF (3, ("dmac_init_channels\n")); 143 for (i=0; i<DMAC_NCHAN; i++) { 144 sc->sc_channels[i].ch_channel = i; 145 sc->sc_channels[i].ch_name[0] = 0; 146 sc->sc_channels[i].ch_softc = &sc->sc_dev; 147 bus_space_subregion(sc->sc_bst, sc->sc_bht, 148 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 149 &sc->sc_channels[i].ch_bht); 150 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 151 /* reset the status register */ 152 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 153 DMAC_REG_CSR, 0xff); 154 } 155 156 return; 157 } 158 159 160 /* 161 * Channel initialization/deinitialization per user device. 162 */ 163 struct dmac_channel_stat * 164 dmac_alloc_channel(self, ch, name, 165 normalv, normal, normalarg, 166 errorv, error, errorarg) 167 struct device *self; 168 int ch; 169 char *name; 170 int normalv, errorv; 171 dmac_intr_handler_t normal, error; 172 void *normalarg, *errorarg; 173 { 174 struct intio_softc *intio = (void*) self; 175 struct dmac_softc *sc = (void*) intio->sc_dmac; 176 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 177 char intrname[16]; 178 #ifdef DMAC_ARRAYCHAIN 179 int r, dummy; 180 #endif 181 182 printf ("%s: allocating ch %d for %s.\n", 183 sc->sc_dev.dv_xname, ch, name); 184 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 185 #ifdef DIAGNOSTIC 186 if (ch < 0 || ch >= DMAC_NCHAN) 187 panic ("Invalid DMAC channel."); 188 if (chan->ch_name[0]) 189 panic ("DMAC: channel in use."); 190 if (strlen(name) > 8) 191 panic ("DMAC: wrong user name."); 192 #endif 193 194 #ifdef DMAC_ARRAYCHAIN 195 /* allocate the DMAC arraychaining map */ 196 r = bus_dmamem_alloc(intio->sc_dmat, 197 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 198 4, 0, &chan->ch_seg[0], 1, &dummy, 199 BUS_DMA_NOWAIT); 200 if (r) 201 panic ("DMAC: cannot alloc DMA safe memory"); 202 r = bus_dmamem_map(intio->sc_dmat, 203 &chan->ch_seg[0], 1, 204 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 205 (caddr_t*) &chan->ch_map, 206 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 207 if (r) 208 panic ("DMAC: cannot map DMA safe memory"); 209 #endif 210 211 /* fill the channel status structure by the default values. */ 212 strcpy(chan->ch_name, name); 213 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 214 DMAC_DCR_OPS_8BIT); 215 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 216 chan->ch_normalv = normalv; 217 chan->ch_errorv = errorv; 218 chan->ch_normal = normal; 219 chan->ch_error = error; 220 chan->ch_normalarg = normalarg; 221 chan->ch_errorarg = errorarg; 222 chan->ch_xfer.dx_dmamap = 0; 223 224 /* setup the device-specific registers */ 225 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 226 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 227 DMAC_REG_DCR, chan->ch_dcr); 228 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 229 230 /* 231 * X68k physical user space is a subset of the kernel space; 232 * the memory is always included in the physical user space, 233 * while the device is not. 234 */ 235 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 236 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 237 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 238 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 239 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 240 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 241 242 /* setup the interrupt handlers */ 243 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 244 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 245 246 strcpy(intrname, name); 247 strcat(intrname, "dma"); 248 intio_intr_establish (normalv, intrname, dmac_done, chan); 249 250 strcpy(intrname, name); 251 strcat(intrname, "dmaerr"); 252 intio_intr_establish (errorv, intrname, dmac_error, chan); 253 254 return chan; 255 } 256 257 int 258 dmac_free_channel(self, ch, channel) 259 struct device *self; 260 int ch; 261 void *channel; 262 { 263 struct intio_softc *intio = (void*) self; 264 struct dmac_softc *sc = (void*) intio->sc_dmac; 265 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 266 267 DPRINTF (3, ("dmac_free_channel, %d\n", ch)); 268 DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap)); 269 if (chan != channel) 270 return -1; 271 if (ch != chan->ch_channel) 272 return -1; 273 274 #ifdef DMAC_ARRAYCHAIN 275 bus_dmamem_unmap(intio->sc_dmat, (caddr_t) chan->ch_map, 276 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 277 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 278 #endif 279 chan->ch_name[0] = 0; 280 intio_intr_disestablish(chan->ch_normalv, channel); 281 intio_intr_disestablish(chan->ch_errorv, channel); 282 283 return 0; 284 } 285 286 /* 287 * Initialization / deinitialization per transfer. 288 */ 289 struct dmac_dma_xfer * 290 dmac_alloc_xfer (chan, dmat, dmamap) 291 struct dmac_channel_stat *chan; 292 bus_dma_tag_t dmat; 293 bus_dmamap_t dmamap; 294 { 295 struct dmac_dma_xfer *xf = &chan->ch_xfer; 296 297 DPRINTF (3, ("dmac_alloc_xfer\n")); 298 xf->dx_channel = chan; 299 xf->dx_dmamap = dmamap; 300 xf->dx_tag = dmat; 301 #ifdef DMAC_ARRAYCHAIN 302 xf->dx_array = chan->ch_map; 303 xf->dx_done = 0; 304 #endif 305 xf->dx_nextoff = xf->dx_nextsize = -1; 306 return xf; 307 } 308 309 int 310 dmac_load_xfer (self, xf) 311 struct device *self; 312 struct dmac_dma_xfer *xf; 313 { 314 struct dmac_softc *sc = (void*) self; 315 struct dmac_channel_stat *chan = xf->dx_channel; 316 317 DPRINTF (3, ("dmac_load_xfer\n")); 318 319 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 320 if (xf->dx_dmamap->dm_nsegs == 1) 321 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 322 else { 323 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 324 xf->dx_nextoff = ~0; 325 xf->dx_nextsize = ~0; 326 } 327 328 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 329 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 330 bus_space_write_1(sc->sc_bst, chan->ch_bht, 331 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 332 bus_space_write_4(sc->sc_bst, chan->ch_bht, 333 DMAC_REG_DAR, (int) xf->dx_device); 334 335 return 0; 336 } 337 338 struct dmac_dma_xfer * 339 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 340 struct dmac_channel_stat *chan; 341 bus_dma_tag_t dmat; 342 bus_dmamap_t dmamap; 343 int dir, scr; 344 void *dar; 345 { 346 struct dmac_dma_xfer *xf; 347 struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc; 348 349 xf = dmac_alloc_xfer(chan, dmat, dmamap); 350 351 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 352 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 353 xf->dx_device = dar; 354 355 dmac_load_xfer(&sc->sc_dev, xf); 356 357 return xf; 358 } 359 360 #ifdef DMAC_DEBUG 361 static struct dmac_channel_stat *debugchan = 0; 362 #endif 363 364 #ifdef DMAC_DEBUG 365 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 366 dnivr, deivr, ddfcr, dmfcr, dbfcr; 367 static u_int16_t dmtcr, dbtcr; 368 static u_int32_t ddar, dmar, dbar; 369 #endif 370 /* 371 * Do the actual transfer. 372 */ 373 int 374 dmac_start_xfer(self, xf) 375 struct device *self; 376 struct dmac_dma_xfer *xf; 377 { 378 return dmac_start_xfer_offset(self, xf, 0, 0); 379 } 380 381 int 382 dmac_start_xfer_offset(self, xf, offset, size) 383 struct device *self; 384 struct dmac_dma_xfer *xf; 385 u_int offset; 386 u_int size; 387 { 388 struct dmac_softc *sc = (void*) self; 389 struct dmac_channel_stat *chan = xf->dx_channel; 390 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 391 int go = DMAC_CCR_STR|DMAC_CCR_INT; 392 #ifdef DMAC_ARRAYCHAIN 393 int c; 394 #endif 395 396 DPRINTF (3, ("dmac_start_xfer\n")); 397 #ifdef DMAC_DEBUG 398 debugchan=chan; 399 #endif 400 401 if (size == 0) { 402 #ifdef DIAGNOSTIC 403 if (offset != 0) 404 panic ("dmac_start_xfer_offset: invalid offset %x", 405 offset); 406 #endif 407 size = dmamap->dm_mapsize; 408 } 409 410 #ifdef DMAC_ARRAYCHAIN 411 #ifdef DIAGNOSTIC 412 if (xf->dx_done) 413 panic("dmac_start_xfer: DMA transfer in progress"); 414 #endif 415 #endif 416 DPRINTF (3, ("First program:\n")); 417 #ifdef DIAGNOSTIC 418 if ((offset >= dmamap->dm_mapsize) || 419 (offset + size > dmamap->dm_mapsize)) 420 panic ("dmac_start_xfer_offset: invalid offset: " 421 "offset=%d, size=%d, mapsize=%ld", 422 offset, size, dmamap->dm_mapsize); 423 #endif 424 /* program DMAC in single block mode or array chainning mode */ 425 if (dmamap->dm_nsegs == 1) { 426 DPRINTF(3, ("single block mode\n")); 427 #ifdef DIAGNOSTIC 428 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 429 panic ("dmac_start_xfer_offset: dmamap curruption"); 430 #endif 431 if (offset == xf->dx_nextoff && 432 size == xf->dx_nextsize) { 433 /* Use continued operation */ 434 go |= DMAC_CCR_CNT; 435 xf->dx_nextoff += size; 436 } else { 437 bus_space_write_4(sc->sc_bst, chan->ch_bht, 438 DMAC_REG_MAR, 439 (int) dmamap->dm_segs[0].ds_addr 440 + offset); 441 bus_space_write_2(sc->sc_bst, chan->ch_bht, 442 DMAC_REG_MTCR, (int) size); 443 xf->dx_nextoff = offset; 444 xf->dx_nextsize = size; 445 } 446 #ifdef DMAC_ARRAYCHAIN 447 xf->dx_done = 1; 448 #endif 449 } else { 450 #ifdef DMAC_ARRAYCHAIN 451 c = dmac_program_arraychain(self, xf, offset, size); 452 bus_space_write_4(sc->sc_bst, chan->ch_bht, 453 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 454 bus_space_write_2(sc->sc_bst, chan->ch_bht, 455 DMAC_REG_BTCR, c); 456 #else 457 panic ("DMAC: unexpected use of arraychaining mode"); 458 #endif 459 } 460 461 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 462 463 /* START!! */ 464 DDUMPREGS (3, ("first start\n")); 465 #ifdef DMAC_DEBUG 466 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 467 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 468 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 469 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 470 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 471 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 472 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 473 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 474 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 475 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 476 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 477 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 478 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 479 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 480 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 481 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 482 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 483 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 484 #endif 485 #ifdef DMAC_ARRAYCHAIN 486 #if defined(M68040) || defined(M68060) 487 /* flush data cache for the map */ 488 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 489 dma_cachectl((caddr_t) xf->dx_array, 490 sizeof(struct dmac_sg_array) * c); 491 #endif 492 #endif 493 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 494 495 if (xf->dx_nextoff != ~0) { 496 bus_space_write_4(sc->sc_bst, chan->ch_bht, 497 DMAC_REG_BAR, xf->dx_nextoff); 498 bus_space_write_2(sc->sc_bst, chan->ch_bht, 499 DMAC_REG_BTCR, xf->dx_nextsize); 500 } 501 502 return 0; 503 } 504 505 #ifdef DMAC_ARRAYCHAIN 506 static int 507 dmac_program_arraychain(self, xf, offset, size) 508 struct device *self; 509 struct dmac_dma_xfer *xf; 510 u_int offset; 511 u_int size; 512 { 513 struct dmac_channel_stat *chan = xf->dx_channel; 514 int ch = chan->ch_channel; 515 struct x68k_bus_dmamap *map = xf->dx_dmamap; 516 int i, j; 517 518 /* XXX not yet!! */ 519 if (offset != 0 || size != map->dm_mapsize) 520 panic ("dmac_program_arraychain: unsupported offset/size"); 521 522 DPRINTF (3, ("dmac_program_arraychain\n")); 523 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 524 i++, j++) { 525 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 526 #ifdef DIAGNOSTIC 527 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 528 panic ("dmac_program_arraychain: wrong map: %ld", 529 map->dm_segs[j].ds_len); 530 #endif 531 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 532 } 533 xf->dx_done = j; 534 535 return i; 536 } 537 #endif 538 539 /* 540 * interrupt handlers. 541 */ 542 static int 543 dmac_done(arg) 544 void *arg; 545 { 546 struct dmac_channel_stat *chan = arg; 547 struct dmac_softc *sc = (void*) chan->ch_softc; 548 #ifdef DMAC_ARRAYCHAIN 549 struct dmac_dma_xfer *xf = &chan->ch_xfer; 550 struct x68k_bus_dmamap *map = xf->dx_dmamap; 551 int c; 552 #endif 553 554 DPRINTF (3, ("dmac_done\n")); 555 556 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 557 558 #ifdef DMAC_ARRAYCHAIN 559 if (xf->dx_done == map->dm_nsegs) { 560 xf->dx_done = 0; 561 #endif 562 /* Done */ 563 return (*chan->ch_normal) (chan->ch_normalarg); 564 #ifdef DMAC_ARRAYCHAIN 565 } 566 #endif 567 568 #ifdef DMAC_ARRAYCHAIN 569 /* Continue transfer */ 570 DPRINTF (3, ("reprograming\n")); 571 c = dmac_program_arraychain (&sc->sc_dev, xf, 0, map->dm_mapsize); 572 573 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 574 bus_space_write_4(sc->sc_bst, chan->ch_bht, 575 DMAC_REG_BAR, (int) chan->ch_map); 576 bus_space_write_4(sc->sc_bst, chan->ch_bht, 577 DMAC_REG_DAR, (int) xf->dx_device); 578 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 579 580 /* START!! */ 581 DDUMPREGS (3, ("restart\n")); 582 bus_space_write_1(sc->sc_bst, chan->ch_bht, 583 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 584 585 return 1; 586 #endif 587 } 588 589 static int 590 dmac_error(arg) 591 void *arg; 592 { 593 struct dmac_channel_stat *chan = arg; 594 struct dmac_softc *sc = (void*) chan->ch_softc; 595 596 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 597 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 598 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 599 DPRINTF(5, ("registers were:\n")); 600 #ifdef DMAC_DEBUG 601 if ((dmacdebug & 0x0f) > 5) { 602 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 603 "CCR=%02x, CPR=%02x, GCR=%02x\n", 604 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 605 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 606 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 607 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 608 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 609 ddar, dmar, dbar); 610 } 611 #endif 612 613 /* Clear the status bits */ 614 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 615 DDUMPREGS(3, ("dmac_error\n")); 616 617 #ifdef DMAC_ARRAYCHAIN 618 chan->ch_xfer.dx_done = 0; 619 #endif 620 621 return (*chan->ch_error) (chan->ch_errorarg); 622 } 623 624 int 625 dmac_abort_xfer(self, xf) 626 struct device *self; 627 struct dmac_dma_xfer *xf; 628 { 629 struct dmac_softc *sc = (void*) self; 630 struct dmac_channel_stat *chan = xf->dx_channel; 631 632 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 633 DMAC_CCR_INT | DMAC_CCR_HLT); 634 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 635 xf->dx_nextoff = xf->dx_nextsize = -1; 636 637 return 0; 638 } 639 640 #ifdef DMAC_DEBUG 641 static int 642 dmac_dump_regs(void) 643 { 644 struct dmac_channel_stat *chan = debugchan; 645 struct dmac_softc *sc; 646 647 if ((chan == 0) || (dmacdebug & 0xf0)) 648 return 0; 649 sc = (void*) chan->ch_softc; 650 651 printf ("DMAC channel %d registers\n", chan->ch_channel); 652 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 653 "CCR=%02x, CPR=%02x, GCR=%02x\n", 654 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 655 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 656 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 657 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 658 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 659 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 660 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 661 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 662 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 663 "MFCR=%02x, BFCR=%02x\n", 664 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 665 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 666 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 667 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 668 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 669 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 670 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 671 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 672 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 673 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 674 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 675 676 return 0; 677 } 678 #endif 679
Indexes created Fri Sep 26 08:10:20 GMT 2025