intio_dmac.c revision 1.2
1 /* $NetBSD: intio_dmac.c,v 1.2 1999/03/16 16:30:18 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/extent.h> 48 #include <vm/vm.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*)); 68 static int dmac_done __P((void*)); 69 static int dmac_error __P((void*)); 70 71 static int dmac_dump_regs __P((void)); 72 73 /* 74 * autoconf stuff 75 */ 76 static int dmac_match __P((struct device *, struct cfdata *, void *)); 77 static void dmac_attach __P((struct device *, struct device *, void *)); 78 79 struct cfattach dmac_ca = { 80 sizeof(struct dmac_softc), dmac_match, dmac_attach 81 }; 82 83 static int 84 dmac_match(parent, cf, aux) 85 struct device *parent; 86 struct cfdata *cf; 87 void *aux; 88 { 89 struct intio_attach_args *ia = aux; 90 91 if (strcmp (ia->ia_name, "dmac") != 0) 92 return (0); 93 if (cf->cf_unit != 0) 94 return (0); 95 96 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 97 ia->ia_addr = DMAC_ADDR; 98 99 /* fixed address */ 100 if (ia->ia_addr != DMAC_ADDR) 101 return (0); 102 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 103 return (0); 104 105 return 1; 106 } 107 108 static void 109 dmac_attach(parent, self, aux) 110 struct device *parent, *self; 111 void *aux; 112 { 113 struct dmac_softc *sc = (struct dmac_softc *)self; 114 struct intio_attach_args *ia = aux; 115 int r; 116 117 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 118 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 119 #ifdef DIAGNOSTIC 120 if (r) 121 panic ("IO map for DMAC corruption??"); 122 #endif 123 124 ((struct intio_softc*) parent)->sc_dmac = self; 125 sc->sc_bst = ia->ia_bst; 126 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 127 dmac_init_channels(sc); 128 129 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 130 } 131 132 #define DMAC_MAPSIZE 64 133 /* Allocate statically in order to make sure the DMAC can reach the maps. */ 134 static struct dmac_sg_array dmac_map[DMAC_NCHAN][DMAC_MAPSIZE]; 135 136 static void 137 dmac_init_channels(sc) 138 struct dmac_softc *sc; 139 { 140 int i; 141 pmap_t pmap = pmap_kernel(); 142 143 for (i=0; i<DMAC_NCHAN; i++) { 144 sc->sc_channels[i].ch_channel = i; 145 sc->sc_channels[i].ch_name[0] = 0; 146 sc->sc_channels[i].ch_softc = &sc->sc_dev; 147 sc->sc_channels[i].ch_map = 148 (void*) pmap_extract (pmap, (vaddr_t) &dmac_map[i]); 149 bus_space_subregion(sc->sc_bst, sc->sc_bht, 150 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 151 &sc->sc_channels[i].ch_bht); 152 } 153 154 return; 155 } 156 157 158 /* 159 * Channel initialization/deinitialization per user device. 160 */ 161 struct dmac_channel_stat * 162 dmac_alloc_channel(self, ch, name, 163 normalv, normal, normalarg, 164 errorv, error, errorarg) 165 struct device *self; 166 int ch; 167 char *name; 168 int normalv, errorv; 169 dmac_intr_handler_t normal, error; 170 void *normalarg, *errorarg; 171 { 172 struct intio_softc *intio = (void*) self; 173 struct dmac_softc *sc = (void*) intio->sc_dmac; 174 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 175 char intrname[16]; 176 177 #ifdef DIAGNOSTIC 178 if (ch < 0 || ch >= DMAC_NCHAN) 179 panic ("Invalid DMAC channel."); 180 if (chan->ch_name[0]) 181 panic ("DMAC: channel in use."); 182 if (strlen(name) > 8) 183 panic ("DMAC: wrong user name."); 184 #endif 185 186 /* fill the channel status structure. */ 187 strcpy(chan->ch_name, name); 188 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 189 DMAC_DCR_OPS_8BIT); 190 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_CHAIN_ARRAY | 191 DMAC_OCR_REQG_EXTERNAL); 192 chan->ch_normalv = normalv; 193 chan->ch_errorv = errorv; 194 chan->ch_normal = normal; 195 chan->ch_error = error; 196 chan->ch_normalarg = normalarg; 197 chan->ch_errorarg = errorarg; 198 chan->ch_xfer_in_progress = 0; 199 200 /* setup the device-specific registers */ 201 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 202 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 203 DMAC_REG_DCR, chan->ch_dcr); 204 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 205 206 /* 207 * X68k physical user space is a subset of the kernel space; 208 * the memory is always included in the physical user space, 209 * while the device is not. 210 */ 211 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 212 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 213 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 214 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 215 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 216 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 217 218 /* setup the interrupt handlers */ 219 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 220 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 221 222 strcpy(intrname, name); 223 strcat(intrname, "dma"); 224 intio_intr_establish (normalv, intrname, dmac_done, chan); 225 226 strcpy(intrname, name); 227 strcat(intrname, "dmaerr"); 228 intio_intr_establish (errorv, intrname, dmac_error, chan); 229 230 return chan; 231 } 232 233 int 234 dmac_free_channel(self, ch, channel) 235 struct device *self; 236 int ch; 237 void *channel; 238 { 239 struct dmac_softc *sc = (void*) self; 240 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 241 242 if (chan != channel) 243 return -1; 244 if (ch != chan->ch_channel) 245 return -1; 246 #if DIAGNOSTIC 247 if (chan->ch_xfer_in_progress) 248 panic ("dmac_free_channel: DMA transfer in progress"); 249 #endif 250 251 chan->ch_name[0] = 0; 252 intio_intr_disestablish(chan->ch_normalv, channel); 253 intio_intr_disestablish(chan->ch_errorv, channel); 254 255 return 0; 256 } 257 258 /* 259 * Initialization / deinitialization per transfer. 260 */ 261 struct dmac_dma_xfer * 262 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 263 struct dmac_channel_stat *chan; 264 bus_dma_tag_t dmat; 265 bus_dmamap_t dmamap; 266 int dir, scr; 267 void *dar; 268 { 269 struct dmac_dma_xfer *r = malloc (sizeof (struct dmac_dma_xfer), 270 M_DEVBUF, M_WAITOK); 271 272 r->dx_channel = chan; 273 r->dx_dmamap = dmamap; 274 r->dx_tag = dmat; 275 r->dx_ocr = dir & DMAC_OCR_DIR_MASK; 276 r->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 277 r->dx_device = dar; 278 r->dx_done = 0; 279 280 return r; 281 } 282 283 #ifdef DMAC_DEBUG 284 static struct dmac_channel_stat *debugchan = 0; 285 #endif 286 287 #ifdef DMAC_DEBUG 288 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 289 dnivr, deivr, ddfcr, dmfcr, dbfcr; 290 static u_int16_t dmtcr, dbtcr; 291 static u_int32_t ddar, dmar, dbar; 292 #endif 293 /* 294 * Do the actual transfer. 295 */ 296 int 297 dmac_start_xfer(self, xf) 298 struct device *self; 299 struct dmac_dma_xfer *xf; 300 { 301 struct dmac_softc *sc = (void*) self; 302 struct dmac_channel_stat *chan = xf->dx_channel; 303 int c; 304 305 306 #ifdef DMAC_DEBUG 307 debugchan=chan; 308 #endif 309 bus_space_write_1(sc->sc_bst, chan->ch_bht, 310 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 311 bus_space_write_1(sc->sc_bst, chan->ch_bht, 312 DMAC_REG_SCR, xf->dx_scr); 313 314 /* program DMAC in array chainning mode */ 315 xf->dx_done = 0; 316 DPRINTF (3, ("First program:\n")); 317 c = dmac_program_arraychain(self, xf); 318 319 /* setup the address/count registers */ 320 bus_space_write_4(sc->sc_bst, chan->ch_bht, 321 DMAC_REG_BAR, (int) chan->ch_map); 322 bus_space_write_4(sc->sc_bst, chan->ch_bht, 323 DMAC_REG_DAR, (int) xf->dx_device); 324 bus_space_write_1(sc->sc_bst, chan->ch_bht, 325 DMAC_REG_CSR, 0xff); 326 bus_space_write_2(sc->sc_bst, chan->ch_bht, 327 DMAC_REG_BTCR, c); 328 329 /* START!! */ 330 DDUMPREGS (3, ("first start\n")); 331 #ifdef DMAC_DEBUG 332 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 333 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 334 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 335 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 336 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 337 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 338 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 339 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 340 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 341 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 342 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 343 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 344 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 345 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 346 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 347 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 348 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 349 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 350 #endif 351 #if defined(M68040) || defined(M68060) 352 if (mmutype == MMU_68040) 353 dma_cachectl((caddr_t) &dmac_map[chan->ch_channel], 354 sizeof(struct dmac_sg_array)*DMAC_MAPSIZE); 355 #endif 356 bus_space_write_1(sc->sc_bst, chan->ch_bht, 357 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 358 chan->ch_xfer_in_progress = xf; 359 360 return 0; 361 } 362 363 static int 364 dmac_program_arraychain(self, xf) 365 struct device *self; 366 struct dmac_dma_xfer *xf; 367 { 368 struct dmac_softc *sc = (void*) self; 369 struct dmac_channel_stat *chan = xf->dx_channel; 370 int ch = chan->ch_channel; 371 struct x68k_bus_dmamap *map = xf->dx_dmamap; 372 int i, j; 373 374 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 375 i++, j++) { 376 dmac_map[ch][i].da_addr = map->dm_segs[j].ds_addr; 377 #ifdef DIAGNOSTIC 378 if (map->dm_segs[j].ds_len > 0xff00) 379 panic ("dmac_program_arraychain: wrong map: %d", map->dm_segs[j].ds_len); 380 #endif 381 dmac_map[ch][i].da_count = map->dm_segs[j].ds_len; 382 } 383 xf->dx_done = j; 384 385 return i; 386 } 387 388 /* 389 * interrupt handlers. 390 */ 391 static int 392 dmac_done(arg) 393 void *arg; 394 { 395 struct dmac_channel_stat *chan = arg; 396 struct dmac_softc *sc = (void*) chan->ch_softc; 397 struct dmac_dma_xfer *xf = chan->ch_xfer_in_progress; 398 struct x68k_bus_dmamap *map = xf->dx_dmamap; 399 int c; 400 401 DPRINTF (3, ("dmac_done\n")); 402 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 403 404 if (xf->dx_done == map->dm_nsegs) { 405 /* Done */ 406 chan->ch_xfer_in_progress = 0; 407 return (*chan->ch_normal) (chan->ch_normalarg); 408 } 409 410 /* Continue transfer */ 411 DPRINTF (3, ("reprograming\n")); 412 c = dmac_program_arraychain (&sc->sc_dev, xf); 413 414 bus_space_write_4(sc->sc_bst, chan->ch_bht, 415 DMAC_REG_BAR, (int) chan->ch_map); 416 bus_space_write_4(sc->sc_bst, chan->ch_bht, 417 DMAC_REG_DAR, (int) xf->dx_device); 418 bus_space_write_1(sc->sc_bst, chan->ch_bht, 419 DMAC_REG_CSR, 0xff); 420 bus_space_write_2(sc->sc_bst, chan->ch_bht, 421 DMAC_REG_BTCR, c); 422 423 /* START!! */ 424 DDUMPREGS (3, ("restart\n")); 425 bus_space_write_1(sc->sc_bst, chan->ch_bht, 426 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 427 428 return 1; 429 } 430 431 static int 432 dmac_error(arg) 433 void *arg; 434 { 435 struct dmac_channel_stat *chan = arg; 436 struct dmac_softc *sc = (void*) chan->ch_softc; 437 438 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 439 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 440 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 441 DPRINTF(5, ("registers were:\n")); 442 #ifdef DMAC_DEBUG 443 if ((dmacdebug & 0x0f) > 5) { 444 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 445 "CCR=%02x, CPR=%02x, GCR=%02x\n", 446 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 447 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 448 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 449 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 450 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 451 ddar, dmar, dbar); 452 } 453 #endif 454 455 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 456 DDUMPREGS(3, ("dmac_error\n")); 457 458 return (*chan->ch_error) (chan->ch_errorarg); 459 } 460 461 462 #ifdef DMAC_DEBUG 463 static int 464 dmac_dump_regs(void) 465 { 466 struct dmac_channel_stat *chan = debugchan; 467 struct dmac_softc *sc; 468 469 if ((chan == 0) || (dmacdebug & 0xf0)) return; 470 sc = (void*) chan->ch_softc; 471 472 printf ("DMAC channel %d registers\n", chan->ch_channel); 473 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 474 "CCR=%02x, CPR=%02x, GCR=%02x\n", 475 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 476 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 477 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 478 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 479 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 480 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 481 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 482 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 483 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 484 "MFCR=%02x, BFCR=%02x\n", 485 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 486 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 487 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 488 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 489 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 490 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 491 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 492 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 493 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 494 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 495 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 496 497 return 0; 498 } 499 #endif 500
Indexes created Tue Sep 23 23:09:58 GMT 2025