intio_dmac.c revision 1.26
1 /* $NetBSD: intio_dmac.c,v 1.26 2007/05/12 06:31:18 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.26 2007/05/12 06:31:18 isaki Exp $"); 45 46 #include "opt_m680x0.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/bus.h> 54 #include <machine/cpu.h> 55 #include <machine/frame.h> 56 57 #include <arch/x68k/dev/intiovar.h> 58 #include <arch/x68k/dev/dmacvar.h> 59 60 #ifdef DMAC_DEBUG 61 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 62 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 63 int dmacdebug = 0; 64 #else 65 #define DPRINTF(n,x) 66 #define DDUMPREGS(n,x) 67 #endif 68 69 static void dmac_init_channels(struct dmac_softc *); 70 #ifdef DMAC_ARRAYCHAIN 71 static int dmac_program_arraychain(struct device *, struct dmac_dma_xfer *, 72 u_int, u_int); 73 #endif 74 static int dmac_done(void *); 75 static int dmac_error(void *); 76 77 #ifdef DMAC_DEBUG 78 static int dmac_dump_regs(void); 79 #endif 80 81 /* 82 * autoconf stuff 83 */ 84 static int dmac_match(struct device *, struct cfdata *, void *); 85 static void dmac_attach(struct device *, struct device *, void *); 86 87 CFATTACH_DECL(dmac, sizeof(struct dmac_softc), 88 dmac_match, dmac_attach, NULL, NULL); 89 90 static int dmac_attached; 91 92 static int 93 dmac_match(struct device *parent, struct cfdata *cf, void *aux) 94 { 95 struct intio_attach_args *ia = aux; 96 97 if (strcmp(ia->ia_name, "dmac") != 0) 98 return (0); 99 if (dmac_attached) 100 return (0); 101 102 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 103 ia->ia_addr = DMAC_ADDR; 104 105 /* fixed address */ 106 if (ia->ia_addr != DMAC_ADDR) 107 return (0); 108 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 109 return (0); 110 111 return 1; 112 } 113 114 static void 115 dmac_attach(struct device *parent, struct device *self, void *aux) 116 { 117 struct dmac_softc *sc = (struct dmac_softc *)self; 118 struct intio_attach_args *ia = aux; 119 int r; 120 121 dmac_attached = 1; 122 123 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 124 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE); 125 #ifdef DIAGNOSTIC 126 if (r) 127 panic("IO map for DMAC corruption??"); 128 #endif 129 130 ((struct intio_softc*) parent)->sc_dmac = self; 131 sc->sc_bst = ia->ia_bst; 132 bus_space_map(sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 133 dmac_init_channels(sc); 134 135 printf(": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 136 } 137 138 static void 139 dmac_init_channels(struct dmac_softc *sc) 140 { 141 int i; 142 143 DPRINTF(3, ("dmac_init_channels\n")); 144 for (i=0; i<DMAC_NCHAN; i++) { 145 sc->sc_channels[i].ch_channel = i; 146 sc->sc_channels[i].ch_name[0] = 0; 147 sc->sc_channels[i].ch_softc = &sc->sc_dev; 148 bus_space_subregion(sc->sc_bst, sc->sc_bht, 149 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 150 &sc->sc_channels[i].ch_bht); 151 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 152 /* reset the status register */ 153 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 154 DMAC_REG_CSR, 0xff); 155 } 156 157 return; 158 } 159 160 161 /* 162 * Channel initialization/deinitialization per user device. 163 */ 164 struct dmac_channel_stat * 165 dmac_alloc_channel(struct device *self, int ch, const char *name, int normalv, 166 dmac_intr_handler_t normal, void *normalarg, int errorv, 167 dmac_intr_handler_t error, void *errorarg) 168 { 169 struct intio_softc *intio = (void *)self; 170 struct dmac_softc *sc = (void *)intio->sc_dmac; 171 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 172 char intrname[16]; 173 #ifdef DMAC_ARRAYCHAIN 174 int r, dummy; 175 #endif 176 177 printf("%s: allocating ch %d for %s.\n", 178 sc->sc_dev.dv_xname, ch, name); 179 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 180 #ifdef DIAGNOSTIC 181 if (ch < 0 || ch >= DMAC_NCHAN) 182 panic("Invalid DMAC channel."); 183 if (chan->ch_name[0]) 184 panic("DMAC: channel in use."); 185 if (strlen(name) > 8) 186 panic("DMAC: wrong user name."); 187 #endif 188 189 #ifdef DMAC_ARRAYCHAIN 190 /* allocate the DMAC arraychaining map */ 191 r = bus_dmamem_alloc(intio->sc_dmat, 192 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 193 4, 0, &chan->ch_seg[0], 1, &dummy, 194 BUS_DMA_NOWAIT); 195 if (r) 196 panic("DMAC: cannot alloc DMA safe memory"); 197 r = bus_dmamem_map(intio->sc_dmat, 198 &chan->ch_seg[0], 1, 199 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 200 (void **) &chan->ch_map, 201 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 202 if (r) 203 panic("DMAC: cannot map DMA safe memory"); 204 #endif 205 206 /* fill the channel status structure by the default values. */ 207 strcpy(chan->ch_name, name); 208 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 209 DMAC_DCR_OPS_8BIT); 210 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 211 chan->ch_normalv = normalv; 212 chan->ch_errorv = errorv; 213 chan->ch_normal = normal; 214 chan->ch_error = error; 215 chan->ch_normalarg = normalarg; 216 chan->ch_errorarg = errorarg; 217 chan->ch_xfer.dx_dmamap = 0; 218 219 /* setup the device-specific registers */ 220 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 221 bus_space_write_1(sc->sc_bst, chan->ch_bht, 222 DMAC_REG_DCR, chan->ch_dcr); 223 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 224 225 /* 226 * X68k physical user space is a subset of the kernel space; 227 * the memory is always included in the physical user space, 228 * while the device is not. 229 */ 230 bus_space_write_1(sc->sc_bst, chan->ch_bht, 231 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 232 bus_space_write_1(sc->sc_bst, chan->ch_bht, 233 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 234 bus_space_write_1(sc->sc_bst, chan->ch_bht, 235 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 236 237 /* setup the interrupt handlers */ 238 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 239 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 240 241 strcpy(intrname, name); 242 strcat(intrname, "dma"); 243 intio_intr_establish(normalv, intrname, dmac_done, chan); 244 245 strcpy(intrname, name); 246 strcat(intrname, "dmaerr"); 247 intio_intr_establish(errorv, intrname, dmac_error, chan); 248 249 return chan; 250 } 251 252 int 253 dmac_free_channel(struct device *self, int ch, void *channel) 254 { 255 struct intio_softc *intio = (void *)self; 256 struct dmac_softc *sc = (void *)intio->sc_dmac; 257 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 258 259 DPRINTF(3, ("dmac_free_channel, %d\n", ch)); 260 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 261 if (chan != channel) 262 return -1; 263 if (ch != chan->ch_channel) 264 return -1; 265 266 #ifdef DMAC_ARRAYCHAIN 267 bus_dmamem_unmap(intio->sc_dmat, (void *)chan->ch_map, 268 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 269 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 270 #endif 271 chan->ch_name[0] = 0; 272 intio_intr_disestablish(chan->ch_normalv, channel); 273 intio_intr_disestablish(chan->ch_errorv, channel); 274 275 return 0; 276 } 277 278 /* 279 * Initialization / deinitialization per transfer. 280 */ 281 struct dmac_dma_xfer * 282 dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 283 bus_dmamap_t dmamap) 284 { 285 struct dmac_dma_xfer *xf = &chan->ch_xfer; 286 287 DPRINTF(3, ("dmac_alloc_xfer\n")); 288 xf->dx_channel = chan; 289 xf->dx_dmamap = dmamap; 290 xf->dx_tag = dmat; 291 #ifdef DMAC_ARRAYCHAIN 292 xf->dx_array = chan->ch_map; 293 xf->dx_done = 0; 294 #endif 295 xf->dx_nextoff = xf->dx_nextsize = -1; 296 return xf; 297 } 298 299 int 300 dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf) 301 { 302 struct dmac_softc *sc = (void *)self; 303 struct dmac_channel_stat *chan = xf->dx_channel; 304 305 DPRINTF(3, ("dmac_load_xfer\n")); 306 307 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 308 if (xf->dx_dmamap->dm_nsegs == 1) 309 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 310 else { 311 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 312 xf->dx_nextoff = ~0; 313 xf->dx_nextsize = ~0; 314 } 315 316 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 317 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 318 bus_space_write_1(sc->sc_bst, chan->ch_bht, 319 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 320 bus_space_write_4(sc->sc_bst, chan->ch_bht, 321 DMAC_REG_DAR, (int) xf->dx_device); 322 323 return 0; 324 } 325 326 struct dmac_dma_xfer * 327 dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 328 bus_dmamap_t dmamap, int dir, int scr, void *dar) 329 { 330 struct dmac_dma_xfer *xf; 331 struct dmac_softc *sc = (struct dmac_softc *)chan->ch_softc; 332 333 xf = dmac_alloc_xfer(chan, dmat, dmamap); 334 335 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 336 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 337 xf->dx_device = dar; 338 339 dmac_load_xfer(&sc->sc_dev, xf); 340 341 return xf; 342 } 343 344 #ifdef DMAC_DEBUG 345 static struct dmac_channel_stat *debugchan = 0; 346 #endif 347 348 /* 349 * Do the actual transfer. 350 */ 351 int 352 dmac_start_xfer(struct device *self, struct dmac_dma_xfer *xf) 353 { 354 return dmac_start_xfer_offset(self, xf, 0, 0); 355 } 356 357 int 358 dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf, 359 u_int offset, u_int size) 360 { 361 struct dmac_softc *sc = (void *)self; 362 struct dmac_channel_stat *chan = xf->dx_channel; 363 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 364 int go = DMAC_CCR_STR|DMAC_CCR_INT; 365 #ifdef DMAC_ARRAYCHAIN 366 int c; 367 #endif 368 369 DPRINTF(3, ("dmac_start_xfer\n")); 370 #ifdef DMAC_DEBUG 371 debugchan=chan; 372 #endif 373 374 if (size == 0) { 375 #ifdef DIAGNOSTIC 376 if (offset != 0) 377 panic("dmac_start_xfer_offset: invalid offset %x", 378 offset); 379 #endif 380 size = dmamap->dm_mapsize; 381 } 382 383 #ifdef DMAC_ARRAYCHAIN 384 #ifdef DIAGNOSTIC 385 if (xf->dx_done) 386 panic("dmac_start_xfer: DMA transfer in progress"); 387 #endif 388 #endif 389 DPRINTF(3, ("First program:\n")); 390 #ifdef DIAGNOSTIC 391 if ((offset >= dmamap->dm_mapsize) || 392 (offset + size > dmamap->dm_mapsize)) 393 panic("dmac_start_xfer_offset: invalid offset: " 394 "offset=%d, size=%d, mapsize=%ld", 395 offset, size, dmamap->dm_mapsize); 396 #endif 397 /* program DMAC in single block mode or array chainning mode */ 398 if (dmamap->dm_nsegs == 1) { 399 DPRINTF(3, ("single block mode\n")); 400 #ifdef DIAGNOSTIC 401 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 402 panic("dmac_start_xfer_offset: dmamap curruption"); 403 #endif 404 if (offset == xf->dx_nextoff && 405 size == xf->dx_nextsize) { 406 /* Use continued operation */ 407 go |= DMAC_CCR_CNT; 408 xf->dx_nextoff += size; 409 } else { 410 bus_space_write_4(sc->sc_bst, chan->ch_bht, 411 DMAC_REG_MAR, 412 (int) dmamap->dm_segs[0].ds_addr 413 + offset); 414 bus_space_write_2(sc->sc_bst, chan->ch_bht, 415 DMAC_REG_MTCR, (int) size); 416 xf->dx_nextoff = offset; 417 xf->dx_nextsize = size; 418 } 419 #ifdef DMAC_ARRAYCHAIN 420 xf->dx_done = 1; 421 #endif 422 } else { 423 #ifdef DMAC_ARRAYCHAIN 424 c = dmac_program_arraychain(self, xf, offset, size); 425 bus_space_write_4(sc->sc_bst, chan->ch_bht, 426 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 427 bus_space_write_2(sc->sc_bst, chan->ch_bht, 428 DMAC_REG_BTCR, c); 429 #else 430 panic("DMAC: unexpected use of arraychaining mode"); 431 #endif 432 } 433 434 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 435 436 /* START!! */ 437 DDUMPREGS(3, ("first start\n")); 438 439 #ifdef DMAC_ARRAYCHAIN 440 #if defined(M68040) || defined(M68060) 441 /* flush data cache for the map */ 442 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 443 dma_cachectl((void *) xf->dx_array, 444 sizeof(struct dmac_sg_array) * c); 445 #endif 446 #endif 447 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 448 449 if (xf->dx_nextoff != ~0) { 450 bus_space_write_4(sc->sc_bst, chan->ch_bht, 451 DMAC_REG_BAR, xf->dx_nextoff); 452 bus_space_write_2(sc->sc_bst, chan->ch_bht, 453 DMAC_REG_BTCR, xf->dx_nextsize); 454 } 455 456 return 0; 457 } 458 459 #ifdef DMAC_ARRAYCHAIN 460 static int 461 dmac_program_arraychain(struct device *self, struct dmac_dma_xfer *xf, 462 u_int offset, u_int size) 463 { 464 struct dmac_channel_stat *chan = xf->dx_channel; 465 int ch = chan->ch_channel; 466 struct x68k_bus_dmamap *map = xf->dx_dmamap; 467 int i, j; 468 469 /* XXX not yet!! */ 470 if (offset != 0 || size != map->dm_mapsize) 471 panic("dmac_program_arraychain: unsupported offset/size"); 472 473 DPRINTF(3, ("dmac_program_arraychain\n")); 474 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 475 i++, j++) { 476 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 477 #ifdef DIAGNOSTIC 478 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 479 panic("dmac_program_arraychain: wrong map: %ld", 480 map->dm_segs[j].ds_len); 481 #endif 482 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 483 } 484 xf->dx_done = j; 485 486 return i; 487 } 488 #endif 489 490 /* 491 * interrupt handlers. 492 */ 493 static int 494 dmac_done(void *arg) 495 { 496 struct dmac_channel_stat *chan = arg; 497 struct dmac_softc *sc = (void *)chan->ch_softc; 498 #ifdef DMAC_ARRAYCHAIN 499 struct dmac_dma_xfer *xf = &chan->ch_xfer; 500 struct x68k_bus_dmamap *map = xf->dx_dmamap; 501 int c; 502 #endif 503 504 DPRINTF(3, ("dmac_done\n")); 505 506 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 507 508 #ifdef DMAC_ARRAYCHAIN 509 if (xf->dx_done == map->dm_nsegs) { 510 xf->dx_done = 0; 511 #endif 512 /* Done */ 513 return (*chan->ch_normal)(chan->ch_normalarg); 514 #ifdef DMAC_ARRAYCHAIN 515 } 516 #endif 517 518 #ifdef DMAC_ARRAYCHAIN 519 /* Continue transfer */ 520 DPRINTF(3, ("reprograming\n")); 521 c = dmac_program_arraychain(&sc->sc_dev, xf, 0, map->dm_mapsize); 522 523 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 524 bus_space_write_4(sc->sc_bst, chan->ch_bht, 525 DMAC_REG_BAR, (int) chan->ch_map); 526 bus_space_write_4(sc->sc_bst, chan->ch_bht, 527 DMAC_REG_DAR, (int) xf->dx_device); 528 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 529 530 /* START!! */ 531 DDUMPREGS(3, ("restart\n")); 532 bus_space_write_1(sc->sc_bst, chan->ch_bht, 533 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 534 535 return 1; 536 #endif 537 } 538 539 static int 540 dmac_error(void *arg) 541 { 542 struct dmac_channel_stat *chan = arg; 543 struct dmac_softc *sc = (void *)chan->ch_softc; 544 545 printf("DMAC transfer error CSR=%02x, CER=%02x\n", 546 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 547 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 548 DDUMPREGS(3, ("registers were:\n")); 549 550 /* Clear the status bits */ 551 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 552 553 #ifdef DMAC_ARRAYCHAIN 554 chan->ch_xfer.dx_done = 0; 555 #endif 556 557 return (*chan->ch_error)(chan->ch_errorarg); 558 } 559 560 int 561 dmac_abort_xfer(struct device *self, struct dmac_dma_xfer *xf) 562 { 563 struct dmac_softc *sc = (void *)self; 564 struct dmac_channel_stat *chan = xf->dx_channel; 565 566 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 567 DMAC_CCR_INT | DMAC_CCR_HLT); 568 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 569 xf->dx_nextoff = xf->dx_nextsize = -1; 570 571 return 0; 572 } 573 574 #ifdef DMAC_DEBUG 575 static int 576 dmac_dump_regs(void) 577 { 578 struct dmac_channel_stat *chan = debugchan; 579 struct dmac_softc *sc; 580 581 if ((chan == 0) || (dmacdebug & 0xf0)) 582 return 0; 583 sc = (void *)chan->ch_softc; 584 585 printf("DMAC channel %d registers\n", chan->ch_channel); 586 printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 587 "CCR=%02x, CPR=%02x, GCR=%02x\n", 588 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 589 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 590 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 591 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 592 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 593 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 594 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 595 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 596 printf("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x, " 597 "MFCR=%02x, BFCR=%02x\n", 598 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 599 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 600 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 601 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 602 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 603 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 604 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 605 printf("DAR=%08x, MAR=%08x, BAR=%08x\n", 606 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 607 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 608 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 609 610 return 0; 611 } 612 #endif 613
Indexes created Fri Sep 26 20:09:58 GMT 2025