intio_dmac.c revision 1.28
1 /* $NetBSD: intio_dmac.c,v 1.28 2008/04/28 20:23:39 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.28 2008/04/28 20:23:39 martin Exp $"); 38 39 #include "opt_m680x0.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 #include <machine/frame.h> 49 50 #include <arch/x68k/dev/intiovar.h> 51 #include <arch/x68k/dev/dmacvar.h> 52 53 #ifdef DMAC_DEBUG 54 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 55 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 56 int dmacdebug = 0; 57 #else 58 #define DPRINTF(n,x) 59 #define DDUMPREGS(n,x) 60 #endif 61 62 static void dmac_init_channels(struct dmac_softc *); 63 #ifdef DMAC_ARRAYCHAIN 64 static int dmac_program_arraychain(struct device *, struct dmac_dma_xfer *, 65 u_int, u_int); 66 #endif 67 static int dmac_done(void *); 68 static int dmac_error(void *); 69 70 #ifdef DMAC_DEBUG 71 static int dmac_dump_regs(void); 72 #endif 73 74 /* 75 * autoconf stuff 76 */ 77 static int dmac_match(struct device *, struct cfdata *, void *); 78 static void dmac_attach(struct device *, struct device *, void *); 79 80 CFATTACH_DECL(dmac, sizeof(struct dmac_softc), 81 dmac_match, dmac_attach, NULL, NULL); 82 83 static int dmac_attached; 84 85 static int 86 dmac_match(struct device *parent, struct cfdata *cf, void *aux) 87 { 88 struct intio_attach_args *ia = aux; 89 90 if (strcmp(ia->ia_name, "dmac") != 0) 91 return (0); 92 if (dmac_attached) 93 return (0); 94 95 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 96 ia->ia_addr = DMAC_ADDR; 97 98 /* fixed address */ 99 if (ia->ia_addr != DMAC_ADDR) 100 return (0); 101 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 102 return (0); 103 104 return 1; 105 } 106 107 static void 108 dmac_attach(struct device *parent, struct device *self, void *aux) 109 { 110 struct dmac_softc *sc = (struct dmac_softc *)self; 111 struct intio_attach_args *ia = aux; 112 int r; 113 114 dmac_attached = 1; 115 116 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 117 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE); 118 #ifdef DIAGNOSTIC 119 if (r) 120 panic("IO map for DMAC corruption??"); 121 #endif 122 123 ((struct intio_softc*) parent)->sc_dmac = self; 124 sc->sc_bst = ia->ia_bst; 125 bus_space_map(sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 126 dmac_init_channels(sc); 127 128 printf(": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 129 } 130 131 static void 132 dmac_init_channels(struct dmac_softc *sc) 133 { 134 int i; 135 136 DPRINTF(3, ("dmac_init_channels\n")); 137 for (i=0; i<DMAC_NCHAN; i++) { 138 sc->sc_channels[i].ch_channel = i; 139 sc->sc_channels[i].ch_name[0] = 0; 140 sc->sc_channels[i].ch_softc = &sc->sc_dev; 141 bus_space_subregion(sc->sc_bst, sc->sc_bht, 142 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 143 &sc->sc_channels[i].ch_bht); 144 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 145 /* reset the status register */ 146 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 147 DMAC_REG_CSR, 0xff); 148 } 149 150 return; 151 } 152 153 154 /* 155 * Channel initialization/deinitialization per user device. 156 */ 157 struct dmac_channel_stat * 158 dmac_alloc_channel(struct device *self, int ch, const char *name, int normalv, 159 dmac_intr_handler_t normal, void *normalarg, int errorv, 160 dmac_intr_handler_t error, void *errorarg) 161 { 162 struct intio_softc *intio = (void *)self; 163 struct dmac_softc *sc = (void *)intio->sc_dmac; 164 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 165 char intrname[16]; 166 #ifdef DMAC_ARRAYCHAIN 167 int r, dummy; 168 #endif 169 170 printf("%s: allocating ch %d for %s.\n", 171 sc->sc_dev.dv_xname, ch, name); 172 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 173 #ifdef DIAGNOSTIC 174 if (ch < 0 || ch >= DMAC_NCHAN) 175 panic("Invalid DMAC channel."); 176 if (chan->ch_name[0]) 177 panic("DMAC: channel in use."); 178 if (strlen(name) > 8) 179 panic("DMAC: wrong user name."); 180 #endif 181 182 #ifdef DMAC_ARRAYCHAIN 183 /* allocate the DMAC arraychaining map */ 184 r = bus_dmamem_alloc(intio->sc_dmat, 185 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 186 4, 0, &chan->ch_seg[0], 1, &dummy, 187 BUS_DMA_NOWAIT); 188 if (r) 189 panic("DMAC: cannot alloc DMA safe memory"); 190 r = bus_dmamem_map(intio->sc_dmat, 191 &chan->ch_seg[0], 1, 192 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 193 (void **) &chan->ch_map, 194 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 195 if (r) 196 panic("DMAC: cannot map DMA safe memory"); 197 #endif 198 199 /* fill the channel status structure by the default values. */ 200 strcpy(chan->ch_name, name); 201 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 202 DMAC_DCR_OPS_8BIT); 203 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 204 chan->ch_normalv = normalv; 205 chan->ch_errorv = errorv; 206 chan->ch_normal = normal; 207 chan->ch_error = error; 208 chan->ch_normalarg = normalarg; 209 chan->ch_errorarg = errorarg; 210 chan->ch_xfer.dx_dmamap = 0; 211 212 /* setup the device-specific registers */ 213 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 214 bus_space_write_1(sc->sc_bst, chan->ch_bht, 215 DMAC_REG_DCR, chan->ch_dcr); 216 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 217 218 /* 219 * X68k physical user space is a subset of the kernel space; 220 * the memory is always included in the physical user space, 221 * while the device is not. 222 */ 223 bus_space_write_1(sc->sc_bst, chan->ch_bht, 224 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 225 bus_space_write_1(sc->sc_bst, chan->ch_bht, 226 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 227 bus_space_write_1(sc->sc_bst, chan->ch_bht, 228 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 229 230 /* setup the interrupt handlers */ 231 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 232 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 233 234 strcpy(intrname, name); 235 strcat(intrname, "dma"); 236 intio_intr_establish(normalv, intrname, dmac_done, chan); 237 238 strcpy(intrname, name); 239 strcat(intrname, "dmaerr"); 240 intio_intr_establish(errorv, intrname, dmac_error, chan); 241 242 return chan; 243 } 244 245 int 246 dmac_free_channel(struct device *self, int ch, void *channel) 247 { 248 struct intio_softc *intio = (void *)self; 249 struct dmac_softc *sc = (void *)intio->sc_dmac; 250 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 251 252 DPRINTF(3, ("dmac_free_channel, %d\n", ch)); 253 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 254 if (chan != channel) 255 return -1; 256 if (ch != chan->ch_channel) 257 return -1; 258 259 #ifdef DMAC_ARRAYCHAIN 260 bus_dmamem_unmap(intio->sc_dmat, (void *)chan->ch_map, 261 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 262 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 263 #endif 264 chan->ch_name[0] = 0; 265 intio_intr_disestablish(chan->ch_normalv, channel); 266 intio_intr_disestablish(chan->ch_errorv, channel); 267 268 return 0; 269 } 270 271 /* 272 * Initialization / deinitialization per transfer. 273 */ 274 struct dmac_dma_xfer * 275 dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 276 bus_dmamap_t dmamap) 277 { 278 struct dmac_dma_xfer *xf = &chan->ch_xfer; 279 280 DPRINTF(3, ("dmac_alloc_xfer\n")); 281 xf->dx_channel = chan; 282 xf->dx_dmamap = dmamap; 283 xf->dx_tag = dmat; 284 #ifdef DMAC_ARRAYCHAIN 285 xf->dx_array = chan->ch_map; 286 xf->dx_done = 0; 287 #endif 288 xf->dx_nextoff = xf->dx_nextsize = -1; 289 return xf; 290 } 291 292 int 293 dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf) 294 { 295 struct dmac_softc *sc = (void *)self; 296 struct dmac_channel_stat *chan = xf->dx_channel; 297 298 DPRINTF(3, ("dmac_load_xfer\n")); 299 300 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 301 if (xf->dx_dmamap->dm_nsegs == 1) 302 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 303 else { 304 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 305 xf->dx_nextoff = ~0; 306 xf->dx_nextsize = ~0; 307 } 308 309 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 310 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 311 bus_space_write_1(sc->sc_bst, chan->ch_bht, 312 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 313 bus_space_write_4(sc->sc_bst, chan->ch_bht, 314 DMAC_REG_DAR, (int) xf->dx_device); 315 316 return 0; 317 } 318 319 struct dmac_dma_xfer * 320 dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 321 bus_dmamap_t dmamap, int dir, int scr, void *dar) 322 { 323 struct dmac_dma_xfer *xf; 324 struct dmac_softc *sc = (struct dmac_softc *)chan->ch_softc; 325 326 xf = dmac_alloc_xfer(chan, dmat, dmamap); 327 328 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 329 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 330 xf->dx_device = dar; 331 332 dmac_load_xfer(&sc->sc_dev, xf); 333 334 return xf; 335 } 336 337 #ifdef DMAC_DEBUG 338 static struct dmac_channel_stat *debugchan = 0; 339 #endif 340 341 /* 342 * Do the actual transfer. 343 */ 344 int 345 dmac_start_xfer(struct device *self, struct dmac_dma_xfer *xf) 346 { 347 return dmac_start_xfer_offset(self, xf, 0, 0); 348 } 349 350 int 351 dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf, 352 u_int offset, u_int size) 353 { 354 struct dmac_softc *sc = (void *)self; 355 struct dmac_channel_stat *chan = xf->dx_channel; 356 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 357 int go = DMAC_CCR_STR|DMAC_CCR_INT; 358 #ifdef DMAC_ARRAYCHAIN 359 int c; 360 #endif 361 362 DPRINTF(3, ("dmac_start_xfer\n")); 363 #ifdef DMAC_DEBUG 364 debugchan=chan; 365 #endif 366 367 if (size == 0) { 368 #ifdef DIAGNOSTIC 369 if (offset != 0) 370 panic("dmac_start_xfer_offset: invalid offset %x", 371 offset); 372 #endif 373 size = dmamap->dm_mapsize; 374 } 375 376 #ifdef DMAC_ARRAYCHAIN 377 #ifdef DIAGNOSTIC 378 if (xf->dx_done) 379 panic("dmac_start_xfer: DMA transfer in progress"); 380 #endif 381 #endif 382 DPRINTF(3, ("First program:\n")); 383 #ifdef DIAGNOSTIC 384 if ((offset >= dmamap->dm_mapsize) || 385 (offset + size > dmamap->dm_mapsize)) 386 panic("dmac_start_xfer_offset: invalid offset: " 387 "offset=%d, size=%d, mapsize=%ld", 388 offset, size, dmamap->dm_mapsize); 389 #endif 390 /* program DMAC in single block mode or array chainning mode */ 391 if (dmamap->dm_nsegs == 1) { 392 DPRINTF(3, ("single block mode\n")); 393 #ifdef DIAGNOSTIC 394 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 395 panic("dmac_start_xfer_offset: dmamap curruption"); 396 #endif 397 if (offset == xf->dx_nextoff && 398 size == xf->dx_nextsize) { 399 /* Use continued operation */ 400 go |= DMAC_CCR_CNT; 401 xf->dx_nextoff += size; 402 } else { 403 bus_space_write_4(sc->sc_bst, chan->ch_bht, 404 DMAC_REG_MAR, 405 (int) dmamap->dm_segs[0].ds_addr 406 + offset); 407 bus_space_write_2(sc->sc_bst, chan->ch_bht, 408 DMAC_REG_MTCR, (int) size); 409 xf->dx_nextoff = offset; 410 xf->dx_nextsize = size; 411 } 412 #ifdef DMAC_ARRAYCHAIN 413 xf->dx_done = 1; 414 #endif 415 } else { 416 #ifdef DMAC_ARRAYCHAIN 417 c = dmac_program_arraychain(self, xf, offset, size); 418 bus_space_write_4(sc->sc_bst, chan->ch_bht, 419 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 420 bus_space_write_2(sc->sc_bst, chan->ch_bht, 421 DMAC_REG_BTCR, c); 422 #else 423 panic("DMAC: unexpected use of arraychaining mode"); 424 #endif 425 } 426 427 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 428 429 /* START!! */ 430 DDUMPREGS(3, ("first start\n")); 431 432 #ifdef DMAC_ARRAYCHAIN 433 #if defined(M68040) || defined(M68060) 434 /* flush data cache for the map */ 435 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 436 dma_cachectl((void *) xf->dx_array, 437 sizeof(struct dmac_sg_array) * c); 438 #endif 439 #endif 440 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 441 442 if (xf->dx_nextoff != ~0) { 443 bus_space_write_4(sc->sc_bst, chan->ch_bht, 444 DMAC_REG_BAR, xf->dx_nextoff); 445 bus_space_write_2(sc->sc_bst, chan->ch_bht, 446 DMAC_REG_BTCR, xf->dx_nextsize); 447 } 448 449 return 0; 450 } 451 452 #ifdef DMAC_ARRAYCHAIN 453 static int 454 dmac_program_arraychain(struct device *self, struct dmac_dma_xfer *xf, 455 u_int offset, u_int size) 456 { 457 struct dmac_channel_stat *chan = xf->dx_channel; 458 int ch = chan->ch_channel; 459 struct x68k_bus_dmamap *map = xf->dx_dmamap; 460 int i, j; 461 462 /* XXX not yet!! */ 463 if (offset != 0 || size != map->dm_mapsize) 464 panic("dmac_program_arraychain: unsupported offset/size"); 465 466 DPRINTF(3, ("dmac_program_arraychain\n")); 467 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 468 i++, j++) { 469 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 470 #ifdef DIAGNOSTIC 471 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 472 panic("dmac_program_arraychain: wrong map: %ld", 473 map->dm_segs[j].ds_len); 474 #endif 475 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 476 } 477 xf->dx_done = j; 478 479 return i; 480 } 481 #endif 482 483 /* 484 * interrupt handlers. 485 */ 486 static int 487 dmac_done(void *arg) 488 { 489 struct dmac_channel_stat *chan = arg; 490 struct dmac_softc *sc = (void *)chan->ch_softc; 491 #ifdef DMAC_ARRAYCHAIN 492 struct dmac_dma_xfer *xf = &chan->ch_xfer; 493 struct x68k_bus_dmamap *map = xf->dx_dmamap; 494 int c; 495 #endif 496 497 DPRINTF(3, ("dmac_done\n")); 498 499 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 500 501 #ifdef DMAC_ARRAYCHAIN 502 if (xf->dx_done == map->dm_nsegs) { 503 xf->dx_done = 0; 504 #endif 505 /* Done */ 506 return (*chan->ch_normal)(chan->ch_normalarg); 507 #ifdef DMAC_ARRAYCHAIN 508 } 509 #endif 510 511 #ifdef DMAC_ARRAYCHAIN 512 /* Continue transfer */ 513 DPRINTF(3, ("reprograming\n")); 514 c = dmac_program_arraychain(&sc->sc_dev, xf, 0, map->dm_mapsize); 515 516 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 517 bus_space_write_4(sc->sc_bst, chan->ch_bht, 518 DMAC_REG_BAR, (int) chan->ch_map); 519 bus_space_write_4(sc->sc_bst, chan->ch_bht, 520 DMAC_REG_DAR, (int) xf->dx_device); 521 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 522 523 /* START!! */ 524 DDUMPREGS(3, ("restart\n")); 525 bus_space_write_1(sc->sc_bst, chan->ch_bht, 526 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 527 528 return 1; 529 #endif 530 } 531 532 static int 533 dmac_error(void *arg) 534 { 535 struct dmac_channel_stat *chan = arg; 536 struct dmac_softc *sc = (void *)chan->ch_softc; 537 538 printf("DMAC transfer error CSR=%02x, CER=%02x\n", 539 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 540 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 541 DDUMPREGS(3, ("registers were:\n")); 542 543 /* Clear the status bits */ 544 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 545 546 #ifdef DMAC_ARRAYCHAIN 547 chan->ch_xfer.dx_done = 0; 548 #endif 549 550 return (*chan->ch_error)(chan->ch_errorarg); 551 } 552 553 int 554 dmac_abort_xfer(struct device *self, struct dmac_dma_xfer *xf) 555 { 556 struct dmac_softc *sc = (void *)self; 557 struct dmac_channel_stat *chan = xf->dx_channel; 558 559 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 560 DMAC_CCR_INT | DMAC_CCR_HLT); 561 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 562 xf->dx_nextoff = xf->dx_nextsize = -1; 563 564 return 0; 565 } 566 567 #ifdef DMAC_DEBUG 568 static int 569 dmac_dump_regs(void) 570 { 571 struct dmac_channel_stat *chan = debugchan; 572 struct dmac_softc *sc; 573 574 if ((chan == 0) || (dmacdebug & 0xf0)) 575 return 0; 576 sc = (void *)chan->ch_softc; 577 578 printf("DMAC channel %d registers\n", chan->ch_channel); 579 printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 580 "CCR=%02x, CPR=%02x, GCR=%02x\n", 581 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 582 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 583 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 584 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 585 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 586 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 587 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 588 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 589 printf("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x, " 590 "MFCR=%02x, BFCR=%02x\n", 591 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 592 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 593 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 594 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 595 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 596 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 597 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 598 printf("DAR=%08x, MAR=%08x, BAR=%08x\n", 599 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 600 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 601 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 602 603 return 0; 604 } 605 #endif 606
Indexes created Thu Oct 02 14:10:14 GMT 2025