intio_dmac.c revision 1.29
1 /* $NetBSD: intio_dmac.c,v 1.29 2008/06/23 08:33:38 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.29 2008/06/23 08:33:38 isaki Exp $"); 38 39 #include "opt_m680x0.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 #include <machine/frame.h> 49 50 #include <arch/x68k/dev/intiovar.h> 51 #include <arch/x68k/dev/dmacvar.h> 52 53 #ifdef DMAC_DEBUG 54 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 55 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 56 int dmacdebug = 0; 57 #else 58 #define DPRINTF(n,x) 59 #define DDUMPREGS(n,x) 60 #endif 61 62 static void dmac_init_channels(struct dmac_softc *); 63 #ifdef DMAC_ARRAYCHAIN 64 static int dmac_program_arraychain(struct device *, struct dmac_dma_xfer *, 65 u_int, u_int); 66 #endif 67 static int dmac_done(void *); 68 static int dmac_error(void *); 69 70 #ifdef DMAC_DEBUG 71 static int dmac_dump_regs(void); 72 #endif 73 74 /* 75 * autoconf stuff 76 */ 77 static int dmac_match(struct device *, struct cfdata *, void *); 78 static void dmac_attach(struct device *, struct device *, void *); 79 80 CFATTACH_DECL(dmac, sizeof(struct dmac_softc), 81 dmac_match, dmac_attach, NULL, NULL); 82 83 static int dmac_attached; 84 85 static int 86 dmac_match(struct device *parent, struct cfdata *cf, void *aux) 87 { 88 struct intio_attach_args *ia = aux; 89 90 if (strcmp(ia->ia_name, "dmac") != 0) 91 return (0); 92 if (dmac_attached) 93 return (0); 94 95 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 96 ia->ia_addr = DMAC_ADDR; 97 98 /* fixed address */ 99 if (ia->ia_addr != DMAC_ADDR) 100 return (0); 101 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 102 return (0); 103 104 return 1; 105 } 106 107 static void 108 dmac_attach(struct device *parent, struct device *self, void *aux) 109 { 110 struct dmac_softc *sc = (struct dmac_softc *)self; 111 struct intio_attach_args *ia = aux; 112 int r; 113 114 dmac_attached = 1; 115 116 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 117 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE); 118 #ifdef DIAGNOSTIC 119 if (r) 120 panic("IO map for DMAC corruption??"); 121 #endif 122 123 ((struct intio_softc*) parent)->sc_dmac = self; 124 sc->sc_bst = ia->ia_bst; 125 bus_space_map(sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 126 dmac_init_channels(sc); 127 128 printf(": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 129 } 130 131 static void 132 dmac_init_channels(struct dmac_softc *sc) 133 { 134 int i; 135 136 DPRINTF(3, ("dmac_init_channels\n")); 137 for (i=0; i<DMAC_NCHAN; i++) { 138 sc->sc_channels[i].ch_channel = i; 139 sc->sc_channels[i].ch_name[0] = 0; 140 sc->sc_channels[i].ch_softc = &sc->sc_dev; 141 bus_space_subregion(sc->sc_bst, sc->sc_bht, 142 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 143 &sc->sc_channels[i].ch_bht); 144 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 145 /* reset the status register */ 146 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 147 DMAC_REG_CSR, 0xff); 148 } 149 150 return; 151 } 152 153 154 /* 155 * Channel initialization/deinitialization per user device. 156 */ 157 struct dmac_channel_stat * 158 dmac_alloc_channel(struct device *self, int ch, const char *name, int normalv, 159 dmac_intr_handler_t normal, void *normalarg, int errorv, 160 dmac_intr_handler_t error, void *errorarg) 161 { 162 struct intio_softc *intio = (void *)self; 163 struct dmac_softc *sc = (void *)intio->sc_dmac; 164 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 165 #ifdef DMAC_ARRAYCHAIN 166 int r, dummy; 167 #endif 168 169 printf("%s: allocating ch %d for %s.\n", 170 sc->sc_dev.dv_xname, ch, name); 171 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 172 #ifdef DIAGNOSTIC 173 if (ch < 0 || ch >= DMAC_NCHAN) 174 panic("Invalid DMAC channel."); 175 if (chan->ch_name[0]) 176 panic("DMAC: channel in use."); 177 if (strlen(name) > 8) 178 panic("DMAC: wrong user name."); 179 #endif 180 181 #ifdef DMAC_ARRAYCHAIN 182 /* allocate the DMAC arraychaining map */ 183 r = bus_dmamem_alloc(intio->sc_dmat, 184 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 185 4, 0, &chan->ch_seg[0], 1, &dummy, 186 BUS_DMA_NOWAIT); 187 if (r) 188 panic("DMAC: cannot alloc DMA safe memory"); 189 r = bus_dmamem_map(intio->sc_dmat, 190 &chan->ch_seg[0], 1, 191 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 192 (void **) &chan->ch_map, 193 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 194 if (r) 195 panic("DMAC: cannot map DMA safe memory"); 196 #endif 197 198 /* fill the channel status structure by the default values. */ 199 strcpy(chan->ch_name, name); 200 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 201 DMAC_DCR_OPS_8BIT); 202 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 203 chan->ch_normalv = normalv; 204 chan->ch_errorv = errorv; 205 chan->ch_normal = normal; 206 chan->ch_error = error; 207 chan->ch_normalarg = normalarg; 208 chan->ch_errorarg = errorarg; 209 chan->ch_xfer.dx_dmamap = 0; 210 211 /* setup the device-specific registers */ 212 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 213 bus_space_write_1(sc->sc_bst, chan->ch_bht, 214 DMAC_REG_DCR, chan->ch_dcr); 215 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 216 217 /* 218 * X68k physical user space is a subset of the kernel space; 219 * the memory is always included in the physical user space, 220 * while the device is not. 221 */ 222 bus_space_write_1(sc->sc_bst, chan->ch_bht, 223 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 224 bus_space_write_1(sc->sc_bst, chan->ch_bht, 225 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 226 bus_space_write_1(sc->sc_bst, chan->ch_bht, 227 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 228 229 /* setup the interrupt handlers */ 230 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 231 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 232 233 intio_intr_establish_ext(normalv, name, "dma", dmac_done, chan); 234 intio_intr_establish_ext(errorv, name, "dmaerr", dmac_error, chan); 235 236 return chan; 237 } 238 239 int 240 dmac_free_channel(struct device *self, int ch, void *channel) 241 { 242 struct intio_softc *intio = (void *)self; 243 struct dmac_softc *sc = (void *)intio->sc_dmac; 244 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 245 246 DPRINTF(3, ("dmac_free_channel, %d\n", ch)); 247 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 248 if (chan != channel) 249 return -1; 250 if (ch != chan->ch_channel) 251 return -1; 252 253 #ifdef DMAC_ARRAYCHAIN 254 bus_dmamem_unmap(intio->sc_dmat, (void *)chan->ch_map, 255 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 256 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 257 #endif 258 chan->ch_name[0] = 0; 259 intio_intr_disestablish(chan->ch_normalv, channel); 260 intio_intr_disestablish(chan->ch_errorv, channel); 261 262 return 0; 263 } 264 265 /* 266 * Initialization / deinitialization per transfer. 267 */ 268 struct dmac_dma_xfer * 269 dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 270 bus_dmamap_t dmamap) 271 { 272 struct dmac_dma_xfer *xf = &chan->ch_xfer; 273 274 DPRINTF(3, ("dmac_alloc_xfer\n")); 275 xf->dx_channel = chan; 276 xf->dx_dmamap = dmamap; 277 xf->dx_tag = dmat; 278 #ifdef DMAC_ARRAYCHAIN 279 xf->dx_array = chan->ch_map; 280 xf->dx_done = 0; 281 #endif 282 xf->dx_nextoff = xf->dx_nextsize = -1; 283 return xf; 284 } 285 286 int 287 dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf) 288 { 289 struct dmac_softc *sc = (void *)self; 290 struct dmac_channel_stat *chan = xf->dx_channel; 291 292 DPRINTF(3, ("dmac_load_xfer\n")); 293 294 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 295 if (xf->dx_dmamap->dm_nsegs == 1) 296 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 297 else { 298 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 299 xf->dx_nextoff = ~0; 300 xf->dx_nextsize = ~0; 301 } 302 303 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 304 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 305 bus_space_write_1(sc->sc_bst, chan->ch_bht, 306 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 307 bus_space_write_4(sc->sc_bst, chan->ch_bht, 308 DMAC_REG_DAR, (int) xf->dx_device); 309 310 return 0; 311 } 312 313 struct dmac_dma_xfer * 314 dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 315 bus_dmamap_t dmamap, int dir, int scr, void *dar) 316 { 317 struct dmac_dma_xfer *xf; 318 struct dmac_softc *sc = (struct dmac_softc *)chan->ch_softc; 319 320 xf = dmac_alloc_xfer(chan, dmat, dmamap); 321 322 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 323 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 324 xf->dx_device = dar; 325 326 dmac_load_xfer(&sc->sc_dev, xf); 327 328 return xf; 329 } 330 331 #ifdef DMAC_DEBUG 332 static struct dmac_channel_stat *debugchan = 0; 333 #endif 334 335 /* 336 * Do the actual transfer. 337 */ 338 int 339 dmac_start_xfer(struct device *self, struct dmac_dma_xfer *xf) 340 { 341 return dmac_start_xfer_offset(self, xf, 0, 0); 342 } 343 344 int 345 dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf, 346 u_int offset, u_int size) 347 { 348 struct dmac_softc *sc = (void *)self; 349 struct dmac_channel_stat *chan = xf->dx_channel; 350 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 351 int go = DMAC_CCR_STR|DMAC_CCR_INT; 352 #ifdef DMAC_ARRAYCHAIN 353 int c; 354 #endif 355 356 DPRINTF(3, ("dmac_start_xfer\n")); 357 #ifdef DMAC_DEBUG 358 debugchan=chan; 359 #endif 360 361 if (size == 0) { 362 #ifdef DIAGNOSTIC 363 if (offset != 0) 364 panic("dmac_start_xfer_offset: invalid offset %x", 365 offset); 366 #endif 367 size = dmamap->dm_mapsize; 368 } 369 370 #ifdef DMAC_ARRAYCHAIN 371 #ifdef DIAGNOSTIC 372 if (xf->dx_done) 373 panic("dmac_start_xfer: DMA transfer in progress"); 374 #endif 375 #endif 376 DPRINTF(3, ("First program:\n")); 377 #ifdef DIAGNOSTIC 378 if ((offset >= dmamap->dm_mapsize) || 379 (offset + size > dmamap->dm_mapsize)) 380 panic("dmac_start_xfer_offset: invalid offset: " 381 "offset=%d, size=%d, mapsize=%ld", 382 offset, size, dmamap->dm_mapsize); 383 #endif 384 /* program DMAC in single block mode or array chainning mode */ 385 if (dmamap->dm_nsegs == 1) { 386 DPRINTF(3, ("single block mode\n")); 387 #ifdef DIAGNOSTIC 388 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 389 panic("dmac_start_xfer_offset: dmamap curruption"); 390 #endif 391 if (offset == xf->dx_nextoff && 392 size == xf->dx_nextsize) { 393 /* Use continued operation */ 394 go |= DMAC_CCR_CNT; 395 xf->dx_nextoff += size; 396 } else { 397 bus_space_write_4(sc->sc_bst, chan->ch_bht, 398 DMAC_REG_MAR, 399 (int) dmamap->dm_segs[0].ds_addr 400 + offset); 401 bus_space_write_2(sc->sc_bst, chan->ch_bht, 402 DMAC_REG_MTCR, (int) size); 403 xf->dx_nextoff = offset; 404 xf->dx_nextsize = size; 405 } 406 #ifdef DMAC_ARRAYCHAIN 407 xf->dx_done = 1; 408 #endif 409 } else { 410 #ifdef DMAC_ARRAYCHAIN 411 c = dmac_program_arraychain(self, xf, offset, size); 412 bus_space_write_4(sc->sc_bst, chan->ch_bht, 413 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 414 bus_space_write_2(sc->sc_bst, chan->ch_bht, 415 DMAC_REG_BTCR, c); 416 #else 417 panic("DMAC: unexpected use of arraychaining mode"); 418 #endif 419 } 420 421 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 422 423 /* START!! */ 424 DDUMPREGS(3, ("first start\n")); 425 426 #ifdef DMAC_ARRAYCHAIN 427 #if defined(M68040) || defined(M68060) 428 /* flush data cache for the map */ 429 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 430 dma_cachectl((void *) xf->dx_array, 431 sizeof(struct dmac_sg_array) * c); 432 #endif 433 #endif 434 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 435 436 if (xf->dx_nextoff != ~0) { 437 bus_space_write_4(sc->sc_bst, chan->ch_bht, 438 DMAC_REG_BAR, xf->dx_nextoff); 439 bus_space_write_2(sc->sc_bst, chan->ch_bht, 440 DMAC_REG_BTCR, xf->dx_nextsize); 441 } 442 443 return 0; 444 } 445 446 #ifdef DMAC_ARRAYCHAIN 447 static int 448 dmac_program_arraychain(struct device *self, struct dmac_dma_xfer *xf, 449 u_int offset, u_int size) 450 { 451 struct dmac_channel_stat *chan = xf->dx_channel; 452 int ch = chan->ch_channel; 453 struct x68k_bus_dmamap *map = xf->dx_dmamap; 454 int i, j; 455 456 /* XXX not yet!! */ 457 if (offset != 0 || size != map->dm_mapsize) 458 panic("dmac_program_arraychain: unsupported offset/size"); 459 460 DPRINTF(3, ("dmac_program_arraychain\n")); 461 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 462 i++, j++) { 463 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 464 #ifdef DIAGNOSTIC 465 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 466 panic("dmac_program_arraychain: wrong map: %ld", 467 map->dm_segs[j].ds_len); 468 #endif 469 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 470 } 471 xf->dx_done = j; 472 473 return i; 474 } 475 #endif 476 477 /* 478 * interrupt handlers. 479 */ 480 static int 481 dmac_done(void *arg) 482 { 483 struct dmac_channel_stat *chan = arg; 484 struct dmac_softc *sc = (void *)chan->ch_softc; 485 #ifdef DMAC_ARRAYCHAIN 486 struct dmac_dma_xfer *xf = &chan->ch_xfer; 487 struct x68k_bus_dmamap *map = xf->dx_dmamap; 488 int c; 489 #endif 490 491 DPRINTF(3, ("dmac_done\n")); 492 493 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 494 495 #ifdef DMAC_ARRAYCHAIN 496 if (xf->dx_done == map->dm_nsegs) { 497 xf->dx_done = 0; 498 #endif 499 /* Done */ 500 return (*chan->ch_normal)(chan->ch_normalarg); 501 #ifdef DMAC_ARRAYCHAIN 502 } 503 #endif 504 505 #ifdef DMAC_ARRAYCHAIN 506 /* Continue transfer */ 507 DPRINTF(3, ("reprograming\n")); 508 c = dmac_program_arraychain(&sc->sc_dev, xf, 0, map->dm_mapsize); 509 510 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 511 bus_space_write_4(sc->sc_bst, chan->ch_bht, 512 DMAC_REG_BAR, (int) chan->ch_map); 513 bus_space_write_4(sc->sc_bst, chan->ch_bht, 514 DMAC_REG_DAR, (int) xf->dx_device); 515 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 516 517 /* START!! */ 518 DDUMPREGS(3, ("restart\n")); 519 bus_space_write_1(sc->sc_bst, chan->ch_bht, 520 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 521 522 return 1; 523 #endif 524 } 525 526 static int 527 dmac_error(void *arg) 528 { 529 struct dmac_channel_stat *chan = arg; 530 struct dmac_softc *sc = (void *)chan->ch_softc; 531 532 printf("DMAC transfer error CSR=%02x, CER=%02x\n", 533 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 534 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 535 DDUMPREGS(3, ("registers were:\n")); 536 537 /* Clear the status bits */ 538 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 539 540 #ifdef DMAC_ARRAYCHAIN 541 chan->ch_xfer.dx_done = 0; 542 #endif 543 544 return (*chan->ch_error)(chan->ch_errorarg); 545 } 546 547 int 548 dmac_abort_xfer(struct device *self, struct dmac_dma_xfer *xf) 549 { 550 struct dmac_softc *sc = (void *)self; 551 struct dmac_channel_stat *chan = xf->dx_channel; 552 553 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 554 DMAC_CCR_INT | DMAC_CCR_HLT); 555 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 556 xf->dx_nextoff = xf->dx_nextsize = -1; 557 558 return 0; 559 } 560 561 #ifdef DMAC_DEBUG 562 static int 563 dmac_dump_regs(void) 564 { 565 struct dmac_channel_stat *chan = debugchan; 566 struct dmac_softc *sc; 567 568 if ((chan == 0) || (dmacdebug & 0xf0)) 569 return 0; 570 sc = (void *)chan->ch_softc; 571 572 printf("DMAC channel %d registers\n", chan->ch_channel); 573 printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 574 "CCR=%02x, CPR=%02x, GCR=%02x\n", 575 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 576 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 577 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 578 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 579 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 580 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 581 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 582 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 583 printf("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x, " 584 "MFCR=%02x, BFCR=%02x\n", 585 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 586 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 587 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 588 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 589 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 590 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 591 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 592 printf("DAR=%08x, MAR=%08x, BAR=%08x\n", 593 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 594 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 595 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 596 597 return 0; 598 } 599 #endif 600
Indexes created Wed Sep 24 05:09:52 GMT 2025