intio_dmac.c revision 1.30
1 /* $NetBSD: intio_dmac.c,v 1.30 2008/06/25 08:14:59 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.30 2008/06/25 08:14:59 isaki Exp $"); 38 39 #include "opt_m680x0.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 #include <machine/frame.h> 49 50 #include <arch/x68k/dev/intiovar.h> 51 #include <arch/x68k/dev/dmacvar.h> 52 53 #ifdef DMAC_DEBUG 54 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 55 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 56 int dmacdebug = 0; 57 #else 58 #define DPRINTF(n,x) 59 #define DDUMPREGS(n,x) 60 #endif 61 62 static void dmac_init_channels(struct dmac_softc *); 63 #ifdef DMAC_ARRAYCHAIN 64 static int dmac_program_arraychain(device_t, struct dmac_dma_xfer *, 65 u_int, u_int); 66 #endif 67 static int dmac_done(void *); 68 static int dmac_error(void *); 69 70 #ifdef DMAC_DEBUG 71 static int dmac_dump_regs(void); 72 #endif 73 74 /* 75 * autoconf stuff 76 */ 77 static int dmac_match(device_t, cfdata_t, void *); 78 static void dmac_attach(device_t, device_t, void *); 79 80 CFATTACH_DECL_NEW(dmac, sizeof(struct dmac_softc), 81 dmac_match, dmac_attach, NULL, NULL); 82 83 static int dmac_attached; 84 85 static int 86 dmac_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct intio_attach_args *ia = aux; 89 90 if (strcmp(ia->ia_name, "dmac") != 0) 91 return (0); 92 if (dmac_attached) 93 return (0); 94 95 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 96 ia->ia_addr = DMAC_ADDR; 97 98 /* fixed address */ 99 if (ia->ia_addr != DMAC_ADDR) 100 return (0); 101 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 102 return (0); 103 104 return 1; 105 } 106 107 static void 108 dmac_attach(device_t parent, device_t self, void *aux) 109 { 110 struct dmac_softc *sc = device_private(self); 111 struct intio_attach_args *ia = aux; 112 struct intio_softc *intio; 113 int r; 114 115 sc->sc_dev = self; 116 dmac_attached = 1; 117 118 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 119 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE); 120 #ifdef DIAGNOSTIC 121 if (r) 122 panic("IO map for DMAC corruption??"); 123 #endif 124 125 intio = device_private(parent); 126 intio->sc_dmac = self; 127 sc->sc_bst = ia->ia_bst; 128 bus_space_map(sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 129 dmac_init_channels(sc); 130 131 aprint_normal(": HD63450 DMAC\n"); 132 aprint_normal_dev(self, "4 channels available.\n"); 133 } 134 135 static void 136 dmac_init_channels(struct dmac_softc *sc) 137 { 138 int i; 139 140 DPRINTF(3, ("dmac_init_channels\n")); 141 for (i=0; i<DMAC_NCHAN; i++) { 142 sc->sc_channels[i].ch_channel = i; 143 sc->sc_channels[i].ch_name[0] = 0; 144 sc->sc_channels[i].ch_softc = sc->sc_dev; 145 bus_space_subregion(sc->sc_bst, sc->sc_bht, 146 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 147 &sc->sc_channels[i].ch_bht); 148 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 149 /* reset the status register */ 150 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 151 DMAC_REG_CSR, 0xff); 152 } 153 154 return; 155 } 156 157 158 /* 159 * Channel initialization/deinitialization per user device. 160 */ 161 struct dmac_channel_stat * 162 dmac_alloc_channel(device_t self, int ch, const char *name, int normalv, 163 dmac_intr_handler_t normal, void *normalarg, int errorv, 164 dmac_intr_handler_t error, void *errorarg) 165 { 166 struct intio_softc *intio = device_private(self); 167 struct dmac_softc *sc = device_private(intio->sc_dmac); 168 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 169 #ifdef DMAC_ARRAYCHAIN 170 int r, dummy; 171 #endif 172 173 aprint_normal_dev(sc->sc_dev, "allocating ch %d for %s.\n", 174 ch, name); 175 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 176 #ifdef DIAGNOSTIC 177 if (ch < 0 || ch >= DMAC_NCHAN) 178 panic("Invalid DMAC channel."); 179 if (chan->ch_name[0]) 180 panic("DMAC: channel in use."); 181 if (strlen(name) > 8) 182 panic("DMAC: wrong user name."); 183 #endif 184 185 #ifdef DMAC_ARRAYCHAIN 186 /* allocate the DMAC arraychaining map */ 187 r = bus_dmamem_alloc(intio->sc_dmat, 188 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 189 4, 0, &chan->ch_seg[0], 1, &dummy, 190 BUS_DMA_NOWAIT); 191 if (r) 192 panic("DMAC: cannot alloc DMA safe memory"); 193 r = bus_dmamem_map(intio->sc_dmat, 194 &chan->ch_seg[0], 1, 195 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 196 (void **) &chan->ch_map, 197 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 198 if (r) 199 panic("DMAC: cannot map DMA safe memory"); 200 #endif 201 202 /* fill the channel status structure by the default values. */ 203 strcpy(chan->ch_name, name); 204 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 205 DMAC_DCR_OPS_8BIT); 206 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL); 207 chan->ch_normalv = normalv; 208 chan->ch_errorv = errorv; 209 chan->ch_normal = normal; 210 chan->ch_error = error; 211 chan->ch_normalarg = normalarg; 212 chan->ch_errorarg = errorarg; 213 chan->ch_xfer.dx_dmamap = 0; 214 215 /* setup the device-specific registers */ 216 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 217 bus_space_write_1(sc->sc_bst, chan->ch_bht, 218 DMAC_REG_DCR, chan->ch_dcr); 219 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 220 221 /* 222 * X68k physical user space is a subset of the kernel space; 223 * the memory is always included in the physical user space, 224 * while the device is not. 225 */ 226 bus_space_write_1(sc->sc_bst, chan->ch_bht, 227 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 228 bus_space_write_1(sc->sc_bst, chan->ch_bht, 229 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 230 bus_space_write_1(sc->sc_bst, chan->ch_bht, 231 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 232 233 /* setup the interrupt handlers */ 234 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 235 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 236 237 intio_intr_establish_ext(normalv, name, "dma", dmac_done, chan); 238 intio_intr_establish_ext(errorv, name, "dmaerr", dmac_error, chan); 239 240 return chan; 241 } 242 243 int 244 dmac_free_channel(struct device *self, int ch, void *channel) 245 { 246 struct intio_softc *intio = (void *)self; 247 struct dmac_softc *sc = (void *)intio->sc_dmac; 248 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 249 250 DPRINTF(3, ("dmac_free_channel, %d\n", ch)); 251 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 252 if (chan != channel) 253 return -1; 254 if (ch != chan->ch_channel) 255 return -1; 256 257 #ifdef DMAC_ARRAYCHAIN 258 bus_dmamem_unmap(intio->sc_dmat, (void *)chan->ch_map, 259 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 260 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 261 #endif 262 chan->ch_name[0] = 0; 263 intio_intr_disestablish(chan->ch_normalv, channel); 264 intio_intr_disestablish(chan->ch_errorv, channel); 265 266 return 0; 267 } 268 269 /* 270 * Initialization / deinitialization per transfer. 271 */ 272 struct dmac_dma_xfer * 273 dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 274 bus_dmamap_t dmamap) 275 { 276 struct dmac_dma_xfer *xf = &chan->ch_xfer; 277 278 DPRINTF(3, ("dmac_alloc_xfer\n")); 279 xf->dx_channel = chan; 280 xf->dx_dmamap = dmamap; 281 xf->dx_tag = dmat; 282 #ifdef DMAC_ARRAYCHAIN 283 xf->dx_array = chan->ch_map; 284 xf->dx_done = 0; 285 #endif 286 xf->dx_nextoff = xf->dx_nextsize = -1; 287 return xf; 288 } 289 290 int 291 dmac_load_xfer(struct device *self, struct dmac_dma_xfer *xf) 292 { 293 struct dmac_softc *sc = (void *)self; 294 struct dmac_channel_stat *chan = xf->dx_channel; 295 296 DPRINTF(3, ("dmac_load_xfer\n")); 297 298 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 299 if (xf->dx_dmamap->dm_nsegs == 1) 300 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 301 else { 302 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 303 xf->dx_nextoff = ~0; 304 xf->dx_nextsize = ~0; 305 } 306 307 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 308 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 309 bus_space_write_1(sc->sc_bst, chan->ch_bht, 310 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 311 bus_space_write_4(sc->sc_bst, chan->ch_bht, 312 DMAC_REG_DAR, (int) xf->dx_device); 313 314 return 0; 315 } 316 317 struct dmac_dma_xfer * 318 dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 319 bus_dmamap_t dmamap, int dir, int scr, void *dar) 320 { 321 struct dmac_dma_xfer *xf; 322 struct dmac_softc *sc = (struct dmac_softc *)chan->ch_softc; 323 324 xf = dmac_alloc_xfer(chan, dmat, dmamap); 325 326 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 327 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 328 xf->dx_device = dar; 329 330 dmac_load_xfer(sc->sc_dev, xf); 331 332 return xf; 333 } 334 335 #ifdef DMAC_DEBUG 336 static struct dmac_channel_stat *debugchan = 0; 337 #endif 338 339 /* 340 * Do the actual transfer. 341 */ 342 int 343 dmac_start_xfer(struct device *self, struct dmac_dma_xfer *xf) 344 { 345 return dmac_start_xfer_offset(self, xf, 0, 0); 346 } 347 348 int 349 dmac_start_xfer_offset(struct device *self, struct dmac_dma_xfer *xf, 350 u_int offset, u_int size) 351 { 352 struct dmac_softc *sc = (void *)self; 353 struct dmac_channel_stat *chan = xf->dx_channel; 354 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 355 int go = DMAC_CCR_STR|DMAC_CCR_INT; 356 #ifdef DMAC_ARRAYCHAIN 357 int c; 358 #endif 359 360 DPRINTF(3, ("dmac_start_xfer\n")); 361 #ifdef DMAC_DEBUG 362 debugchan=chan; 363 #endif 364 365 if (size == 0) { 366 #ifdef DIAGNOSTIC 367 if (offset != 0) 368 panic("dmac_start_xfer_offset: invalid offset %x", 369 offset); 370 #endif 371 size = dmamap->dm_mapsize; 372 } 373 374 #ifdef DMAC_ARRAYCHAIN 375 #ifdef DIAGNOSTIC 376 if (xf->dx_done) 377 panic("dmac_start_xfer: DMA transfer in progress"); 378 #endif 379 #endif 380 DPRINTF(3, ("First program:\n")); 381 #ifdef DIAGNOSTIC 382 if ((offset >= dmamap->dm_mapsize) || 383 (offset + size > dmamap->dm_mapsize)) 384 panic("dmac_start_xfer_offset: invalid offset: " 385 "offset=%d, size=%d, mapsize=%ld", 386 offset, size, dmamap->dm_mapsize); 387 #endif 388 /* program DMAC in single block mode or array chainning mode */ 389 if (dmamap->dm_nsegs == 1) { 390 DPRINTF(3, ("single block mode\n")); 391 #ifdef DIAGNOSTIC 392 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 393 panic("dmac_start_xfer_offset: dmamap curruption"); 394 #endif 395 if (offset == xf->dx_nextoff && 396 size == xf->dx_nextsize) { 397 /* Use continued operation */ 398 go |= DMAC_CCR_CNT; 399 xf->dx_nextoff += size; 400 } else { 401 bus_space_write_4(sc->sc_bst, chan->ch_bht, 402 DMAC_REG_MAR, 403 (int) dmamap->dm_segs[0].ds_addr 404 + offset); 405 bus_space_write_2(sc->sc_bst, chan->ch_bht, 406 DMAC_REG_MTCR, (int) size); 407 xf->dx_nextoff = offset; 408 xf->dx_nextsize = size; 409 } 410 #ifdef DMAC_ARRAYCHAIN 411 xf->dx_done = 1; 412 #endif 413 } else { 414 #ifdef DMAC_ARRAYCHAIN 415 c = dmac_program_arraychain(self, xf, offset, size); 416 bus_space_write_4(sc->sc_bst, chan->ch_bht, 417 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 418 bus_space_write_2(sc->sc_bst, chan->ch_bht, 419 DMAC_REG_BTCR, c); 420 #else 421 panic("DMAC: unexpected use of arraychaining mode"); 422 #endif 423 } 424 425 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 426 427 /* START!! */ 428 DDUMPREGS(3, ("first start\n")); 429 430 #ifdef DMAC_ARRAYCHAIN 431 #if defined(M68040) || defined(M68060) 432 /* flush data cache for the map */ 433 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 434 dma_cachectl((void *) xf->dx_array, 435 sizeof(struct dmac_sg_array) * c); 436 #endif 437 #endif 438 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 439 440 if (xf->dx_nextoff != ~0) { 441 bus_space_write_4(sc->sc_bst, chan->ch_bht, 442 DMAC_REG_BAR, xf->dx_nextoff); 443 bus_space_write_2(sc->sc_bst, chan->ch_bht, 444 DMAC_REG_BTCR, xf->dx_nextsize); 445 } 446 447 return 0; 448 } 449 450 #ifdef DMAC_ARRAYCHAIN 451 static int 452 dmac_program_arraychain(struct device *self, struct dmac_dma_xfer *xf, 453 u_int offset, u_int size) 454 { 455 struct dmac_channel_stat *chan = xf->dx_channel; 456 int ch = chan->ch_channel; 457 struct x68k_bus_dmamap *map = xf->dx_dmamap; 458 int i, j; 459 460 /* XXX not yet!! */ 461 if (offset != 0 || size != map->dm_mapsize) 462 panic("dmac_program_arraychain: unsupported offset/size"); 463 464 DPRINTF(3, ("dmac_program_arraychain\n")); 465 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 466 i++, j++) { 467 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 468 #ifdef DIAGNOSTIC 469 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 470 panic("dmac_program_arraychain: wrong map: %ld", 471 map->dm_segs[j].ds_len); 472 #endif 473 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 474 } 475 xf->dx_done = j; 476 477 return i; 478 } 479 #endif 480 481 /* 482 * interrupt handlers. 483 */ 484 static int 485 dmac_done(void *arg) 486 { 487 struct dmac_channel_stat *chan = arg; 488 struct dmac_softc *sc = (void *)chan->ch_softc; 489 #ifdef DMAC_ARRAYCHAIN 490 struct dmac_dma_xfer *xf = &chan->ch_xfer; 491 struct x68k_bus_dmamap *map = xf->dx_dmamap; 492 int c; 493 #endif 494 495 DPRINTF(3, ("dmac_done\n")); 496 497 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 498 499 #ifdef DMAC_ARRAYCHAIN 500 if (xf->dx_done == map->dm_nsegs) { 501 xf->dx_done = 0; 502 #endif 503 /* Done */ 504 return (*chan->ch_normal)(chan->ch_normalarg); 505 #ifdef DMAC_ARRAYCHAIN 506 } 507 #endif 508 509 #ifdef DMAC_ARRAYCHAIN 510 /* Continue transfer */ 511 DPRINTF(3, ("reprograming\n")); 512 c = dmac_program_arraychain(sc->sc_dev, xf, 0, map->dm_mapsize); 513 514 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 515 bus_space_write_4(sc->sc_bst, chan->ch_bht, 516 DMAC_REG_BAR, (int) chan->ch_map); 517 bus_space_write_4(sc->sc_bst, chan->ch_bht, 518 DMAC_REG_DAR, (int) xf->dx_device); 519 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 520 521 /* START!! */ 522 DDUMPREGS(3, ("restart\n")); 523 bus_space_write_1(sc->sc_bst, chan->ch_bht, 524 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 525 526 return 1; 527 #endif 528 } 529 530 static int 531 dmac_error(void *arg) 532 { 533 struct dmac_channel_stat *chan = arg; 534 struct dmac_softc *sc = (void *)chan->ch_softc; 535 536 printf("DMAC transfer error CSR=%02x, CER=%02x\n", 537 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 538 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 539 DDUMPREGS(3, ("registers were:\n")); 540 541 /* Clear the status bits */ 542 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 543 544 #ifdef DMAC_ARRAYCHAIN 545 chan->ch_xfer.dx_done = 0; 546 #endif 547 548 return (*chan->ch_error)(chan->ch_errorarg); 549 } 550 551 int 552 dmac_abort_xfer(struct device *self, struct dmac_dma_xfer *xf) 553 { 554 struct dmac_softc *sc = (void *)self; 555 struct dmac_channel_stat *chan = xf->dx_channel; 556 557 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR, 558 DMAC_CCR_INT | DMAC_CCR_HLT); 559 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 560 xf->dx_nextoff = xf->dx_nextsize = -1; 561 562 return 0; 563 } 564 565 #ifdef DMAC_DEBUG 566 static int 567 dmac_dump_regs(void) 568 { 569 struct dmac_channel_stat *chan = debugchan; 570 struct dmac_softc *sc; 571 572 if ((chan == 0) || (dmacdebug & 0xf0)) 573 return 0; 574 sc = (void *)chan->ch_softc; 575 576 printf("DMAC channel %d registers\n", chan->ch_channel); 577 printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 578 "CCR=%02x, CPR=%02x, GCR=%02x\n", 579 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 580 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 581 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 582 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 583 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 584 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 585 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 586 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 587 printf("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x, " 588 "MFCR=%02x, BFCR=%02x\n", 589 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 590 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 591 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 592 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 593 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 594 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 595 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 596 printf("DAR=%08x, MAR=%08x, BAR=%08x\n", 597 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 598 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 599 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 600 601 return 0; 602 } 603 #endif 604
Indexes created Sun Sep 28 07:09:56 GMT 2025