intio_dmac.c revision 1.36
1 /* $NetBSD: intio_dmac.c,v 1.36 2017/08/11 07:08:40 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 34 */ 35 36 #include "opt_m68k_arch.h" 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: intio_dmac.c,v 1.36 2017/08/11 07:08:40 isaki Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 #include <machine/frame.h> 49 50 #include <arch/x68k/dev/intiovar.h> 51 #include <arch/x68k/dev/dmacvar.h> 52 53 #ifdef DMAC_DEBUG 54 #define DPRINTF(n,x) if (dmacdebug>((n)&0x0f)) printf x 55 #define DDUMPREGS(n,x) if (dmacdebug>((n)&0x0f)) {printf x; dmac_dump_regs();} 56 int dmacdebug = 0; 57 #else 58 #define DPRINTF(n,x) 59 #define DDUMPREGS(n,x) 60 #endif 61 62 static void dmac_init_channels(struct dmac_softc *); 63 #ifdef DMAC_ARRAYCHAIN 64 static int dmac_program_arraychain(device_t, struct dmac_dma_xfer *, 65 u_int, u_int); 66 #endif 67 static int dmac_done(void *); 68 static int dmac_error(void *); 69 70 #ifdef DMAC_DEBUG 71 static int dmac_dump_regs(void); 72 #endif 73 74 /* 75 * autoconf stuff 76 */ 77 static int dmac_match(device_t, cfdata_t, void *); 78 static void dmac_attach(device_t, device_t, void *); 79 80 CFATTACH_DECL_NEW(dmac, sizeof(struct dmac_softc), 81 dmac_match, dmac_attach, NULL, NULL); 82 83 static int dmac_attached; 84 85 static int 86 dmac_match(device_t parent, cfdata_t cf, void *aux) 87 { 88 struct intio_attach_args *ia = aux; 89 90 if (strcmp(ia->ia_name, "dmac") != 0) 91 return (0); 92 if (dmac_attached) 93 return (0); 94 95 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 96 ia->ia_addr = DMAC_ADDR; 97 98 /* fixed address */ 99 if (ia->ia_addr != DMAC_ADDR) 100 return (0); 101 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 102 return (0); 103 104 return 1; 105 } 106 107 static void 108 dmac_attach(device_t parent, device_t self, void *aux) 109 { 110 struct dmac_softc *sc = device_private(self); 111 struct intio_attach_args *ia = aux; 112 struct intio_softc *intio; 113 int r __diagused; 114 115 sc->sc_dev = self; 116 dmac_attached = 1; 117 118 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 119 r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE); 120 #ifdef DIAGNOSTIC 121 if (r) 122 panic("IO map for DMAC corruption??"); 123 #endif 124 125 intio = device_private(parent); 126 intio->sc_dmac = self; 127 sc->sc_bst = ia->ia_bst; 128 bus_space_map(sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 129 dmac_init_channels(sc); 130 131 aprint_normal(": HD63450 DMAC\n"); 132 aprint_normal_dev(self, "4 channels available.\n"); 133 } 134 135 static void 136 dmac_init_channels(struct dmac_softc *sc) 137 { 138 int i; 139 140 DPRINTF(3, ("dmac_init_channels\n")); 141 for (i=0; i<DMAC_NCHAN; i++) { 142 sc->sc_channels[i].ch_channel = i; 143 sc->sc_channels[i].ch_name[0] = 0; 144 sc->sc_channels[i].ch_softc = sc; 145 bus_space_subregion(sc->sc_bst, sc->sc_bht, 146 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 147 &sc->sc_channels[i].ch_bht); 148 sc->sc_channels[i].ch_xfer.dx_dmamap = 0; 149 /* reset the status register */ 150 bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht, 151 DMAC_REG_CSR, 0xff); 152 } 153 154 return; 155 } 156 157 158 /* 159 * Channel initialization/deinitialization per user device. 160 */ 161 struct dmac_channel_stat * 162 dmac_alloc_channel(device_t self, int ch, const char *name, 163 int normalv, dmac_intr_handler_t normal, void *normalarg, 164 int errorv, dmac_intr_handler_t error, void *errorarg, 165 uint8_t dcr, uint8_t ocr) 166 { 167 struct intio_softc *intio = device_private(self); 168 struct dmac_softc *dmac = device_private(intio->sc_dmac); 169 struct dmac_channel_stat *chan = &dmac->sc_channels[ch]; 170 #ifdef DMAC_ARRAYCHAIN 171 int r, dummy; 172 #endif 173 174 aprint_normal_dev(dmac->sc_dev, "allocating ch %d for %s.\n", 175 ch, name); 176 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 177 #ifdef DIAGNOSTIC 178 if (ch < 0 || ch >= DMAC_NCHAN) 179 panic("Invalid DMAC channel."); 180 if (chan->ch_name[0]) 181 panic("DMAC: channel in use."); 182 if (strlen(name) > 8) 183 panic("DMAC: wrong user name."); 184 #endif 185 186 #ifdef DMAC_ARRAYCHAIN 187 /* allocate the DMAC arraychaining map */ 188 r = bus_dmamem_alloc(intio->sc_dmat, 189 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 190 4, 0, &chan->ch_seg[0], 1, &dummy, 191 BUS_DMA_NOWAIT); 192 if (r) 193 panic("DMAC: cannot alloc DMA safe memory"); 194 r = bus_dmamem_map(intio->sc_dmat, 195 &chan->ch_seg[0], 1, 196 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE, 197 (void **) &chan->ch_map, 198 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 199 if (r) 200 panic("DMAC: cannot map DMA safe memory"); 201 #endif 202 203 /* fill the channel status structure by the default values. */ 204 strcpy(chan->ch_name, name); 205 chan->ch_dcr = dcr; 206 chan->ch_ocr = ocr; 207 chan->ch_normalv = normalv; 208 chan->ch_errorv = errorv; 209 chan->ch_normal = normal; 210 chan->ch_error = error; 211 chan->ch_normalarg = normalarg; 212 chan->ch_errorarg = errorarg; 213 chan->ch_xfer.dx_dmamap = 0; 214 215 /* setup the device-specific registers */ 216 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 217 bus_space_write_1(dmac->sc_bst, chan->ch_bht, 218 DMAC_REG_DCR, chan->ch_dcr); 219 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 220 /* OCR will be written at dmac_load_xfer() */ 221 222 /* 223 * X68k physical user space is a subset of the kernel space; 224 * the memory is always included in the physical user space, 225 * while the device is not. 226 */ 227 bus_space_write_1(dmac->sc_bst, chan->ch_bht, 228 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 229 bus_space_write_1(dmac->sc_bst, chan->ch_bht, 230 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 231 bus_space_write_1(dmac->sc_bst, chan->ch_bht, 232 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 233 234 /* setup the interrupt handlers */ 235 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 236 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 237 238 intio_intr_establish_ext(normalv, name, "dma", dmac_done, chan); 239 intio_intr_establish_ext(errorv, name, "dmaerr", dmac_error, chan); 240 241 return chan; 242 } 243 244 int 245 dmac_free_channel(device_t self, int ch, void *channel) 246 { 247 struct intio_softc *intio = device_private(self); 248 struct dmac_softc *dmac = device_private(intio->sc_dmac); 249 struct dmac_channel_stat *chan = &dmac->sc_channels[ch]; 250 251 DPRINTF(3, ("dmac_free_channel, %d\n", ch)); 252 DPRINTF(3, ("dmamap=%p\n", (void *)chan->ch_xfer.dx_dmamap)); 253 if (chan != channel) 254 return -1; 255 if (ch != chan->ch_channel) 256 return -1; 257 258 #ifdef DMAC_ARRAYCHAIN 259 bus_dmamem_unmap(intio->sc_dmat, (void *)chan->ch_map, 260 sizeof(struct dmac_sg_array) * DMAC_MAPSIZE); 261 bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1); 262 #endif 263 chan->ch_name[0] = 0; 264 intio_intr_disestablish(chan->ch_normalv, channel); 265 intio_intr_disestablish(chan->ch_errorv, channel); 266 267 return 0; 268 } 269 270 /* 271 * Initialization / deinitialization per transfer. 272 */ 273 struct dmac_dma_xfer * 274 dmac_alloc_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 275 bus_dmamap_t dmamap) 276 { 277 struct dmac_dma_xfer *xf = &chan->ch_xfer; 278 279 DPRINTF(3, ("dmac_alloc_xfer\n")); 280 xf->dx_channel = chan; 281 xf->dx_dmamap = dmamap; 282 xf->dx_tag = dmat; 283 #ifdef DMAC_ARRAYCHAIN 284 xf->dx_array = chan->ch_map; 285 xf->dx_done = 0; 286 #endif 287 xf->dx_nextoff = xf->dx_nextsize = -1; 288 return xf; 289 } 290 291 int 292 dmac_load_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf) 293 { 294 struct dmac_channel_stat *chan = xf->dx_channel; 295 296 DPRINTF(3, ("dmac_load_xfer\n")); 297 298 xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK; 299 if (xf->dx_dmamap->dm_nsegs == 1) 300 xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED; 301 else { 302 xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY; 303 xf->dx_nextoff = ~0; 304 xf->dx_nextsize = ~0; 305 } 306 307 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 308 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr); 309 bus_space_write_1(dmac->sc_bst, chan->ch_bht, 310 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 311 bus_space_write_4(dmac->sc_bst, chan->ch_bht, 312 DMAC_REG_DAR, (int) xf->dx_device); 313 314 return 0; 315 } 316 317 struct dmac_dma_xfer * 318 dmac_prepare_xfer(struct dmac_channel_stat *chan, bus_dma_tag_t dmat, 319 bus_dmamap_t dmamap, int dir, int scr, void *dar) 320 { 321 struct dmac_dma_xfer *xf; 322 struct dmac_softc *dmac = chan->ch_softc; 323 324 xf = dmac_alloc_xfer(chan, dmat, dmamap); 325 326 xf->dx_ocr = dir & DMAC_OCR_DIR_MASK; 327 xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 328 xf->dx_device = dar; 329 330 dmac_load_xfer(dmac, xf); 331 332 return xf; 333 } 334 335 #ifdef DMAC_DEBUG 336 static struct dmac_channel_stat *debugchan = 0; 337 #endif 338 339 /* 340 * Do the actual transfer. 341 */ 342 int 343 dmac_start_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf) 344 { 345 return dmac_start_xfer_offset(dmac, xf, 0, 0); 346 } 347 348 int 349 dmac_start_xfer_offset(struct dmac_softc *dmac, struct dmac_dma_xfer *xf, 350 u_int offset, u_int size) 351 { 352 struct dmac_channel_stat *chan = xf->dx_channel; 353 struct x68k_bus_dmamap *dmamap = xf->dx_dmamap; 354 int go = DMAC_CCR_STR|DMAC_CCR_INT; 355 #ifdef DMAC_ARRAYCHAIN 356 int c; 357 #endif 358 359 DPRINTF(3, ("dmac_start_xfer\n")); 360 #ifdef DMAC_DEBUG 361 debugchan=chan; 362 #endif 363 364 if (size == 0) { 365 #ifdef DIAGNOSTIC 366 if (offset != 0) 367 panic("dmac_start_xfer_offset: invalid offset %x", 368 offset); 369 #endif 370 size = dmamap->dm_mapsize; 371 } 372 373 #ifdef DMAC_ARRAYCHAIN 374 #ifdef DIAGNOSTIC 375 if (xf->dx_done) 376 panic("dmac_start_xfer: DMA transfer in progress"); 377 #endif 378 #endif 379 DPRINTF(3, ("First program:\n")); 380 #ifdef DIAGNOSTIC 381 if ((offset >= dmamap->dm_mapsize) || 382 (offset + size > dmamap->dm_mapsize)) 383 panic("dmac_start_xfer_offset: invalid offset: " 384 "offset=%d, size=%d, mapsize=%ld", 385 offset, size, dmamap->dm_mapsize); 386 #endif 387 /* program DMAC in single block mode or array chainning mode */ 388 if (dmamap->dm_nsegs == 1) { 389 DPRINTF(3, ("single block mode\n")); 390 #ifdef DIAGNOSTIC 391 if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len) 392 panic("dmac_start_xfer_offset: dmamap curruption"); 393 #endif 394 if (offset == xf->dx_nextoff && 395 size == xf->dx_nextsize) { 396 /* Use continued operation */ 397 go |= DMAC_CCR_CNT; 398 xf->dx_nextoff += size; 399 } else { 400 bus_space_write_4(dmac->sc_bst, chan->ch_bht, 401 DMAC_REG_MAR, 402 (int) dmamap->dm_segs[0].ds_addr 403 + offset); 404 bus_space_write_2(dmac->sc_bst, chan->ch_bht, 405 DMAC_REG_MTCR, (int) size); 406 xf->dx_nextoff = offset; 407 xf->dx_nextsize = size; 408 } 409 #ifdef DMAC_ARRAYCHAIN 410 xf->dx_done = 1; 411 #endif 412 } else { 413 #ifdef DMAC_ARRAYCHAIN 414 c = dmac_program_arraychain(self, xf, offset, size); 415 bus_space_write_4(dmac->sc_bst, chan->ch_bht, 416 DMAC_REG_BAR, (int) chan->ch_seg[0].ds_addr); 417 bus_space_write_2(dmac->sc_bst, chan->ch_bht, 418 DMAC_REG_BTCR, c); 419 #else 420 panic("DMAC: unexpected use of arraychaining mode"); 421 #endif 422 } 423 424 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 425 426 /* START!! */ 427 DDUMPREGS(3, ("first start\n")); 428 429 #ifdef DMAC_ARRAYCHAIN 430 #if defined(M68040) || defined(M68060) 431 /* flush data cache for the map */ 432 if (dmamap->dm_nsegs != 1 && mmutype == MMU_68040) 433 dma_cachectl((void *) xf->dx_array, 434 sizeof(struct dmac_sg_array) * c); 435 #endif 436 #endif 437 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR, go); 438 439 if (xf->dx_nextoff != ~0) { 440 bus_space_write_4(dmac->sc_bst, chan->ch_bht, 441 DMAC_REG_BAR, xf->dx_nextoff); 442 bus_space_write_2(dmac->sc_bst, chan->ch_bht, 443 DMAC_REG_BTCR, xf->dx_nextsize); 444 } 445 446 return 0; 447 } 448 449 #ifdef DMAC_ARRAYCHAIN 450 static int 451 dmac_program_arraychain(device_t self, struct dmac_dma_xfer *xf, 452 u_int offset, u_int size) 453 { 454 struct dmac_channel_stat *chan = xf->dx_channel; 455 int ch = chan->ch_channel; 456 struct x68k_bus_dmamap *map = xf->dx_dmamap; 457 int i, j; 458 459 /* XXX not yet!! */ 460 if (offset != 0 || size != map->dm_mapsize) 461 panic("dmac_program_arraychain: unsupported offset/size"); 462 463 DPRINTF(3, ("dmac_program_arraychain\n")); 464 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 465 i++, j++) { 466 xf->dx_array[i].da_addr = map->dm_segs[j].ds_addr; 467 #ifdef DIAGNOSTIC 468 if (map->dm_segs[j].ds_len > DMAC_MAXSEGSZ) 469 panic("dmac_program_arraychain: wrong map: %ld", 470 map->dm_segs[j].ds_len); 471 #endif 472 xf->dx_array[i].da_count = map->dm_segs[j].ds_len; 473 } 474 xf->dx_done = j; 475 476 return i; 477 } 478 #endif 479 480 /* 481 * interrupt handlers. 482 */ 483 static int 484 dmac_done(void *arg) 485 { 486 struct dmac_channel_stat *chan = arg; 487 struct dmac_softc *sc = chan->ch_softc; 488 #ifdef DMAC_ARRAYCHAIN 489 struct dmac_dma_xfer *xf = &chan->ch_xfer; 490 struct x68k_bus_dmamap *map = xf->dx_dmamap; 491 int c; 492 #endif 493 494 DPRINTF(3, ("dmac_done\n")); 495 496 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 497 498 #ifdef DMAC_ARRAYCHAIN 499 if (xf->dx_done == map->dm_nsegs) { 500 xf->dx_done = 0; 501 #endif 502 /* Done */ 503 return (*chan->ch_normal)(chan->ch_normalarg); 504 #ifdef DMAC_ARRAYCHAIN 505 } 506 #endif 507 508 #ifdef DMAC_ARRAYCHAIN 509 /* Continue transfer */ 510 DPRINTF(3, ("reprograming\n")); 511 c = dmac_program_arraychain(sc->sc_dev, xf, 0, map->dm_mapsize); 512 513 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 514 bus_space_write_4(sc->sc_bst, chan->ch_bht, 515 DMAC_REG_BAR, (int) chan->ch_map); 516 bus_space_write_4(sc->sc_bst, chan->ch_bht, 517 DMAC_REG_DAR, (int) xf->dx_device); 518 bus_space_write_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR, c); 519 520 /* START!! */ 521 DDUMPREGS(3, ("restart\n")); 522 bus_space_write_1(sc->sc_bst, chan->ch_bht, 523 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 524 525 return 1; 526 #endif 527 } 528 529 static int 530 dmac_error(void *arg) 531 { 532 struct dmac_channel_stat *chan = arg; 533 struct dmac_softc *sc = chan->ch_softc; 534 uint8_t csr, cer; 535 536 csr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 537 cer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 538 539 #ifndef DMAC_DEBUG 540 /* Software abort (CER=0x11) could happen on normal xfer termination */ 541 if (cer != 0x11) 542 #endif 543 { 544 printf("DMAC transfer error CSR=%02x, CER=%02x\n", csr, cer); 545 } 546 DDUMPREGS(3, ("registers were:\n")); 547 548 /* Clear the status bits */ 549 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 550 551 #ifdef DMAC_ARRAYCHAIN 552 chan->ch_xfer.dx_done = 0; 553 #endif 554 555 return (*chan->ch_error)(chan->ch_errorarg); 556 } 557 558 int 559 dmac_abort_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf) 560 { 561 struct dmac_channel_stat *chan = xf->dx_channel; 562 563 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR, 564 DMAC_CCR_INT | DMAC_CCR_SAB); 565 bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 566 xf->dx_nextoff = xf->dx_nextsize = -1; 567 568 return 0; 569 } 570 571 #ifdef DMAC_DEBUG 572 static int 573 dmac_dump_regs(void) 574 { 575 struct dmac_channel_stat *chan = debugchan; 576 struct dmac_softc *sc; 577 578 if ((chan == 0) || (dmacdebug & 0xf0)) 579 return 0; 580 sc = chan->ch_softc; 581 582 printf("DMAC channel %d registers\n", chan->ch_channel); 583 printf("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x, " 584 "CCR=%02x, CPR=%02x, GCR=%02x\n", 585 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 586 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 587 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 588 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 589 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 590 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 591 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 592 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 593 printf("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x, " 594 "MFCR=%02x, BFCR=%02x\n", 595 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 596 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 597 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 598 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 599 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 600 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 601 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 602 printf("DAR=%08x, MAR=%08x, BAR=%08x\n", 603 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 604 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 605 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 606 607 return 0; 608 } 609 #endif 610
Indexes created Fri Sep 26 20:09:58 GMT 2025