intio_dmac.c revision 1.5
1 /* $NetBSD: intio_dmac.c,v 1.5 1999/07/08 18:11:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/extent.h> 48 #include <vm/vm.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/frame.h> 53 54 #include <arch/x68k/dev/intiovar.h> 55 #include <arch/x68k/dev/dmacvar.h> 56 57 #ifdef DMAC_DEBUG 58 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 59 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 60 int dmacdebug = 0; 61 #else 62 #define DPRINTF(n,x) 63 #define DDUMPREGS(n,x) 64 #endif 65 66 static void dmac_init_channels __P((struct dmac_softc*)); 67 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*)); 68 static int dmac_done __P((void*)); 69 static int dmac_error __P((void*)); 70 71 #ifdef DMAC_DEBUG 72 static int dmac_dump_regs __P((void)); 73 #endif 74 75 /* 76 * autoconf stuff 77 */ 78 static int dmac_match __P((struct device *, struct cfdata *, void *)); 79 static void dmac_attach __P((struct device *, struct device *, void *)); 80 81 struct cfattach dmac_ca = { 82 sizeof(struct dmac_softc), dmac_match, dmac_attach 83 }; 84 85 static int 86 dmac_match(parent, cf, aux) 87 struct device *parent; 88 struct cfdata *cf; 89 void *aux; 90 { 91 struct intio_attach_args *ia = aux; 92 93 if (strcmp (ia->ia_name, "dmac") != 0) 94 return (0); 95 if (cf->cf_unit != 0) 96 return (0); 97 98 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 99 ia->ia_addr = DMAC_ADDR; 100 101 /* fixed address */ 102 if (ia->ia_addr != DMAC_ADDR) 103 return (0); 104 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 105 return (0); 106 107 return 1; 108 } 109 110 static void 111 dmac_attach(parent, self, aux) 112 struct device *parent, *self; 113 void *aux; 114 { 115 struct dmac_softc *sc = (struct dmac_softc *)self; 116 struct intio_attach_args *ia = aux; 117 int r; 118 119 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 120 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 121 #ifdef DIAGNOSTIC 122 if (r) 123 panic ("IO map for DMAC corruption??"); 124 #endif 125 126 ((struct intio_softc*) parent)->sc_dmac = self; 127 sc->sc_bst = ia->ia_bst; 128 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 129 dmac_init_channels(sc); 130 131 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 132 } 133 134 #define DMAC_MAPSIZE 64 135 /* Allocate statically in order to make sure the DMAC can reach the maps. */ 136 static struct dmac_sg_array dmac_map[DMAC_NCHAN][DMAC_MAPSIZE]; 137 138 static void 139 dmac_init_channels(sc) 140 struct dmac_softc *sc; 141 { 142 int i; 143 pmap_t pmap = pmap_kernel(); 144 145 for (i=0; i<DMAC_NCHAN; i++) { 146 sc->sc_channels[i].ch_channel = i; 147 sc->sc_channels[i].ch_name[0] = 0; 148 sc->sc_channels[i].ch_softc = &sc->sc_dev; 149 (void) pmap_extract(pmap, (vaddr_t) &dmac_map[i], 150 (paddr_t *) &sc->sc_channels[i].ch_map); 151 bus_space_subregion(sc->sc_bst, sc->sc_bht, 152 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 153 &sc->sc_channels[i].ch_bht); 154 } 155 156 return; 157 } 158 159 160 /* 161 * Channel initialization/deinitialization per user device. 162 */ 163 struct dmac_channel_stat * 164 dmac_alloc_channel(self, ch, name, 165 normalv, normal, normalarg, 166 errorv, error, errorarg) 167 struct device *self; 168 int ch; 169 char *name; 170 int normalv, errorv; 171 dmac_intr_handler_t normal, error; 172 void *normalarg, *errorarg; 173 { 174 struct intio_softc *intio = (void*) self; 175 struct dmac_softc *sc = (void*) intio->sc_dmac; 176 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 177 char intrname[16]; 178 179 #ifdef DIAGNOSTIC 180 if (ch < 0 || ch >= DMAC_NCHAN) 181 panic ("Invalid DMAC channel."); 182 if (chan->ch_name[0]) 183 panic ("DMAC: channel in use."); 184 if (strlen(name) > 8) 185 panic ("DMAC: wrong user name."); 186 #endif 187 188 /* fill the channel status structure. */ 189 strcpy(chan->ch_name, name); 190 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 191 DMAC_DCR_OPS_8BIT); 192 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_CHAIN_ARRAY | 193 DMAC_OCR_REQG_EXTERNAL); 194 chan->ch_normalv = normalv; 195 chan->ch_errorv = errorv; 196 chan->ch_normal = normal; 197 chan->ch_error = error; 198 chan->ch_normalarg = normalarg; 199 chan->ch_errorarg = errorarg; 200 chan->ch_xfer_in_progress = 0; 201 202 /* setup the device-specific registers */ 203 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 204 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 205 DMAC_REG_DCR, chan->ch_dcr); 206 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 207 208 /* 209 * X68k physical user space is a subset of the kernel space; 210 * the memory is always included in the physical user space, 211 * while the device is not. 212 */ 213 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 214 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 215 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 216 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 217 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 218 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 219 220 /* setup the interrupt handlers */ 221 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 222 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 223 224 strcpy(intrname, name); 225 strcat(intrname, "dma"); 226 intio_intr_establish (normalv, intrname, dmac_done, chan); 227 228 strcpy(intrname, name); 229 strcat(intrname, "dmaerr"); 230 intio_intr_establish (errorv, intrname, dmac_error, chan); 231 232 return chan; 233 } 234 235 int 236 dmac_free_channel(self, ch, channel) 237 struct device *self; 238 int ch; 239 void *channel; 240 { 241 struct dmac_softc *sc = (void*) self; 242 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 243 244 if (chan != channel) 245 return -1; 246 if (ch != chan->ch_channel) 247 return -1; 248 #if DIAGNOSTIC 249 if (chan->ch_xfer_in_progress) 250 panic ("dmac_free_channel: DMA transfer in progress"); 251 #endif 252 253 chan->ch_name[0] = 0; 254 intio_intr_disestablish(chan->ch_normalv, channel); 255 intio_intr_disestablish(chan->ch_errorv, channel); 256 257 return 0; 258 } 259 260 /* 261 * Initialization / deinitialization per transfer. 262 */ 263 struct dmac_dma_xfer * 264 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 265 struct dmac_channel_stat *chan; 266 bus_dma_tag_t dmat; 267 bus_dmamap_t dmamap; 268 int dir, scr; 269 void *dar; 270 { 271 struct dmac_dma_xfer *r = malloc (sizeof (struct dmac_dma_xfer), 272 M_DEVBUF, M_WAITOK); 273 274 r->dx_channel = chan; 275 r->dx_dmamap = dmamap; 276 r->dx_tag = dmat; 277 r->dx_ocr = dir & DMAC_OCR_DIR_MASK; 278 r->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 279 r->dx_device = dar; 280 r->dx_done = 0; 281 282 return r; 283 } 284 285 #ifdef DMAC_DEBUG 286 static struct dmac_channel_stat *debugchan = 0; 287 #endif 288 289 #ifdef DMAC_DEBUG 290 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 291 dnivr, deivr, ddfcr, dmfcr, dbfcr; 292 static u_int16_t dmtcr, dbtcr; 293 static u_int32_t ddar, dmar, dbar; 294 #endif 295 /* 296 * Do the actual transfer. 297 */ 298 int 299 dmac_start_xfer(self, xf) 300 struct device *self; 301 struct dmac_dma_xfer *xf; 302 { 303 struct dmac_softc *sc = (void*) self; 304 struct dmac_channel_stat *chan = xf->dx_channel; 305 int c; 306 307 308 #ifdef DMAC_DEBUG 309 debugchan=chan; 310 #endif 311 bus_space_write_1(sc->sc_bst, chan->ch_bht, 312 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 313 bus_space_write_1(sc->sc_bst, chan->ch_bht, 314 DMAC_REG_SCR, xf->dx_scr); 315 316 /* program DMAC in array chainning mode */ 317 xf->dx_done = 0; 318 DPRINTF (3, ("First program:\n")); 319 c = dmac_program_arraychain(self, xf); 320 321 /* setup the address/count registers */ 322 bus_space_write_4(sc->sc_bst, chan->ch_bht, 323 DMAC_REG_BAR, (int) chan->ch_map); 324 bus_space_write_4(sc->sc_bst, chan->ch_bht, 325 DMAC_REG_DAR, (int) xf->dx_device); 326 bus_space_write_1(sc->sc_bst, chan->ch_bht, 327 DMAC_REG_CSR, 0xff); 328 bus_space_write_2(sc->sc_bst, chan->ch_bht, 329 DMAC_REG_BTCR, c); 330 331 /* START!! */ 332 DDUMPREGS (3, ("first start\n")); 333 #ifdef DMAC_DEBUG 334 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 335 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 336 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 337 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 338 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 339 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 340 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 341 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 342 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 343 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 344 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 345 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 346 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 347 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 348 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 349 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 350 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 351 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 352 #endif 353 #if defined(M68040) || defined(M68060) 354 if (mmutype == MMU_68040) 355 dma_cachectl((caddr_t) &dmac_map[chan->ch_channel], 356 sizeof(struct dmac_sg_array)*DMAC_MAPSIZE); 357 #endif 358 bus_space_write_1(sc->sc_bst, chan->ch_bht, 359 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 360 chan->ch_xfer_in_progress = xf; 361 362 return 0; 363 } 364 365 static int 366 dmac_program_arraychain(self, xf) 367 struct device *self; 368 struct dmac_dma_xfer *xf; 369 { 370 struct dmac_channel_stat *chan = xf->dx_channel; 371 int ch = chan->ch_channel; 372 struct x68k_bus_dmamap *map = xf->dx_dmamap; 373 int i, j; 374 375 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 376 i++, j++) { 377 dmac_map[ch][i].da_addr = map->dm_segs[j].ds_addr; 378 #ifdef DIAGNOSTIC 379 if (map->dm_segs[j].ds_len > 0xff00) 380 panic ("dmac_program_arraychain: wrong map: %ld", map->dm_segs[j].ds_len); 381 #endif 382 dmac_map[ch][i].da_count = map->dm_segs[j].ds_len; 383 } 384 xf->dx_done = j; 385 386 return i; 387 } 388 389 /* 390 * interrupt handlers. 391 */ 392 static int 393 dmac_done(arg) 394 void *arg; 395 { 396 struct dmac_channel_stat *chan = arg; 397 struct dmac_softc *sc = (void*) chan->ch_softc; 398 struct dmac_dma_xfer *xf = chan->ch_xfer_in_progress; 399 struct x68k_bus_dmamap *map = xf->dx_dmamap; 400 int c; 401 402 DPRINTF (3, ("dmac_done\n")); 403 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 404 405 if (xf->dx_done == map->dm_nsegs) { 406 /* Done */ 407 chan->ch_xfer_in_progress = 0; 408 return (*chan->ch_normal) (chan->ch_normalarg); 409 } 410 411 /* Continue transfer */ 412 DPRINTF (3, ("reprograming\n")); 413 c = dmac_program_arraychain (&sc->sc_dev, xf); 414 415 bus_space_write_4(sc->sc_bst, chan->ch_bht, 416 DMAC_REG_BAR, (int) chan->ch_map); 417 bus_space_write_4(sc->sc_bst, chan->ch_bht, 418 DMAC_REG_DAR, (int) xf->dx_device); 419 bus_space_write_1(sc->sc_bst, chan->ch_bht, 420 DMAC_REG_CSR, 0xff); 421 bus_space_write_2(sc->sc_bst, chan->ch_bht, 422 DMAC_REG_BTCR, c); 423 424 /* START!! */ 425 DDUMPREGS (3, ("restart\n")); 426 bus_space_write_1(sc->sc_bst, chan->ch_bht, 427 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 428 429 return 1; 430 } 431 432 static int 433 dmac_error(arg) 434 void *arg; 435 { 436 struct dmac_channel_stat *chan = arg; 437 struct dmac_softc *sc = (void*) chan->ch_softc; 438 439 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 440 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 441 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 442 DPRINTF(5, ("registers were:\n")); 443 #ifdef DMAC_DEBUG 444 if ((dmacdebug & 0x0f) > 5) { 445 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 446 "CCR=%02x, CPR=%02x, GCR=%02x\n", 447 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 448 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 449 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 450 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 451 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 452 ddar, dmar, dbar); 453 } 454 #endif 455 456 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 457 DDUMPREGS(3, ("dmac_error\n")); 458 459 return (*chan->ch_error) (chan->ch_errorarg); 460 } 461 462 463 #ifdef DMAC_DEBUG 464 static int 465 dmac_dump_regs(void) 466 { 467 struct dmac_channel_stat *chan = debugchan; 468 struct dmac_softc *sc; 469 470 if ((chan == 0) || (dmacdebug & 0xf0)) return; 471 sc = (void*) chan->ch_softc; 472 473 printf ("DMAC channel %d registers\n", chan->ch_channel); 474 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 475 "CCR=%02x, CPR=%02x, GCR=%02x\n", 476 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 477 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 478 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 479 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 480 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 481 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 482 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 483 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 484 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 485 "MFCR=%02x, BFCR=%02x\n", 486 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 487 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 488 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 489 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 490 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 491 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 492 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 493 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 494 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 495 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 496 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 497 498 return 0; 499 } 500 #endif 501
Indexes created Thu Sep 25 16:09:42 GMT 2025