intio_dmac.c revision 1.6
1 /* $NetBSD: intio_dmac.c,v 1.6 2000/04/18 21:06:06 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k. 41 */ 42 43 #include "opt_m680x0.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/malloc.h> 49 #include <sys/extent.h> 50 #include <vm/vm.h> 51 52 #include <machine/bus.h> 53 #include <machine/cpu.h> 54 #include <machine/frame.h> 55 56 #include <arch/x68k/dev/intiovar.h> 57 #include <arch/x68k/dev/dmacvar.h> 58 59 #ifdef DMAC_DEBUG 60 #define DPRINTF(n,x) if (dmacdebug>(n)&0x0f) printf x 61 #define DDUMPREGS(n,x) if (dmacdebug>(n)&0x0f) {printf x; dmac_dump_regs();} 62 int dmacdebug = 0; 63 #else 64 #define DPRINTF(n,x) 65 #define DDUMPREGS(n,x) 66 #endif 67 68 static void dmac_init_channels __P((struct dmac_softc*)); 69 static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*)); 70 static int dmac_done __P((void*)); 71 static int dmac_error __P((void*)); 72 73 #ifdef DMAC_DEBUG 74 static int dmac_dump_regs __P((void)); 75 #endif 76 77 /* 78 * autoconf stuff 79 */ 80 static int dmac_match __P((struct device *, struct cfdata *, void *)); 81 static void dmac_attach __P((struct device *, struct device *, void *)); 82 83 struct cfattach dmac_ca = { 84 sizeof(struct dmac_softc), dmac_match, dmac_attach 85 }; 86 87 static int 88 dmac_match(parent, cf, aux) 89 struct device *parent; 90 struct cfdata *cf; 91 void *aux; 92 { 93 struct intio_attach_args *ia = aux; 94 95 if (strcmp (ia->ia_name, "dmac") != 0) 96 return (0); 97 if (cf->cf_unit != 0) 98 return (0); 99 100 if (ia->ia_addr == INTIOCF_ADDR_DEFAULT) 101 ia->ia_addr = DMAC_ADDR; 102 103 /* fixed address */ 104 if (ia->ia_addr != DMAC_ADDR) 105 return (0); 106 if (ia->ia_intr != INTIOCF_INTR_DEFAULT) 107 return (0); 108 109 return 1; 110 } 111 112 static void 113 dmac_attach(parent, self, aux) 114 struct device *parent, *self; 115 void *aux; 116 { 117 struct dmac_softc *sc = (struct dmac_softc *)self; 118 struct intio_attach_args *ia = aux; 119 int r; 120 121 ia->ia_size = DMAC_CHAN_SIZE * DMAC_NCHAN; 122 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 123 #ifdef DIAGNOSTIC 124 if (r) 125 panic ("IO map for DMAC corruption??"); 126 #endif 127 128 ((struct intio_softc*) parent)->sc_dmac = self; 129 sc->sc_bst = ia->ia_bst; 130 bus_space_map (sc->sc_bst, ia->ia_addr, ia->ia_size, 0, &sc->sc_bht); 131 dmac_init_channels(sc); 132 133 printf (": HD63450 DMAC\n%s: 4 channels available.\n", self->dv_xname); 134 } 135 136 #define DMAC_MAPSIZE 64 137 /* Allocate statically in order to make sure the DMAC can reach the maps. */ 138 static struct dmac_sg_array dmac_map[DMAC_NCHAN][DMAC_MAPSIZE]; 139 140 static void 141 dmac_init_channels(sc) 142 struct dmac_softc *sc; 143 { 144 int i; 145 pmap_t pmap = pmap_kernel(); 146 147 for (i=0; i<DMAC_NCHAN; i++) { 148 sc->sc_channels[i].ch_channel = i; 149 sc->sc_channels[i].ch_name[0] = 0; 150 sc->sc_channels[i].ch_softc = &sc->sc_dev; 151 (void) pmap_extract(pmap, (vaddr_t) &dmac_map[i], 152 (paddr_t *) &sc->sc_channels[i].ch_map); 153 bus_space_subregion(sc->sc_bst, sc->sc_bht, 154 DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE, 155 &sc->sc_channels[i].ch_bht); 156 } 157 158 return; 159 } 160 161 162 /* 163 * Channel initialization/deinitialization per user device. 164 */ 165 struct dmac_channel_stat * 166 dmac_alloc_channel(self, ch, name, 167 normalv, normal, normalarg, 168 errorv, error, errorarg) 169 struct device *self; 170 int ch; 171 char *name; 172 int normalv, errorv; 173 dmac_intr_handler_t normal, error; 174 void *normalarg, *errorarg; 175 { 176 struct intio_softc *intio = (void*) self; 177 struct dmac_softc *sc = (void*) intio->sc_dmac; 178 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 179 char intrname[16]; 180 181 #ifdef DIAGNOSTIC 182 if (ch < 0 || ch >= DMAC_NCHAN) 183 panic ("Invalid DMAC channel."); 184 if (chan->ch_name[0]) 185 panic ("DMAC: channel in use."); 186 if (strlen(name) > 8) 187 panic ("DMAC: wrong user name."); 188 #endif 189 190 /* fill the channel status structure. */ 191 strcpy(chan->ch_name, name); 192 chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC | 193 DMAC_DCR_OPS_8BIT); 194 chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_CHAIN_ARRAY | 195 DMAC_OCR_REQG_EXTERNAL); 196 chan->ch_normalv = normalv; 197 chan->ch_errorv = errorv; 198 chan->ch_normal = normal; 199 chan->ch_error = error; 200 chan->ch_normalarg = normalarg; 201 chan->ch_errorarg = errorarg; 202 chan->ch_xfer_in_progress = 0; 203 204 /* setup the device-specific registers */ 205 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 206 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 207 DMAC_REG_DCR, chan->ch_dcr); 208 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0); 209 210 /* 211 * X68k physical user space is a subset of the kernel space; 212 * the memory is always included in the physical user space, 213 * while the device is not. 214 */ 215 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 216 DMAC_REG_BFCR, DMAC_FC_USER_DATA); 217 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 218 DMAC_REG_MFCR, DMAC_FC_USER_DATA); 219 bus_space_write_1 (sc->sc_bst, chan->ch_bht, 220 DMAC_REG_DFCR, DMAC_FC_KERNEL_DATA); 221 222 /* setup the interrupt handlers */ 223 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv); 224 bus_space_write_1 (sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv); 225 226 strcpy(intrname, name); 227 strcat(intrname, "dma"); 228 intio_intr_establish (normalv, intrname, dmac_done, chan); 229 230 strcpy(intrname, name); 231 strcat(intrname, "dmaerr"); 232 intio_intr_establish (errorv, intrname, dmac_error, chan); 233 234 return chan; 235 } 236 237 int 238 dmac_free_channel(self, ch, channel) 239 struct device *self; 240 int ch; 241 void *channel; 242 { 243 struct dmac_softc *sc = (void*) self; 244 struct dmac_channel_stat *chan = &sc->sc_channels[ch]; 245 246 if (chan != channel) 247 return -1; 248 if (ch != chan->ch_channel) 249 return -1; 250 #if DIAGNOSTIC 251 if (chan->ch_xfer_in_progress) 252 panic ("dmac_free_channel: DMA transfer in progress"); 253 #endif 254 255 chan->ch_name[0] = 0; 256 intio_intr_disestablish(chan->ch_normalv, channel); 257 intio_intr_disestablish(chan->ch_errorv, channel); 258 259 return 0; 260 } 261 262 /* 263 * Initialization / deinitialization per transfer. 264 */ 265 struct dmac_dma_xfer * 266 dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar) 267 struct dmac_channel_stat *chan; 268 bus_dma_tag_t dmat; 269 bus_dmamap_t dmamap; 270 int dir, scr; 271 void *dar; 272 { 273 struct dmac_dma_xfer *r = malloc (sizeof (struct dmac_dma_xfer), 274 M_DEVBUF, M_WAITOK); 275 276 r->dx_channel = chan; 277 r->dx_dmamap = dmamap; 278 r->dx_tag = dmat; 279 r->dx_ocr = dir & DMAC_OCR_DIR_MASK; 280 r->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK); 281 r->dx_device = dar; 282 r->dx_done = 0; 283 284 return r; 285 } 286 287 #ifdef DMAC_DEBUG 288 static struct dmac_channel_stat *debugchan = 0; 289 #endif 290 291 #ifdef DMAC_DEBUG 292 static u_int8_t dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr, 293 dnivr, deivr, ddfcr, dmfcr, dbfcr; 294 static u_int16_t dmtcr, dbtcr; 295 static u_int32_t ddar, dmar, dbar; 296 #endif 297 /* 298 * Do the actual transfer. 299 */ 300 int 301 dmac_start_xfer(self, xf) 302 struct device *self; 303 struct dmac_dma_xfer *xf; 304 { 305 struct dmac_softc *sc = (void*) self; 306 struct dmac_channel_stat *chan = xf->dx_channel; 307 int c; 308 309 310 #ifdef DMAC_DEBUG 311 debugchan=chan; 312 #endif 313 bus_space_write_1(sc->sc_bst, chan->ch_bht, 314 DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr)); 315 bus_space_write_1(sc->sc_bst, chan->ch_bht, 316 DMAC_REG_SCR, xf->dx_scr); 317 318 /* program DMAC in array chainning mode */ 319 xf->dx_done = 0; 320 DPRINTF (3, ("First program:\n")); 321 c = dmac_program_arraychain(self, xf); 322 323 /* setup the address/count registers */ 324 bus_space_write_4(sc->sc_bst, chan->ch_bht, 325 DMAC_REG_BAR, (int) chan->ch_map); 326 bus_space_write_4(sc->sc_bst, chan->ch_bht, 327 DMAC_REG_DAR, (int) xf->dx_device); 328 bus_space_write_1(sc->sc_bst, chan->ch_bht, 329 DMAC_REG_CSR, 0xff); 330 bus_space_write_2(sc->sc_bst, chan->ch_bht, 331 DMAC_REG_BTCR, c); 332 333 /* START!! */ 334 DDUMPREGS (3, ("first start\n")); 335 #ifdef DMAC_DEBUG 336 dcsr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR); 337 dcer = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER); 338 ddcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR); 339 docr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR); 340 dscr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR); 341 dccr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR); 342 dcpr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR); 343 dgcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR); 344 dnivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR); 345 deivr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR); 346 ddfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR); 347 dmfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR); 348 dbfcr = bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR); 349 dmtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR); 350 dbtcr = bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR); 351 ddar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR); 352 dmar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR); 353 dbar = bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR); 354 #endif 355 #if defined(M68040) || defined(M68060) 356 if (mmutype == MMU_68040) 357 dma_cachectl((caddr_t) &dmac_map[chan->ch_channel], 358 sizeof(struct dmac_sg_array)*DMAC_MAPSIZE); 359 #endif 360 bus_space_write_1(sc->sc_bst, chan->ch_bht, 361 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 362 chan->ch_xfer_in_progress = xf; 363 364 return 0; 365 } 366 367 static int 368 dmac_program_arraychain(self, xf) 369 struct device *self; 370 struct dmac_dma_xfer *xf; 371 { 372 struct dmac_channel_stat *chan = xf->dx_channel; 373 int ch = chan->ch_channel; 374 struct x68k_bus_dmamap *map = xf->dx_dmamap; 375 int i, j; 376 377 for (i=0, j=xf->dx_done; i<DMAC_MAPSIZE && j<map->dm_nsegs; 378 i++, j++) { 379 dmac_map[ch][i].da_addr = map->dm_segs[j].ds_addr; 380 #ifdef DIAGNOSTIC 381 if (map->dm_segs[j].ds_len > 0xff00) 382 panic ("dmac_program_arraychain: wrong map: %ld", map->dm_segs[j].ds_len); 383 #endif 384 dmac_map[ch][i].da_count = map->dm_segs[j].ds_len; 385 } 386 xf->dx_done = j; 387 388 return i; 389 } 390 391 /* 392 * interrupt handlers. 393 */ 394 static int 395 dmac_done(arg) 396 void *arg; 397 { 398 struct dmac_channel_stat *chan = arg; 399 struct dmac_softc *sc = (void*) chan->ch_softc; 400 struct dmac_dma_xfer *xf = chan->ch_xfer_in_progress; 401 struct x68k_bus_dmamap *map = xf->dx_dmamap; 402 int c; 403 404 DPRINTF (3, ("dmac_done\n")); 405 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 406 407 if (xf->dx_done == map->dm_nsegs) { 408 /* Done */ 409 chan->ch_xfer_in_progress = 0; 410 return (*chan->ch_normal) (chan->ch_normalarg); 411 } 412 413 /* Continue transfer */ 414 DPRINTF (3, ("reprograming\n")); 415 c = dmac_program_arraychain (&sc->sc_dev, xf); 416 417 bus_space_write_4(sc->sc_bst, chan->ch_bht, 418 DMAC_REG_BAR, (int) chan->ch_map); 419 bus_space_write_4(sc->sc_bst, chan->ch_bht, 420 DMAC_REG_DAR, (int) xf->dx_device); 421 bus_space_write_1(sc->sc_bst, chan->ch_bht, 422 DMAC_REG_CSR, 0xff); 423 bus_space_write_2(sc->sc_bst, chan->ch_bht, 424 DMAC_REG_BTCR, c); 425 426 /* START!! */ 427 DDUMPREGS (3, ("restart\n")); 428 bus_space_write_1(sc->sc_bst, chan->ch_bht, 429 DMAC_REG_CCR, DMAC_CCR_STR|DMAC_CCR_INT); 430 431 return 1; 432 } 433 434 static int 435 dmac_error(arg) 436 void *arg; 437 { 438 struct dmac_channel_stat *chan = arg; 439 struct dmac_softc *sc = (void*) chan->ch_softc; 440 441 printf ("DMAC transfer error CSR=%02x, CER=%02x\n", 442 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 443 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER)); 444 DPRINTF(5, ("registers were:\n")); 445 #ifdef DMAC_DEBUG 446 if ((dmacdebug & 0x0f) > 5) { 447 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 448 "CCR=%02x, CPR=%02x, GCR=%02x\n", 449 dcsr, dcer, ddcr, docr, dscr, dccr, dcpr, dgcr); 450 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, " 451 "DFCR=%02x, MFCR=%02x, BFCR=%02x\n", 452 dnivr, deivr, dmtcr, dbtcr, ddfcr, dmfcr, dbfcr); 453 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 454 ddar, dmar, dbar); 455 } 456 #endif 457 458 bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff); 459 DDUMPREGS(3, ("dmac_error\n")); 460 461 return (*chan->ch_error) (chan->ch_errorarg); 462 } 463 464 465 #ifdef DMAC_DEBUG 466 static int 467 dmac_dump_regs(void) 468 { 469 struct dmac_channel_stat *chan = debugchan; 470 struct dmac_softc *sc; 471 472 if ((chan == 0) || (dmacdebug & 0xf0)) return; 473 sc = (void*) chan->ch_softc; 474 475 printf ("DMAC channel %d registers\n", chan->ch_channel); 476 printf ("CSR=%02x, CER=%02x, DCR=%02x, OCR=%02x, SCR=%02x," 477 "CCR=%02x, CPR=%02x, GCR=%02x\n", 478 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR), 479 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CER), 480 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DCR), 481 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_OCR), 482 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR), 483 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CCR), 484 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CPR), 485 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_GCR)); 486 printf ("NIVR=%02x, EIVR=%02x, MTCR=%04x, BTCR=%04x, DFCR=%02x," 487 "MFCR=%02x, BFCR=%02x\n", 488 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_NIVR), 489 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_EIVR), 490 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_MTCR), 491 bus_space_read_2(sc->sc_bst, chan->ch_bht, DMAC_REG_BTCR), 492 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_DFCR), 493 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_MFCR), 494 bus_space_read_1(sc->sc_bst, chan->ch_bht, DMAC_REG_BFCR)); 495 printf ("DAR=%08x, MAR=%08x, BAR=%08x\n", 496 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_DAR), 497 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_MAR), 498 bus_space_read_4(sc->sc_bst, chan->ch_bht, DMAC_REG_BAR)); 499 500 return 0; 501 } 502 #endif 503
Indexes created Thu Sep 25 16:09:42 GMT 2025