mha.c revision 1.11.4.4
1 /* $NetBSD: mha.c,v 1.11.4.4 1999/03/14 16:50:59 minoura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Masaru Oki, Takumi Nakamura and Masanobu Saitoh. All rights reserved. 5 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * Copyright (c) 1994 Jarle Greipsland 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. The name of the author may not be used to endorse or promote products 33 * derived from this software without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 37 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 39 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 43 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 44 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 45 * POSSIBILITY OF SUCH DAMAGE. 46 */ 47 48 #include "opt_ddb.h" 49 50 /* Synchronous data transfers? */ 51 #define SPC_USE_SYNCHRONOUS 0 52 #define SPC_SYNC_REQ_ACK_OFS 8 53 54 /* Default DMA mode? */ 55 #define MHA_DMA_LIMIT_XFER 1 56 #define MHA_DMA_BURST_XFER 1 57 #define MHA_DMA_SHORT_BUS_CYCLE 1 58 59 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 60 | (MHA_DMA_BURST_XFER << 2) \ 61 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 62 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 63 | (MHA_DMA_BURST_XFER << 2) \ 64 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 65 66 /* Include debug functions? At the end of this file there are a bunch of 67 * functions that will print out various information regarding queued SCSI 68 * commands, driver state and chip contents. You can call them from the 69 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 70 * kernel uses less memory) but you lose the debugging facilities. 71 */ 72 #define SPC_DEBUG 0 73 74 /* End of customizable parameters */ 75 76 /* 77 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 78 */ 79 80 #include <sys/types.h> 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/kernel.h> 84 #include <sys/errno.h> 85 #include <sys/ioctl.h> 86 #include <sys/device.h> 87 #include <sys/buf.h> 88 #include <sys/proc.h> 89 #include <sys/user.h> 90 #include <sys/queue.h> 91 92 #include <machine/bus.h> 93 94 #include <dev/scsipi/scsi_all.h> 95 #include <dev/scsipi/scsipi_all.h> 96 #include <dev/scsipi/scsi_message.h> 97 #include <dev/scsipi/scsiconf.h> 98 99 #include <x68k/x68k/iodevice.h> 100 #include <x68k/dev/mb86601reg.h> 101 #include <x68k/dev/mhavar.h> 102 #include <x68k/dev/intiovar.h> 103 #include <x68k/dev/scsiromvar.h> 104 105 #if 0 106 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 107 #else 108 #define WAIT {while (sc->sc_pc[2] & 0x40);} 109 #endif 110 111 #define SSR (sc->sc_pc[2]) 112 #define SS_IREQUEST 0x80 113 #define SS_BUSY 0x40 114 #define SS_DREG_FULL 0x02 115 116 #define NSR (sc->sc_pc[3]) 117 118 #define SIR (sc->sc_pc[4]) 119 120 #define CMR (sc->sc_pc[5]) 121 #define CMD_SEL_AND_CMD 0x00 122 #define CMD_SELECT 0x09 123 #define CMD_SET_ATN 0x0a 124 #define CMD_RESET_ATN 0x0b 125 #define CMD_RESET_ACK 0x0d 126 #define CMD_SEND_FROM_MPU 0x10 127 #define CMD_SEND_FROM_DMA 0x11 128 #define CMD_RECEIVE_TO_MPU 0x12 129 #define CMD_RECEIVE_TO_DMA 0x13 130 #define CMD_RECEIVE_MSG 0x1a 131 #define CMD_RECEIVE_STS 0x1c 132 #define CMD_SOFT_RESET 0x40 133 #define CMD_SCSI_RESET 0x42 134 #define CMD_SET_UP_REG 0x43 135 136 #define SCR (sc->sc_pc[11]) 137 138 #define TMR (sc->sc_pc[12]) 139 #define TM_SYNC 0x80 140 #define TM_ASYNC 0x00 141 142 #define WAR (sc->sc_pc[15]) 143 #define WA_MCSBUFWIN 0x00 144 #define WA_UPMWIN 0x80 145 #define WA_INITWIN 0xc0 146 147 #define MBR (sc->sc_pc[15]) 148 149 #define ISCSR (sc->sc_ps[2]) 150 151 #define CCR (sc->sc_pcx[0]) 152 #define OIR (sc->sc_pcx[1]) 153 #define AMR (sc->sc_pcx[2]) 154 #define SMR (sc->sc_pcx[3]) 155 #define SRR (sc->sc_pcx[4]) 156 #define STR (sc->sc_pcx[5]) 157 #define RTR (sc->sc_pcx[6]) 158 #define ATR (sc->sc_pcx[7]) 159 #define PER (sc->sc_pcx[8]) 160 #define IER (sc->sc_pcx[9]) 161 #define IE_ALL 0xBF 162 163 #define GLR (sc->sc_pcx[10]) 164 #define DMR (sc->sc_pcx[11]) 165 #define IMR (sc->sc_pcx[12]) 166 167 168 #ifndef DDB 170 #define Debugger() panic("should call debugger here (mha.c)") 171 #endif /* ! DDB */ 172 173 174 #if SPC_DEBUG 175 #define SPC_SHOWACBS 0x01 176 #define SPC_SHOWINTS 0x02 177 #define SPC_SHOWCMDS 0x04 178 #define SPC_SHOWMISC 0x08 179 #define SPC_SHOWTRAC 0x10 180 #define SPC_SHOWSTART 0x20 181 #define SPC_SHOWPHASE 0x40 182 #define SPC_SHOWDMA 0x80 183 #define SPC_SHOWCCMDS 0x100 184 #define SPC_SHOWMSGS 0x200 185 #define SPC_DOBREAK 0x400 186 187 int mha_debug = 188 #if 0 189 0x7FF; 190 #else 191 SPC_SHOWSTART|SPC_SHOWTRAC; 192 #endif 193 194 195 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 196 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 197 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 198 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 199 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 200 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 201 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 202 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 203 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 204 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 205 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 206 #else 207 #define SPC_ACBS(str) 208 #define SPC_MISC(str) 209 #define SPC_INTS(str) 210 #define SPC_TRACE(str) 211 #define SPC_CMDS(str) 212 #define SPC_START(str) 213 #define SPC_PHASE(str) 214 #define SPC_DMA(str) 215 #define SPC_MSGS(str) 216 #define SPC_BREAK() 217 #define SPC_ASSERT(x) 218 #endif 219 220 int mhamatch __P((struct device *, struct cfdata *, void *)); 221 void mhaattach __P((struct device *, struct device *, void *)); 222 void mhaselect __P((struct mha_softc *, 223 u_char, u_char, u_char *, u_char)); 224 void mha_scsi_reset __P((struct mha_softc *)); 225 void mha_reset __P((struct mha_softc *)); 226 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 227 void mha_sense __P((struct mha_softc *, struct acb *)); 228 void mha_msgin __P((struct mha_softc *)); 229 void mha_msgout __P((struct mha_softc *)); 230 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 231 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 232 int mha_dataout __P((struct mha_softc *, u_char *, int)); 233 int mha_datain __P((struct mha_softc *, u_char *, int)); 234 void mha_abort __P((struct mha_softc *, struct acb *)); 235 void mha_init __P((struct mha_softc *)); 236 int mha_scsi_cmd __P((struct scsipi_xfer *)); 237 int mha_poll __P((struct mha_softc *, struct acb *)); 238 void mha_sched __P((struct mha_softc *)); 239 void mha_done __P((struct mha_softc *, struct acb *)); 240 int mhaintr __P((void*)); 241 void mha_timeout __P((void *)); 242 void mha_minphys __P((struct buf *)); 243 void mha_dequeue __P((struct mha_softc *, struct acb *)); 244 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 245 #if SPC_DEBUG 246 void mha_print_acb __P((struct acb *)); 247 void mha_show_scsi_cmd __P((struct acb *)); 248 void mha_print_active_acb __P((void)); 249 void mha_dump_driver __P((struct mha_softc *)); 250 #endif 251 252 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 253 254 struct cfattach mha_ca = { 255 sizeof(struct mha_softc), mhamatch, mhaattach 256 }; 257 258 extern struct cfdriver mha_cd; 259 260 struct scsipi_device mha_dev = { 261 NULL, /* Use default error handler */ 262 NULL, /* have a queue, served by this */ 263 NULL, /* have no async handler */ 264 NULL, /* Use default 'done' routine */ 265 }; 266 267 /* 269 * returns non-zero value if a controller is found. 270 */ 271 int 272 mhamatch(parent, cf, aux) 273 struct device *parent; 274 struct cfdata *cf; 275 void *aux; 276 { 277 struct intio_attach_args *ia = aux; 278 bus_space_tag_t iot = ia->ia_bst; 279 bus_space_handle_t ioh; 280 281 ia->ia_size=0x20; 282 if (ia->ia_addr != 0xea0000) 283 return 0; 284 285 if (intio_map_allocate_region(parent->dv_parent, ia, 286 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 287 return 0; 288 289 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 290 &ioh) < 0) 291 return 0; 292 if (!badaddr (INTIO_ADDR(ia->ia_addr + 0))) 293 return 0; 294 bus_space_unmap(iot, ioh, 0x20); 295 296 return 1; 297 } 298 299 /* 300 */ 301 302 struct mha_softc *tmpsc; 303 304 void 305 mhaattach(parent, self, aux) 306 struct device *parent, *self; 307 void *aux; 308 { 309 struct mha_softc *sc = (void *)self; 310 struct intio_attach_args *ia = aux; 311 312 tmpsc = sc; /* XXX */ 313 314 SPC_TRACE(("mhaattach ")); 315 sc->sc_state = SPC_INIT; 316 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 317 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 318 /* XXX: FAKE */ 319 320 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 321 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 322 sc->sc_pcx = &sc->sc_pc[0x10]; 323 324 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 325 326 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 327 328 mha_init(sc); /* Init chip and driver */ 329 330 printf("\n%s: Resetting SCSI bus... ", self->dv_xname); 331 mha_scsi_reset(sc); /* XXX: some devices need this. */ 332 printf("done\n"); 333 334 sc->sc_phase = BUSFREE_PHASE; 335 336 /* 337 * Fill in the adapter. 338 */ 339 sc->sc_adapter.scsipi_cmd = mha_scsi_cmd; 340 sc->sc_adapter.scsipi_minphys = mha_minphys; 341 342 /* 343 * Fill in the prototype scsi_link 344 */ 345 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 346 sc->sc_link.adapter_softc = sc; 347 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 348 sc->sc_link.adapter = &sc->sc_adapter; 349 sc->sc_link.device = &mha_dev; 350 sc->sc_link.openings = 2; 351 sc->sc_link.scsipi_scsi.max_target = 7; 352 sc->sc_link.scsipi_scsi.max_lun = 7; 353 sc->sc_link.type = BUS_SCSI; 354 355 sc->sc_spcinitialized = 0; 356 WAR = WA_INITWIN; 357 #if 1 358 CCR = 0x14; 359 OIR = sc->sc_id; 360 AMR = 0x00; 361 SMR = 0x00; 362 SRR = 0x00; 363 STR = 0x20; 364 RTR = 0x40; 365 ATR = 0x01; 366 PER = 0xc9; 367 #endif 368 IER = IE_ALL; /* */ 369 #if 1 370 GLR = 0x00; 371 DMR = 0x30; 372 IMR = 0x00; 373 #endif 374 WAR = WA_MCSBUFWIN; 375 376 /* drop off */ 377 while (SSR & SS_IREQUEST) 378 { 379 unsigned a = ISCSR; 380 } 381 382 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 383 384 SPC_TRACE(("waiting for intr...")); 385 while (!(SSR & SS_IREQUEST)) 386 delay(10); 387 mhaintr (sc); 388 389 tmpsc = NULL; 390 391 config_found(self, &sc->sc_link, scsiprint); 392 } 393 394 #if 0 395 void 396 mha_reset(sc) 397 struct mha_softc *sc; 398 { 399 u_short dummy; 400 printf("reset..."); 401 CMR = CMD_SOFT_RESET; 402 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 403 dummy = sc->sc_ps[-1]; 404 dummy = sc->sc_ps[-1]; 405 dummy = sc->sc_ps[-1]; 406 dummy = sc->sc_ps[-1]; 407 asm volatile ("nop"); 408 CMR = CMD_SOFT_RESET; 409 sc->sc_spcinitialized = 0; 410 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 411 while(!sc->sc_spcinitialized); 412 413 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 414 printf("done.\n"); 415 } 416 #endif 417 418 /* 419 * Pull the SCSI RST line for 500us. 420 */ 421 void 422 mha_scsi_reset(sc) /* FINISH? */ 423 struct mha_softc *sc; 424 { 425 426 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 427 while (!(SSR&SS_IREQUEST)) 428 delay(10); 429 } 430 431 /* 432 * Initialize mha SCSI driver. 433 */ 434 void 435 mha_init(sc) 436 struct mha_softc *sc; 437 { 438 struct acb *acb; 439 int r; 440 441 if (sc->sc_state == SPC_INIT) { 442 /* First time through; initialize. */ 443 TAILQ_INIT(&sc->ready_list); 444 TAILQ_INIT(&sc->nexus_list); 445 TAILQ_INIT(&sc->free_list); 446 sc->sc_nexus = NULL; 447 acb = sc->sc_acb; 448 bzero(acb, sizeof(sc->sc_acb)); 449 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 450 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 451 acb++; 452 } 453 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 454 } else { 455 /* Cancel any active commands. */ 456 sc->sc_flags |= SPC_ABORTING; 457 sc->sc_state = SPC_IDLE; 458 if ((acb = sc->sc_nexus) != NULL) { 459 acb->xs->error = XS_DRIVER_STUFFUP; 460 mha_done(sc, acb); 461 } 462 while ((acb = sc->nexus_list.tqh_first) != NULL) { 463 acb->xs->error = XS_DRIVER_STUFFUP; 464 mha_done(sc, acb); 465 } 466 } 467 468 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 469 for (r = 0; r < 8; r++) { 470 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 471 472 ti->flags = 0; 473 #if SPC_USE_SYNCHRONOUS 474 ti->flags |= T_SYNCMODE; 475 ti->period = sc->sc_minsync; 476 ti->offset = SPC_SYNC_REQ_ACK_OFS; 477 #else 478 ti->period = ti->offset = 0; 479 #endif 480 ti->width = 0; 481 } 482 483 sc->sc_state = SPC_IDLE; 484 } 485 486 void 487 mha_free_acb(sc, acb, flags) 488 struct mha_softc *sc; 489 struct acb *acb; 490 int flags; 491 { 492 int s; 493 494 s = splbio(); 495 496 acb->flags = 0; 497 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 498 499 /* 500 * If there were none, wake anybody waiting for one to come free, 501 * starting with queued entries. 502 */ 503 if (acb->chain.tqe_next == 0) 504 wakeup(&sc->free_list); 505 506 splx(s); 507 } 508 509 510 /* 512 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 513 */ 514 515 /* 516 * Expected sequence: 517 * 1) Command inserted into ready list 518 * 2) Command selected for execution 519 * 3) Command won arbitration and has selected target device 520 * 4) Send message out (identify message, eventually also sync.negotiations) 521 * 5) Send command 522 * 5a) Receive disconnect message, disconnect. 523 * 5b) Reselected by target 524 * 5c) Receive identify message from target. 525 * 6) Send or receive data 526 * 7) Receive status 527 * 8) Receive message (command complete etc.) 528 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 529 * Repeat 2-8 (no disconnects please...) 530 */ 531 532 /* 533 * Start a selection. This is used by mha_sched() to select an idle target, 534 * and by mha_done() to immediately reselect a target to get sense information. 535 */ 536 void 537 mhaselect(sc, target, lun, cmd, clen) 538 struct mha_softc *sc; 539 u_char target, lun; 540 u_char *cmd; 541 u_char clen; 542 { 543 #if 0 544 struct scsi_link *sc_link = acb->xs->sc_link; 545 #endif 546 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 547 int i; 548 int s; 549 550 s = splbio(); /* XXX */ 551 552 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 553 554 /* CDB SPC MCS REG */ 555 /* Now the command into the FIFO */ 556 WAIT; 557 #if 1 558 SPC_MISC(("[cmd:")); 559 for (i = 0; i < clen; i++) 560 { 561 unsigned c = cmd[i]; 562 if (i == 1) 563 c |= lun << 5; 564 SPC_MISC((" %02x", c)); 565 sc->sc_pcx[i] = c; 566 } 567 SPC_MISC(("], target=%d\n", target)); 568 #else 569 bcopy(cmd, sc->sc_pcx, clen); 570 #endif 571 if (NSR & 0x80) 572 panic("scsistart: already selected..."); 573 sc->sc_phase = COMMAND_PHASE; 574 575 /* new state ASP_SELECTING */ 576 sc->sc_state = SPC_SELECTING; 577 578 SIR = target; 579 #if 0 580 CMR = CMD_SELECT; 581 #else 582 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 583 #endif 584 splx(s); 585 } 586 587 #if 0 588 int 589 mha_reselect(sc, message) 590 struct mha_softc *sc; 591 u_char message; 592 { 593 u_char selid, target, lun; 594 struct acb *acb; 595 struct scsipi_link *sc_link; 596 struct spc_tinfo *ti; 597 598 /* 599 * The SCSI chip made a snapshot of the data bus while the reselection 600 * was being negotiated. This enables us to determine which target did 601 * the reselect. 602 */ 603 selid = sc->sc_selid & ~(1 << sc->sc_id); 604 if (selid & (selid - 1)) { 605 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 606 sc->sc_dev.dv_xname, selid); 607 SPC_BREAK(); 608 goto reset; 609 } 610 611 /* 612 * Search wait queue for disconnected cmd 613 * The list should be short, so I haven't bothered with 614 * any more sophisticated structures than a simple 615 * singly linked list. 616 */ 617 target = ffs(selid) - 1; 618 lun = message & 0x07; 619 for (acb = sc->nexus_list.tqh_first; acb != NULL; 620 acb = acb->chain.tqe_next) { 621 sc_link = acb->xs->sc_link; 622 if (sc_link->scsipi_scsi.target == target && 623 sc_link->scsipi_scsi.lun == lun) 624 break; 625 } 626 if (acb == NULL) { 627 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 628 sc->sc_dev.dv_xname, target, lun); 629 SPC_BREAK(); 630 goto abort; 631 } 632 633 /* Make this nexus active again. */ 634 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 635 sc->sc_state = SPC_HASNEXUS; 636 sc->sc_nexus = acb; 637 ti = &sc->sc_tinfo[target]; 638 ti->lubusy |= (1 << lun); 639 mha_setsync(sc, ti); 640 641 if (acb->flags & ACB_RESET) 642 mha_sched_msgout(sc, SEND_DEV_RESET); 643 else if (acb->flags & ACB_ABORTED) 644 mha_sched_msgout(sc, SEND_ABORT); 645 646 /* Do an implicit RESTORE POINTERS. */ 647 sc->sc_dp = acb->daddr; 648 sc->sc_dleft = acb->dleft; 649 sc->sc_cp = (u_char *)&acb->cmd; 650 sc->sc_cleft = acb->clen; 651 652 return (0); 653 654 reset: 655 mha_sched_msgout(sc, SEND_DEV_RESET); 656 return (1); 657 658 abort: 659 mha_sched_msgout(sc, SEND_ABORT); 660 return (1); 661 } 662 #endif 663 /* 664 * Start a SCSI-command 665 * This function is called by the higher level SCSI-driver to queue/run 666 * SCSI-commands. 667 */ 668 int 669 mha_scsi_cmd(xs) 670 struct scsipi_xfer *xs; 671 { 672 struct scsipi_link *sc_link = xs->sc_link; 673 struct mha_softc *sc = sc_link->adapter_softc; 674 struct acb *acb; 675 int s, flags; 676 677 SPC_TRACE(("[mha_scsi_cmd] ")); 678 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 679 sc_link->scsipi_scsi.target)); 680 681 flags = xs->flags; 682 683 /* Get a mha command block */ 684 s = splbio(); 685 acb = sc->free_list.tqh_first; 686 if (acb) { 687 TAILQ_REMOVE(&sc->free_list, acb, chain); 688 ACB_SETQ(acb, ACB_QNONE); 689 } 690 splx(s); 691 692 if (acb == NULL) { 693 SPC_MISC(("TRY_AGAIN_LATER")); 694 return TRY_AGAIN_LATER; 695 } 696 697 /* Initialize acb */ 698 acb->xs = xs; 699 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 700 acb->clen = xs->cmdlen; 701 acb->daddr = xs->data; 702 acb->dleft = xs->datalen; 703 acb->stat = 0; 704 705 s = splbio(); 706 ACB_SETQ(acb, ACB_QREADY); 707 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 708 #if 1 709 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 710 #endif 711 712 /* 713 * 714 */ 715 if (sc->sc_state == SPC_IDLE) 716 mha_sched(sc); 717 718 splx(s); 719 720 if (flags & SCSI_POLL) { 721 /* Not allowed to use interrupts, use polling instead */ 722 return mha_poll(sc, acb); 723 } 724 725 SPC_MISC(("SUCCESSFULLY_QUEUED")); 726 return SUCCESSFULLY_QUEUED; 727 } 728 729 /* 730 * Adjust transfer size in buffer structure 731 */ 732 void 733 mha_minphys(bp) 734 struct buf *bp; 735 { 736 737 SPC_TRACE(("mha_minphys ")); 738 minphys(bp); 739 } 740 741 /* 742 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 743 */ 744 int 745 mha_poll(sc, acb) 746 struct mha_softc *sc; 747 struct acb *acb; 748 { 749 struct scsipi_xfer *xs = acb->xs; 750 int count = xs->timeout * 100; 751 int s = splbio(); 752 753 SPC_TRACE(("[mha_poll] ")); 754 755 while (count) { 756 /* 757 * If we had interrupts enabled, would we 758 * have got an interrupt? 759 */ 760 if (SSR & SS_IREQUEST) 761 mhaintr(sc); 762 if ((xs->flags & ITSDONE) != 0) 763 break; 764 DELAY(10); 765 #if 1 766 if (sc->sc_state == SPC_IDLE) { 767 SPC_TRACE(("[mha_poll: rescheduling] ")); 768 mha_sched(sc); 769 } 770 #endif 771 count--; 772 } 773 774 if (count == 0) { 775 SPC_MISC(("mha_poll: timeout")); 776 mha_timeout((caddr_t)acb); 777 } 778 splx(s); 779 return COMPLETE; 780 } 781 782 /* 784 * LOW LEVEL SCSI UTILITIES 785 */ 786 787 /* 788 * Set synchronous transfer offset and period. 789 */ 790 inline void 791 mha_setsync(sc, ti) 792 struct mha_softc *sc; 793 struct spc_tinfo *ti; 794 { 795 } 796 797 798 /* 800 * Schedule a SCSI operation. This has now been pulled out of the interrupt 801 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 802 * save us an unecessary interrupt just to get things going. Should only be 803 * called when state == SPC_IDLE and at bio pl. 804 */ 805 void 806 mha_sched(sc) 807 register struct mha_softc *sc; 808 { 809 struct scsipi_link *sc_link; 810 struct acb *acb; 811 int t; 812 813 SPC_TRACE(("[mha_sched] ")); 814 if (sc->sc_state != SPC_IDLE) 815 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 816 817 if (sc->sc_flags & SPC_ABORTING) 818 return; 819 820 /* 821 * Find first acb in ready queue that is for a target/lunit 822 * combinations that is not busy. 823 */ 824 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 825 struct spc_tinfo *ti; 826 sc_link = acb->xs->sc_link; 827 t = sc_link->scsipi_scsi.target; 828 ti = &sc->sc_tinfo[t]; 829 if (!(ti->lubusy & (1 << sc_link->scsipi_scsi.lun))) { 830 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 831 panic("mha: busy entry on ready list"); 832 TAILQ_REMOVE(&sc->ready_list, acb, chain); 833 ACB_SETQ(acb, ACB_QNONE); 834 sc->sc_nexus = acb; 835 sc->sc_flags = 0; 836 sc->sc_prevphase = INVALID_PHASE; 837 sc->sc_dp = acb->daddr; 838 sc->sc_dleft = acb->dleft; 839 ti->lubusy |= (1<<sc_link->scsipi_scsi.lun); 840 mhaselect(sc, t, sc_link->scsipi_scsi.lun, 841 (u_char *)&acb->cmd, acb->clen); 842 break; 843 } else { 844 SPC_MISC(("%d:%d busy\n", 845 sc_link->scsipi_scsi.target, 846 sc_link->scsipi_scsi.lun)); 847 } 848 } 849 } 850 851 void 853 mha_sense(sc, acb) 854 struct mha_softc *sc; 855 struct acb *acb; 856 { 857 struct scsipi_xfer *xs = acb->xs; 858 struct scsipi_link *sc_link = xs->sc_link; 859 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 860 struct scsipi_sense *ss = (void *)&acb->cmd; 861 862 SPC_MISC(("requesting sense ")); 863 /* Next, setup a request sense command block */ 864 bzero(ss, sizeof(*ss)); 865 ss->opcode = REQUEST_SENSE; 866 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 867 ss->length = sizeof(struct scsipi_sense_data); 868 acb->clen = sizeof(*ss); 869 acb->daddr = (char *)&xs->sense; 870 acb->dleft = sizeof(struct scsipi_sense_data); 871 acb->flags |= ACB_CHKSENSE; 872 ti->senses++; 873 if (acb->flags & ACB_QNEXUS) 874 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 875 if (acb == sc->sc_nexus) { 876 mhaselect(sc, sc_link->scsipi_scsi.target, 877 sc_link->scsipi_scsi.lun, 878 (void *)&acb->cmd, acb->clen); 879 } else { 880 mha_dequeue(sc, acb); 881 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 882 if (sc->sc_state == SPC_IDLE) 883 mha_sched(sc); 884 } 885 } 886 887 /* 888 * POST PROCESSING OF SCSI_CMD (usually current) 889 */ 890 void 891 mha_done(sc, acb) 892 struct mha_softc *sc; 893 struct acb *acb; 894 { 895 struct scsipi_xfer *xs = acb->xs; 896 struct scsipi_link *sc_link = xs->sc_link; 897 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 898 899 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 900 901 #if 1 902 untimeout(mha_timeout, acb); 903 #endif 904 905 /* 906 * Now, if we've come here with no error code, i.e. we've kept the 907 * initial XS_NOERROR, and the status code signals that we should 908 * check sense, we'll need to set up a request sense cmd block and 909 * push the command back into the ready queue *before* any other 910 * commands for this target/lunit, else we lose the sense info. 911 * We don't support chk sense conditions for the request sense cmd. 912 */ 913 if (xs->error == XS_NOERROR) { 914 if ((acb->flags & ACB_ABORTED) != 0) { 915 xs->error = XS_TIMEOUT; 916 } else if (acb->flags & ACB_CHKSENSE) { 917 xs->error = XS_SENSE; 918 } else { 919 switch (acb->stat & ST_MASK) { 920 case SCSI_CHECK: 921 { 922 struct scsipi_sense *ss = (void *)&acb->cmd; 923 SPC_MISC(("requesting sense ")); 924 /* First, save the return values */ 925 xs->resid = acb->dleft; 926 xs->status = acb->stat; 927 /* Next, setup a request sense command block */ 928 bzero(ss, sizeof(*ss)); 929 ss->opcode = REQUEST_SENSE; 930 /*ss->byte2 = sc_link->lun << 5;*/ 931 ss->length = sizeof(struct scsipi_sense_data); 932 acb->clen = sizeof(*ss); 933 acb->daddr = (char *)&xs->sense; 934 acb->dleft = sizeof(struct scsipi_sense_data); 935 acb->flags |= ACB_CHKSENSE; 936 /*XXX - must take off queue here */ 937 if (acb != sc->sc_nexus) { 938 panic("%s: mha_sched: floating acb %p", 939 sc->sc_dev.dv_xname, acb); 940 } 941 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 942 ACB_SETQ(acb, ACB_QREADY); 943 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 944 ti->senses++; 945 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 946 if (sc->sc_nexus == acb) { 947 sc->sc_nexus = NULL; 948 sc->sc_state = SPC_IDLE; 949 mha_sched(sc); 950 } 951 #if 0 952 mha_sense(sc, acb); 953 #endif 954 return; 955 } 956 case SCSI_BUSY: 957 xs->error = XS_BUSY; 958 break; 959 case SCSI_OK: 960 xs->resid = acb->dleft; 961 break; 962 default: 963 xs->error = XS_DRIVER_STUFFUP; 964 #if SPC_DEBUG 965 printf("%s: mha_done: bad stat 0x%x\n", 966 sc->sc_dev.dv_xname, acb->stat); 967 #endif 968 break; 969 } 970 } 971 } 972 973 xs->flags |= ITSDONE; 974 975 #if SPC_DEBUG 976 if ((mha_debug & SPC_SHOWMISC) != 0) { 977 if (xs->resid != 0) 978 printf("resid=%d ", xs->resid); 979 if (xs->error == XS_SENSE) 980 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 981 else 982 printf("error=%d\n", xs->error); 983 } 984 #endif 985 986 /* 987 * Remove the ACB from whatever queue it's on. 988 */ 989 switch (acb->flags & ACB_QBITS) { 990 case ACB_QNONE: 991 if (acb != sc->sc_nexus) { 992 panic("%s: floating acb", sc->sc_dev.dv_xname); 993 } 994 sc->sc_nexus = NULL; 995 sc->sc_state = SPC_IDLE; 996 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 997 mha_sched(sc); 998 break; 999 case ACB_QREADY: 1000 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1001 break; 1002 case ACB_QNEXUS: 1003 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1004 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1005 break; 1006 case ACB_QFREE: 1007 panic("%s: dequeue: busy acb on free list", 1008 sc->sc_dev.dv_xname); 1009 break; 1010 default: 1011 panic("%s: dequeue: unknown queue %d", 1012 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1013 } 1014 1015 /* Put it on the free list, and clear flags. */ 1016 #if 0 1017 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1018 acb->flags = ACB_QFREE; 1019 #else 1020 mha_free_acb(sc, acb, xs->flags); 1021 #endif 1022 1023 ti->cmds++; 1024 scsipi_done(xs); 1025 } 1026 1027 void 1028 mha_dequeue(sc, acb) 1029 struct mha_softc *sc; 1030 struct acb *acb; 1031 { 1032 1033 if (acb->flags & ACB_QNEXUS) { 1034 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1035 } else { 1036 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1037 } 1038 } 1039 1040 /* 1042 * INTERRUPT/PROTOCOL ENGINE 1043 */ 1044 1045 /* 1046 * Schedule an outgoing message by prioritizing it, and asserting 1047 * attention on the bus. We can only do this when we are the initiator 1048 * else there will be an illegal command interrupt. 1049 */ 1050 #define mha_sched_msgout(m) \ 1051 do { \ 1052 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1053 CMR = CMD_SET_ATN; \ 1054 sc->sc_msgpriq |= (m); \ 1055 } while (0) 1056 1057 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1058 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1059 #define ISEXTMSG(m) ((m) == 0x01) 1060 1061 /* 1062 * Precondition: 1063 * The SCSI bus is already in the MSGI phase and there is a message byte 1064 * on the bus, along with an asserted REQ signal. 1065 */ 1066 void 1067 mha_msgin(sc) 1068 register struct mha_softc *sc; 1069 { 1070 register int v; 1071 int n; 1072 1073 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1074 1075 /* 1076 * Prepare for a new message. A message should (according 1077 * to the SCSI standard) be transmitted in one single 1078 * MESSAGE_IN_PHASE. If we have been in some other phase, 1079 * then this is a new message. 1080 */ 1081 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1082 sc->sc_flags &= ~SPC_DROP_MSGI; 1083 sc->sc_imlen = 0; 1084 } 1085 1086 WAIT; 1087 1088 v = MBR; /* modified byte */ 1089 v = sc->sc_pcx[0]; 1090 1091 sc->sc_imess[sc->sc_imlen] = v; 1092 1093 /* 1094 * If we're going to reject the message, don't bother storing 1095 * the incoming bytes. But still, we need to ACK them. 1096 */ 1097 1098 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1099 CMR = CMD_SET_ATN; 1100 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1101 printf("<dropping msg byte %x>", 1102 sc->sc_imess[sc->sc_imlen]); 1103 return; 1104 } 1105 1106 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1107 mha_sched_msgout(SEND_REJECT); 1108 sc->sc_flags |= SPC_DROP_MSGI; 1109 } else { 1110 sc->sc_imlen++; 1111 /* 1112 * This testing is suboptimal, but most 1113 * messages will be of the one byte variety, so 1114 * it should not effect performance 1115 * significantly. 1116 */ 1117 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1118 goto gotit; 1119 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1120 goto gotit; 1121 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1122 sc->sc_imlen == sc->sc_imess[1] + 2) 1123 goto gotit; 1124 } 1125 #if 0 1126 /* Ack what we have so far */ 1127 ESPCMD(sc, ESPCMD_MSGOK); 1128 #endif 1129 return; 1130 1131 gotit: 1132 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1133 /* 1134 * Now we should have a complete message (1 byte, 2 byte 1135 * and moderately long extended messages). We only handle 1136 * extended messages which total length is shorter than 1137 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1138 */ 1139 if (sc->sc_state == SPC_HASNEXUS) { 1140 struct acb *acb = sc->sc_nexus; 1141 struct spc_tinfo *ti = 1142 &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1143 1144 switch (sc->sc_imess[0]) { 1145 case MSG_CMDCOMPLETE: 1146 SPC_MSGS(("cmdcomplete ")); 1147 if (sc->sc_dleft < 0) { 1148 struct scsipi_link *sc_link = acb->xs->sc_link; 1149 printf("mha: %d extra bytes from %d:%d\n", 1150 -sc->sc_dleft, 1151 sc_link->scsipi_scsi.target, 1152 sc_link->scsipi_scsi.lun); 1153 sc->sc_dleft = 0; 1154 } 1155 acb->xs->resid = acb->dleft = sc->sc_dleft; 1156 sc->sc_flags |= SPC_BUSFREE_OK; 1157 break; 1158 1159 case MSG_MESSAGE_REJECT: 1160 #if SPC_DEBUG 1161 if (mha_debug & SPC_SHOWMSGS) 1162 printf("%s: our msg rejected by target\n", 1163 sc->sc_dev.dv_xname); 1164 #endif 1165 #if 1 /* XXX - must remember last message */ 1166 scsi_print_addr(acb->xs->sc_link); printf("MSG_MESSAGE_REJECT>>"); 1167 #endif 1168 if (sc->sc_flags & SPC_SYNCHNEGO) { 1169 ti->period = ti->offset = 0; 1170 sc->sc_flags &= ~SPC_SYNCHNEGO; 1171 ti->flags &= ~T_NEGOTIATE; 1172 } 1173 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1174 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1175 mha_sched_msgout(SEND_ABORT); 1176 break; 1177 case MSG_NOOP: 1178 SPC_MSGS(("noop ")); 1179 break; 1180 case MSG_DISCONNECT: 1181 SPC_MSGS(("disconnect ")); 1182 ti->dconns++; 1183 sc->sc_flags |= SPC_DISCON; 1184 sc->sc_flags |= SPC_BUSFREE_OK; 1185 if ((acb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1186 break; 1187 /*FALLTHROUGH*/ 1188 case MSG_SAVEDATAPOINTER: 1189 SPC_MSGS(("save datapointer ")); 1190 acb->dleft = sc->sc_dleft; 1191 acb->daddr = sc->sc_dp; 1192 break; 1193 case MSG_RESTOREPOINTERS: 1194 SPC_MSGS(("restore datapointer ")); 1195 if (!acb) { 1196 mha_sched_msgout(SEND_ABORT); 1197 printf("%s: no DATAPOINTERs to restore\n", 1198 sc->sc_dev.dv_xname); 1199 break; 1200 } 1201 sc->sc_dp = acb->daddr; 1202 sc->sc_dleft = acb->dleft; 1203 break; 1204 case MSG_PARITY_ERROR: 1205 printf("%s:target%d: MSG_PARITY_ERROR\n", 1206 sc->sc_dev.dv_xname, 1207 acb->xs->sc_link->scsipi_scsi.target); 1208 break; 1209 case MSG_EXTENDED: 1210 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1211 switch (sc->sc_imess[2]) { 1212 case MSG_EXT_SDTR: 1213 SPC_MSGS(("SDTR period %d, offset %d ", 1214 sc->sc_imess[3], sc->sc_imess[4])); 1215 ti->period = sc->sc_imess[3]; 1216 ti->offset = sc->sc_imess[4]; 1217 if (sc->sc_minsync == 0) { 1218 /* We won't do synch */ 1219 ti->offset = 0; 1220 mha_sched_msgout(SEND_SDTR); 1221 } else if (ti->offset == 0) { 1222 printf("%s:%d: async\n", "mha", 1223 acb->xs->sc_link->scsipi_scsi.target); 1224 ti->offset = 0; 1225 sc->sc_flags &= ~SPC_SYNCHNEGO; 1226 } else if (ti->period > 124) { 1227 printf("%s:%d: async\n", "mha", 1228 acb->xs->sc_link->scsipi_scsi.target); 1229 ti->offset = 0; 1230 mha_sched_msgout(SEND_SDTR); 1231 } else { 1232 int r = 250/ti->period; 1233 int s = (100*250)/ti->period - 100*r; 1234 int p; 1235 #if 0 1236 p = mha_stp2cpb(sc, ti->period); 1237 ti->period = mha_cpb2stp(sc, p); 1238 #endif 1239 1240 #if SPC_DEBUG 1241 scsi_print_addr(acb->xs->sc_link); 1242 #endif 1243 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1244 /* Target initiated negotiation */ 1245 if (ti->flags & T_SYNCMODE) { 1246 ti->flags &= ~T_SYNCMODE; 1247 #if SPC_DEBUG 1248 printf("renegotiated "); 1249 #endif 1250 } 1251 TMR=TM_ASYNC; 1252 /* Clamp to our maxima */ 1253 if (ti->period < sc->sc_minsync) 1254 ti->period = sc->sc_minsync; 1255 if (ti->offset > 15) 1256 ti->offset = 15; 1257 mha_sched_msgout(SEND_SDTR); 1258 } else { 1259 /* we are sync */ 1260 sc->sc_flags &= ~SPC_SYNCHNEGO; 1261 TMR = TM_SYNC; 1262 ti->flags |= T_SYNCMODE; 1263 } 1264 #if SPC_DEBUG 1265 printf("max sync rate %d.%02dMb/s\n", 1266 r, s); 1267 #endif 1268 } 1269 ti->flags &= ~T_NEGOTIATE; 1270 break; 1271 default: /* Extended messages we don't handle */ 1272 CMR = CMD_SET_ATN; /* XXX? */ 1273 break; 1274 } 1275 break; 1276 default: 1277 SPC_MSGS(("ident ")); 1278 /* thanks for that ident... */ 1279 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1280 SPC_MISC(("unknown ")); 1281 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1282 CMR = CMD_SET_ATN; /* XXX? */ 1283 } 1284 break; 1285 } 1286 } else if (sc->sc_state == SPC_RESELECTED) { 1287 struct scsipi_link *sc_link = NULL; 1288 struct acb *acb; 1289 struct spc_tinfo *ti; 1290 u_char lunit; 1291 1292 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1293 SPC_MISC(("searching ")); 1294 /* 1295 * Search wait queue for disconnected cmd 1296 * The list should be short, so I haven't bothered with 1297 * any more sophisticated structures than a simple 1298 * singly linked list. 1299 */ 1300 lunit = sc->sc_imess[0] & 0x07; 1301 for (acb = sc->nexus_list.tqh_first; acb; 1302 acb = acb->chain.tqe_next) { 1303 sc_link = acb->xs->sc_link; 1304 if (sc_link->scsipi_scsi.lun == lunit && 1305 sc->sc_selid == (1<<sc_link->scsipi_scsi.target)) { 1306 TAILQ_REMOVE(&sc->nexus_list, acb, 1307 chain); 1308 ACB_SETQ(acb, ACB_QNONE); 1309 break; 1310 } 1311 } 1312 1313 if (!acb) { /* Invalid reselection! */ 1314 mha_sched_msgout(SEND_ABORT); 1315 printf("mmespc: invalid reselect (idbit=0x%2x)\n", 1316 sc->sc_selid); 1317 } else { /* Reestablish nexus */ 1318 /* 1319 * Setup driver data structures and 1320 * do an implicit RESTORE POINTERS 1321 */ 1322 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1323 sc->sc_nexus = acb; 1324 sc->sc_dp = acb->daddr; 1325 sc->sc_dleft = acb->dleft; 1326 sc->sc_tinfo[sc_link->scsipi_scsi.target].lubusy 1327 |= (1<<sc_link->scsipi_scsi.lun); 1328 if (ti->flags & T_SYNCMODE) { 1329 TMR = TM_SYNC; /* XXX */ 1330 } else { 1331 TMR = TM_ASYNC; 1332 } 1333 SPC_MISC(("... found acb")); 1334 sc->sc_state = SPC_HASNEXUS; 1335 } 1336 } else { 1337 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1338 sc->sc_dev.dv_xname, sc->sc_selid); 1339 mha_sched_msgout(SEND_DEV_RESET); 1340 } 1341 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1342 printf("%s: unexpected message in; will send DEV_RESET\n", 1343 sc->sc_dev.dv_xname); 1344 mha_sched_msgout(SEND_DEV_RESET); 1345 } 1346 1347 /* Ack last message byte */ 1348 #if 0 1349 ESPCMD(sc, ESPCMD_MSGOK); 1350 #endif 1351 1352 /* Done, reset message pointer. */ 1353 sc->sc_flags &= ~SPC_DROP_MSGI; 1354 sc->sc_imlen = 0; 1355 } 1356 1357 /* 1358 * Send the highest priority, scheduled message. 1359 */ 1360 void 1361 mha_msgout(sc) 1362 register struct mha_softc *sc; 1363 { 1364 struct spc_tinfo *ti; 1365 int n; 1366 1367 SPC_TRACE(("mha_msgout ")); 1368 1369 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1370 if (sc->sc_omp == sc->sc_omess) { 1371 /* 1372 * This is a retransmission. 1373 * 1374 * We get here if the target stayed in MESSAGE OUT 1375 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1376 * that all of the previously transmitted messages must 1377 * be sent again, in the same order. Therefore, we 1378 * requeue all the previously transmitted messages, and 1379 * start again from the top. Our simple priority 1380 * scheme keeps the messages in the right order. 1381 */ 1382 SPC_MISC(("retransmitting ")); 1383 sc->sc_msgpriq |= sc->sc_msgoutq; 1384 /* 1385 * Set ATN. If we're just sending a trivial 1-byte 1386 * message, we'll clear ATN later on anyway. 1387 */ 1388 CMR = CMD_SET_ATN; /* XXX? */ 1389 } else { 1390 /* This is a continuation of the previous message. */ 1391 n = sc->sc_omp - sc->sc_omess; 1392 goto nextbyte; 1393 } 1394 } 1395 1396 /* No messages transmitted so far. */ 1397 sc->sc_msgoutq = 0; 1398 sc->sc_lastmsg = 0; 1399 1400 nextmsg: 1401 /* Pick up highest priority message. */ 1402 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1403 sc->sc_msgpriq &= ~sc->sc_currmsg; 1404 sc->sc_msgoutq |= sc->sc_currmsg; 1405 1406 /* Build the outgoing message data. */ 1407 switch (sc->sc_currmsg) { 1408 case SEND_IDENTIFY: 1409 SPC_ASSERT(sc->sc_nexus != NULL); 1410 sc->sc_omess[0] = 1411 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1412 n = 1; 1413 break; 1414 1415 #if SPC_USE_SYNCHRONOUS 1416 case SEND_SDTR: 1417 SPC_ASSERT(sc->sc_nexus != NULL); 1418 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1419 sc->sc_omess[4] = MSG_EXTENDED; 1420 sc->sc_omess[3] = 3; 1421 sc->sc_omess[2] = MSG_EXT_SDTR; 1422 sc->sc_omess[1] = ti->period >> 2; 1423 sc->sc_omess[0] = ti->offset; 1424 n = 5; 1425 break; 1426 #endif 1427 1428 #if SPC_USE_WIDE 1429 case SEND_WDTR: 1430 SPC_ASSERT(sc->sc_nexus != NULL); 1431 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1432 sc->sc_omess[3] = MSG_EXTENDED; 1433 sc->sc_omess[2] = 2; 1434 sc->sc_omess[1] = MSG_EXT_WDTR; 1435 sc->sc_omess[0] = ti->width; 1436 n = 4; 1437 break; 1438 #endif 1439 1440 case SEND_DEV_RESET: 1441 sc->sc_flags |= SPC_ABORTING; 1442 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1443 n = 1; 1444 break; 1445 1446 case SEND_REJECT: 1447 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1448 n = 1; 1449 break; 1450 1451 case SEND_PARITY_ERROR: 1452 sc->sc_omess[0] = MSG_PARITY_ERROR; 1453 n = 1; 1454 break; 1455 1456 case SEND_INIT_DET_ERR: 1457 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1458 n = 1; 1459 break; 1460 1461 case SEND_ABORT: 1462 sc->sc_flags |= SPC_ABORTING; 1463 sc->sc_omess[0] = MSG_ABORT; 1464 n = 1; 1465 break; 1466 1467 default: 1468 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1469 sc->sc_dev.dv_xname); 1470 SPC_BREAK(); 1471 sc->sc_omess[0] = MSG_NOOP; 1472 n = 1; 1473 break; 1474 } 1475 sc->sc_omp = &sc->sc_omess[n]; 1476 1477 nextbyte: 1478 /* Send message bytes. */ 1479 /* send TRANSFER command. */ 1480 sc->sc_ps[3] = 1; 1481 sc->sc_ps[4] = n >> 8; 1482 sc->sc_pc[10] = n; 1483 sc->sc_ps[-1] = 0x000F; /* burst */ 1484 asm volatile ("nop"); 1485 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1486 for (;;) { 1487 if ((SSR & SS_BUSY) != 0) 1488 break; 1489 if (SSR & SS_IREQUEST) 1490 goto out; 1491 } 1492 for (;;) { 1493 #if 0 1494 for (;;) { 1495 if ((PSNS & PSNS_REQ) != 0) 1496 break; 1497 /* Wait for REQINIT. XXX Need timeout. */ 1498 } 1499 #endif 1500 if (SSR & SS_IREQUEST) { 1501 /* 1502 * Target left MESSAGE OUT, possibly to reject 1503 * our message. 1504 * 1505 * If this is the last message being sent, then we 1506 * deassert ATN, since either the target is going to 1507 * ignore this message, or it's going to ask for a 1508 * retransmission via MESSAGE PARITY ERROR (in which 1509 * case we reassert ATN anyway). 1510 */ 1511 #if 0 1512 if (sc->sc_msgpriq == 0) 1513 CMR = CMD_RESET_ATN; 1514 #endif 1515 goto out; 1516 } 1517 1518 #if 0 1519 /* Clear ATN before last byte if this is the last message. */ 1520 if (n == 1 && sc->sc_msgpriq == 0) 1521 CMR = CMD_RESET_ATN; 1522 #endif 1523 1524 while ((SSR & SS_DREG_FULL) != 0) 1525 ; 1526 /* Send message byte. */ 1527 sc->sc_pc[0] = *--sc->sc_omp; 1528 --n; 1529 /* Keep track of the last message we've sent any bytes of. */ 1530 sc->sc_lastmsg = sc->sc_currmsg; 1531 1532 if (n == 0) 1533 break; 1534 } 1535 1536 /* We get here only if the entire message has been transmitted. */ 1537 if (sc->sc_msgpriq != 0) { 1538 /* There are more outgoing messages. */ 1539 goto nextmsg; 1540 } 1541 1542 /* 1543 * The last message has been transmitted. We need to remember the last 1544 * message transmitted (in case the target switches to MESSAGE IN phase 1545 * and sends a MESSAGE REJECT), and the list of messages transmitted 1546 * this time around (in case the target stays in MESSAGE OUT phase to 1547 * request a retransmit). 1548 */ 1549 1550 out: 1551 /* Disable REQ/ACK protocol. */ 1552 } 1553 1554 1555 /*************************************************************** 1557 * 1558 * datain/dataout 1559 * 1560 */ 1561 1562 int 1563 mha_datain_pio(sc, p, n) 1564 register struct mha_softc *sc; 1565 u_char *p; 1566 int n; 1567 { 1568 u_short d; 1569 int a; 1570 int total_n = n; 1571 1572 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1573 1574 WAIT; 1575 sc->sc_ps[3] = 1; 1576 sc->sc_ps[4] = n >> 8; 1577 sc->sc_pc[10] = n; 1578 /* */ 1579 CMR = CMD_RECEIVE_TO_MPU; 1580 for (;;) { 1581 a = SSR; 1582 if (a & 0x04) { 1583 d = sc->sc_ps[0]; 1584 *p++ = d >> 8; 1585 if (--n > 0) { 1586 *p++ = d; 1587 --n; 1588 } 1589 a = SSR; 1590 } 1591 if (a & 0x40) 1592 continue; 1593 if (a & 0x80) 1594 break; 1595 } 1596 SPC_TRACE(("...%d resd]", n)); 1597 return total_n - n; 1598 } 1599 1600 int 1601 mha_dataout_pio(sc, p, n) 1602 register struct mha_softc *sc; 1603 u_char *p; 1604 int n; 1605 { 1606 u_short d; 1607 int a; 1608 int total_n = n; 1609 1610 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1611 1612 WAIT; 1613 sc->sc_ps[3] = 1; 1614 sc->sc_ps[4] = n >> 8; 1615 sc->sc_pc[10] = n; 1616 /* */ 1617 CMR = CMD_SEND_FROM_MPU; 1618 for (;;) { 1619 a = SSR; 1620 if (a & 0x04) { 1621 d = *p++ << 8; 1622 if (--n > 0) { 1623 d |= *p++; 1624 --n; 1625 } 1626 sc->sc_ps[0] = d; 1627 a = SSR; 1628 } 1629 if (a & 0x40) 1630 continue; 1631 if (a & 0x80) 1632 break; 1633 } 1634 SPC_TRACE(("...%d resd]", n)); 1635 return total_n - n; 1636 } 1637 1638 static int 1639 mha_dataio_dma(dw, cw, sc, p, n) 1640 int dw; /* DMA word */ 1641 int cw; /* CMR word */ 1642 register struct mha_softc *sc; 1643 u_char *p; 1644 int n; 1645 { 1646 int ts; 1647 char *paddr, *vaddr; 1648 1649 vaddr = p; 1650 paddr = (char *)kvtop(vaddr); 1651 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1652 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1653 dw &= ~(1 << 3); 1654 #endif 1655 #if defined(M68040) || defined(M68060) 1656 #if defined(M68020) || defined(M68030) 1657 if (mmutype == MMU_68040) 1658 #endif 1659 DCFP((paddr_t)paddr); /* XXX */ 1660 #endif 1661 for (ts = (NBPG - ((long)vaddr & PGOFSET)); 1662 ts < n && (char *)kvtop(vaddr + ts + 4) == paddr + ts + 4; 1663 ts += NBPG) 1664 #if defined(M68040) || defined(M68060) 1665 #if defined(M68020) || defined(M68030) 1666 if (mmutype == MMU_68040) 1667 #endif 1668 DCFP((paddr_t)paddr + ts); 1669 #else 1670 ; 1671 #endif 1672 if (ts > n) 1673 ts = n; 1674 #if 0 1675 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, ts); 1676 PCIA(); /* XXX */ 1677 #endif 1678 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1679 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1680 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1681 WAIT; 1682 sc->sc_ps[3] = 1; 1683 sc->sc_ps[4] = ts >> 8; 1684 sc->sc_pc[10] = ts; 1685 /* DMA 1686 3 ... short bus cycle 1687 2 ... MAXIMUM XFER. 1688 1 ... BURST XFER. 1689 0 ... R/W */ 1690 sc->sc_ps[-1] = dw; /* burst */ 1691 asm volatile ("nop"); 1692 CMR = cw; /* receive to DMA */ 1693 return ts; 1694 } 1695 int 1696 mha_dataout(sc, p, n) 1697 register struct mha_softc *sc; 1698 u_char *p; 1699 int n; 1700 { 1701 register struct acb *acb = sc->sc_nexus; 1702 1703 if (n == 0) 1704 return n; 1705 1706 if (((long)p & 1) || (n & 1)) 1707 return mha_dataout_pio(sc, p, n); 1708 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1709 } 1710 1711 int 1713 mha_datain(sc, p, n) 1714 register struct mha_softc *sc; 1715 u_char *p; 1716 int n; 1717 { 1718 int ts; 1719 register struct acb *acb = sc->sc_nexus; 1720 char *paddr, *vaddr; 1721 1722 if (n == 0) 1723 return n; 1724 if (acb->cmd.opcode == 0x03 || ((long)p & 1) || (n & 1)) 1725 return mha_datain_pio(sc, p, n); 1726 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1727 } 1728 1729 1731 /* 1732 * Catch an interrupt from the adaptor 1733 */ 1734 /* 1735 * This is the workhorse routine of the driver. 1736 * Deficiencies (for now): 1737 * 1) always uses programmed I/O 1738 */ 1739 int 1740 mhaintr(arg) 1741 void *arg; 1742 { 1743 struct mha_softc *sc = arg; 1744 u_char ints; 1745 struct acb *acb; 1746 struct scsipi_link *sc_link; 1747 struct spc_tinfo *ti; 1748 u_char ph; 1749 u_short r; 1750 int n; 1751 1752 #if 1 /* XXX called during attach? */ 1753 if (tmpsc != NULL) { 1754 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1755 sc = tmpsc; 1756 } else { 1757 #endif 1758 1759 #if 1 /* XXX */ 1760 } 1761 #endif 1762 1763 /* 1764 * 1765 */ 1766 #if 0 1767 SCTL &= ~SCTL_INTR_ENAB; 1768 #endif 1769 1770 SPC_TRACE(("[mhaintr]")); 1771 1772 loop: 1773 /* 1774 * 1775 */ 1776 /* 1777 * First check for abnormal conditions, such as reset. 1778 */ 1779 #if 0 1780 #if 1 /* XXX? */ 1781 while (((ints = SSR) & SS_IREQUEST) == 0) 1782 delay(1); 1783 SPC_MISC(("ints = 0x%x ", ints)); 1784 #else /* usually? */ 1785 ints = SSR; 1786 #endif 1787 #endif 1788 while (SSR & SS_IREQUEST) 1789 { 1790 acb = sc->sc_nexus; 1791 r = ISCSR; 1792 SPC_MISC(("[r=0x%x]", r)); 1793 switch (r >> 8) 1794 { 1795 default: 1796 printf("[addr=%x\n" 1797 "result=0x%x\n" 1798 "cmd=0x%x\n" 1799 "ph=0x%x(ought to be %d)]\n", 1800 &ISCSR, 1801 r, 1802 acb->xs->cmd->opcode, 1803 SCR, sc->sc_phase); 1804 panic("unexpected result."); 1805 case 0x82: /* selection timeout */ 1806 SPC_MISC(("selection timeout ")); 1807 sc->sc_phase = BUSFREE_PHASE; 1808 SPC_ASSERT(sc->sc_nexus != NULL); 1809 acb = sc->sc_nexus; 1810 delay(250); 1811 acb->xs->error = XS_SELTIMEOUT; 1812 mha_done(sc, acb); 1813 continue; /* XXX ??? msaitoh */ 1814 case 0x60: /* command completed */ 1815 sc->sc_spcinitialized++; 1816 if (sc->sc_phase == BUSFREE_PHASE) 1817 continue; 1818 ph = SCR; 1819 if (ph & PSNS_ACK) 1820 { 1821 int s; 1822 /* */ 1823 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", ph & PHASE_MASK, sc->sc_phase)); 1824 # if 0 1825 switch (sc->sc_phase) 1826 #else 1827 switch (ph & PHASE_MASK) 1828 #endif 1829 { 1830 case STATUS_PHASE: 1831 if (sc->sc_state != SPC_HASNEXUS) 1832 { 1833 printf("stsin: !SPC_HASNEXUS->(%d)\n", sc->sc_state); 1834 } 1835 SPC_ASSERT(sc->sc_nexus != NULL); 1836 acb = sc->sc_nexus; 1837 WAIT; 1838 s = MBR; 1839 SPC_ASSERT(s == 1); 1840 acb->stat = sc->sc_pcx[0]; /* XXX */ 1841 SPC_MISC(("stat=0x%02x ", acb->stat)); 1842 sc->sc_prevphase = STATUS_PHASE; 1843 break; 1844 case MESSAGE_IN_PHASE: 1845 mha_msgin(sc); 1846 sc->sc_prevphase = MESSAGE_IN_PHASE; 1847 break; 1848 } 1849 WAIT; 1850 CMR = CMD_RESET_ACK; /* reset ack */ 1851 /*mha_done(sc, acb); XXX */ 1852 continue; 1853 } 1854 else if (NSR & 0x80) /* nexus */ 1855 { 1856 #if 1 1857 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1858 sc->sc_state = SPC_HASNEXUS; 1859 /* 1860 initial-phase error(0x54) 1861 1862 0x65 ? */ 1863 WAIT; 1864 if (SSR & SS_IREQUEST) 1865 continue; 1866 switch (sc->sc_phase) 1867 { 1868 default: 1869 panic(" phase "); 1870 case MESSAGE_IN_PHASE: 1871 /* */ 1872 continue; 1873 case STATUS_PHASE: 1874 sc->sc_phase = MESSAGE_IN_PHASE; 1875 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1876 continue; 1877 case DATA_IN_PHASE: 1878 sc->sc_prevphase = DATA_IN_PHASE; 1879 if (sc->sc_dleft == 0) 1880 { 1881 /* 1882 */ 1883 sc->sc_phase = STATUS_PHASE; 1884 CMR = CMD_RECEIVE_STS; /* receive sts */ 1885 continue; 1886 } 1887 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1888 sc->sc_dp += n; 1889 sc->sc_dleft -= n; 1890 continue; 1891 case DATA_OUT_PHASE: 1892 sc->sc_prevphase = DATA_OUT_PHASE; 1893 if (sc->sc_dleft == 0) 1894 { 1895 /* 1896 */ 1897 sc->sc_phase = STATUS_PHASE; 1898 CMR = CMD_RECEIVE_STS; /* receive sts */ 1899 continue; 1900 } 1901 /* data phase */ 1902 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1903 sc->sc_dp += n; 1904 sc->sc_dleft -= n; 1905 continue; 1906 case COMMAND_PHASE: 1907 /* CMD PHASE */ 1908 if (acb->dleft) 1909 { 1910 /* */ 1911 if (acb->xs->flags & SCSI_DATA_IN) 1912 { 1913 sc->sc_phase = DATA_IN_PHASE; 1914 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1915 sc->sc_dp += n; 1916 sc->sc_dleft -= n; 1917 } 1918 else if (acb->xs->flags & SCSI_DATA_OUT) 1919 { 1920 sc->sc_phase = DATA_OUT_PHASE; 1921 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1922 sc->sc_dp += n; 1923 sc->sc_dleft -= n; 1924 } 1925 continue; 1926 } 1927 else 1928 { 1929 /* ?! */ 1930 WAIT; 1931 sc->sc_phase = STATUS_PHASE; 1932 CMR = CMD_RECEIVE_STS; /* receive sts */ 1933 continue; 1934 } 1935 } 1936 #endif 1937 } 1938 continue; 1939 case 0x31: /* disconnected in xfer progress. */ 1940 SPC_MISC(("[0x31]")); 1941 case 0x70: /* disconnected. */ 1942 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1943 sc->sc_phase = BUSFREE_PHASE; 1944 sc->sc_state = SPC_IDLE; 1945 #if 1 1946 acb = sc->sc_nexus; 1947 SPC_ASSERT(sc->sc_nexus != NULL); 1948 acb->xs->error = XS_NOERROR; 1949 mha_done(sc, acb); 1950 #else 1951 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1952 mha_sched(sc); 1953 #endif 1954 continue; 1955 case 0x32: /* phase error in xfer progress. */ 1956 SPC_MISC(("[0x32]")); 1957 case 0x65: /* invalid command. 1958 1959 */ 1960 #if 1 1961 SPC_MISC(("[0x%04x]", r)); 1962 #endif 1963 case 0x54: /* initial-phase error. */ 1964 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1965 NSR, 1966 SCR, sc->sc_phase)); 1967 /* thru */ 1968 case 0x71: /* assert req */ 1969 WAIT; 1970 if (SSR & 0x40) 1971 { 1972 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1973 SSR, r, NSR, SCR); 1974 WAIT; 1975 } 1976 ph = SCR; 1977 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1978 { 1979 sc->sc_state = SPC_HASNEXUS; 1980 } 1981 if (ph & 0x80) 1982 { 1983 switch (ph & PHASE_MASK) 1984 { 1985 default: 1986 printf("phase = %x\n", ph); 1987 panic("assert req: the phase I don't know!"); 1988 case DATA_IN_PHASE: 1989 sc->sc_prevphase = DATA_IN_PHASE; 1990 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1991 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1992 sc->sc_dp += n; 1993 sc->sc_dleft -= n; 1994 SPC_MISC(("done\n")); 1995 continue; 1996 case DATA_OUT_PHASE: 1997 sc->sc_prevphase = DATA_OUT_PHASE; 1998 SPC_MISC(("DATAOUT\n")); 1999 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 2000 sc->sc_dp += n; 2001 sc->sc_dleft -= n; 2002 continue; 2003 case STATUS_PHASE: 2004 sc->sc_phase = STATUS_PHASE; 2005 SPC_MISC(("[RECV_STS]")); 2006 WAIT; 2007 CMR = CMD_RECEIVE_STS; /* receive sts */ 2008 continue; 2009 case MESSAGE_IN_PHASE: 2010 sc->sc_phase = MESSAGE_IN_PHASE; 2011 WAIT; 2012 CMR = CMD_RECEIVE_MSG; 2013 continue; 2014 } 2015 } 2016 continue; 2017 } 2018 } 2019 } 2020 2021 void 2022 mha_abort(sc, acb) 2023 struct mha_softc *sc; 2024 struct acb *acb; 2025 { 2026 acb->flags |= ACB_ABORTED; 2027 2028 if (acb == sc->sc_nexus) { 2029 /* 2030 * If we're still selecting, the message will be scheduled 2031 * after selection is complete. 2032 */ 2033 if (sc->sc_state == SPC_HASNEXUS) { 2034 sc->sc_flags |= SPC_ABORTING; 2035 mha_sched_msgout(SEND_ABORT); 2036 } 2037 } else { 2038 if (sc->sc_state == SPC_IDLE) 2039 mha_sched(sc); 2040 } 2041 } 2042 2043 void 2044 mha_timeout(arg) 2045 void *arg; 2046 { 2047 int s = splbio(); 2048 struct acb *acb = (struct acb *)arg; 2049 struct scsipi_xfer *xs = acb->xs; 2050 struct scsipi_link *sc_link = xs->sc_link; 2051 struct mha_softc *sc = sc_link->adapter_softc; 2052 2053 scsi_print_addr(sc_link); 2054 again: 2055 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2056 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2057 sc->sc_dev.dv_xname, 2058 acb, acb->flags, acb->dleft, acb->stat, 2059 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2060 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2061 ); 2062 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2063 panic("timeout, ouch!"); 2064 2065 if (acb->flags & ACB_ABORTED) { 2066 /* abort timed out */ 2067 printf(" AGAIN\n"); 2068 #if 0 2069 mha_init(sc, 1); /* XXX 1?*/ 2070 #endif 2071 } else { 2072 /* abort the operation that has timed out */ 2073 printf("\n"); 2074 xs->error = XS_TIMEOUT; 2075 mha_abort(sc, acb); 2076 } 2077 2078 splx(s); 2079 } 2080 2081 #if SPC_DEBUG 2083 /* 2084 * The following functions are mostly used for debugging purposes, either 2085 * directly called from the driver or from the kernel debugger. 2086 */ 2087 2088 void 2089 mha_show_scsi_cmd(acb) 2090 struct acb *acb; 2091 { 2092 u_char *b = (u_char *)&acb->cmd; 2093 struct scsipi_link *sc_link = acb->xs->sc_link; 2094 int i; 2095 2096 scsi_print_addr(sc_link); 2097 if ((acb->xs->flags & SCSI_RESET) == 0) { 2098 for (i = 0; i < acb->clen; i++) { 2099 if (i) 2100 printf(","); 2101 printf("%x", b[i]); 2102 } 2103 printf("\n"); 2104 } else 2105 printf("RESET\n"); 2106 } 2107 2108 void 2109 mha_print_acb(acb) 2110 struct acb *acb; 2111 { 2112 2113 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2114 printf(" dp=%x dleft=%d stat=%x\n", 2115 (long)acb->daddr, acb->dleft, acb->stat); 2116 mha_show_scsi_cmd(acb); 2117 } 2118 2119 void 2120 mha_print_active_acb() 2121 { 2122 struct acb *acb; 2123 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2124 2125 printf("ready list:\n"); 2126 for (acb = sc->ready_list.tqh_first; acb != NULL; 2127 acb = acb->chain.tqe_next) 2128 mha_print_acb(acb); 2129 printf("nexus:\n"); 2130 if (sc->sc_nexus != NULL) 2131 mha_print_acb(sc->sc_nexus); 2132 printf("nexus list:\n"); 2133 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2134 acb = acb->chain.tqe_next) 2135 mha_print_acb(acb); 2136 } 2137 2138 void 2139 mha_dump_driver(sc) 2140 struct mha_softc *sc; 2141 { 2142 struct spc_tinfo *ti; 2143 int i; 2144 2145 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2146 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2147 sc->sc_state, sc->sc_imess[0], 2148 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2149 for (i = 0; i < 7; i++) { 2150 ti = &sc->sc_tinfo[i]; 2151 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2152 i, ti->cmds, ti->dconns, ti->touts); 2153 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2154 } 2155 } 2156 #endif 2157
Indexes created Mon Oct 20 20:10:13 GMT 2025