mha.c revision 1.14
1 /* $NetBSD: mha.c,v 1.14 1999/03/22 08:54:14 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 39 /*- 40 * Copyright (c) 1994 Jarle Greipsland 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 56 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 57 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 63 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 #include "opt_ddb.h" 68 69 /* Synchronous data transfers? */ 70 #define SPC_USE_SYNCHRONOUS 0 71 #define SPC_SYNC_REQ_ACK_OFS 8 72 73 /* Default DMA mode? */ 74 #define MHA_DMA_LIMIT_XFER 1 75 #define MHA_DMA_BURST_XFER 1 76 #define MHA_DMA_SHORT_BUS_CYCLE 1 77 78 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 79 | (MHA_DMA_BURST_XFER << 2) \ 80 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 81 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 82 | (MHA_DMA_BURST_XFER << 2) \ 83 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 84 85 /* Include debug functions? At the end of this file there are a bunch of 86 * functions that will print out various information regarding queued SCSI 87 * commands, driver state and chip contents. You can call them from the 88 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 89 * kernel uses less memory) but you lose the debugging facilities. 90 */ 91 #define SPC_DEBUG 0 92 93 /* End of customizable parameters */ 94 95 /* 96 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 97 */ 98 99 #include <sys/types.h> 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/kernel.h> 103 #include <sys/errno.h> 104 #include <sys/ioctl.h> 105 #include <sys/device.h> 106 #include <sys/buf.h> 107 #include <sys/proc.h> 108 #include <sys/user.h> 109 #include <sys/queue.h> 110 111 #include <machine/bus.h> 112 113 #include <dev/scsipi/scsi_all.h> 114 #include <dev/scsipi/scsipi_all.h> 115 #include <dev/scsipi/scsi_message.h> 116 #include <dev/scsipi/scsiconf.h> 117 118 #include <x68k/x68k/iodevice.h> 119 #include <x68k/dev/mb86601reg.h> 120 #include <x68k/dev/mhavar.h> 121 #include <x68k/dev/intiovar.h> 122 #include <x68k/dev/scsiromvar.h> 123 124 #if 0 125 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 126 #else 127 #define WAIT {while (sc->sc_pc[2] & 0x40);} 128 #endif 129 130 #define SSR (sc->sc_pc[2]) 131 #define SS_IREQUEST 0x80 132 #define SS_BUSY 0x40 133 #define SS_DREG_FULL 0x02 134 135 #define NSR (sc->sc_pc[3]) 136 137 #define SIR (sc->sc_pc[4]) 138 139 #define CMR (sc->sc_pc[5]) 140 #define CMD_SEL_AND_CMD 0x00 141 #define CMD_SELECT 0x09 142 #define CMD_SET_ATN 0x0a 143 #define CMD_RESET_ATN 0x0b 144 #define CMD_RESET_ACK 0x0d 145 #define CMD_SEND_FROM_MPU 0x10 146 #define CMD_SEND_FROM_DMA 0x11 147 #define CMD_RECEIVE_TO_MPU 0x12 148 #define CMD_RECEIVE_TO_DMA 0x13 149 #define CMD_RECEIVE_MSG 0x1a 150 #define CMD_RECEIVE_STS 0x1c 151 #define CMD_SOFT_RESET 0x40 152 #define CMD_SCSI_RESET 0x42 153 #define CMD_SET_UP_REG 0x43 154 155 #define SCR (sc->sc_pc[11]) 156 157 #define TMR (sc->sc_pc[12]) 158 #define TM_SYNC 0x80 159 #define TM_ASYNC 0x00 160 161 #define WAR (sc->sc_pc[15]) 162 #define WA_MCSBUFWIN 0x00 163 #define WA_UPMWIN 0x80 164 #define WA_INITWIN 0xc0 165 166 #define MBR (sc->sc_pc[15]) 167 168 #define ISCSR (sc->sc_ps[2]) 169 170 #define CCR (sc->sc_pcx[0]) 171 #define OIR (sc->sc_pcx[1]) 172 #define AMR (sc->sc_pcx[2]) 173 #define SMR (sc->sc_pcx[3]) 174 #define SRR (sc->sc_pcx[4]) 175 #define STR (sc->sc_pcx[5]) 176 #define RTR (sc->sc_pcx[6]) 177 #define ATR (sc->sc_pcx[7]) 178 #define PER (sc->sc_pcx[8]) 179 #define IER (sc->sc_pcx[9]) 180 #define IE_ALL 0xBF 181 182 #define GLR (sc->sc_pcx[10]) 183 #define DMR (sc->sc_pcx[11]) 184 #define IMR (sc->sc_pcx[12]) 185 186 187 #ifndef DDB 189 #define Debugger() panic("should call debugger here (mha.c)") 190 #endif /* ! DDB */ 191 192 193 #if SPC_DEBUG 194 #define SPC_SHOWACBS 0x01 195 #define SPC_SHOWINTS 0x02 196 #define SPC_SHOWCMDS 0x04 197 #define SPC_SHOWMISC 0x08 198 #define SPC_SHOWTRAC 0x10 199 #define SPC_SHOWSTART 0x20 200 #define SPC_SHOWPHASE 0x40 201 #define SPC_SHOWDMA 0x80 202 #define SPC_SHOWCCMDS 0x100 203 #define SPC_SHOWMSGS 0x200 204 #define SPC_DOBREAK 0x400 205 206 int mha_debug = 207 #if 0 208 0x7FF; 209 #else 210 SPC_SHOWSTART|SPC_SHOWTRAC; 211 #endif 212 213 214 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 215 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 216 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 217 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 218 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 219 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 220 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 221 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 222 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 223 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 224 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 225 #else 226 #define SPC_ACBS(str) 227 #define SPC_MISC(str) 228 #define SPC_INTS(str) 229 #define SPC_TRACE(str) 230 #define SPC_CMDS(str) 231 #define SPC_START(str) 232 #define SPC_PHASE(str) 233 #define SPC_DMA(str) 234 #define SPC_MSGS(str) 235 #define SPC_BREAK() 236 #define SPC_ASSERT(x) 237 #endif 238 239 int mhamatch __P((struct device *, struct cfdata *, void *)); 240 void mhaattach __P((struct device *, struct device *, void *)); 241 void mhaselect __P((struct mha_softc *, 242 u_char, u_char, u_char *, u_char)); 243 void mha_scsi_reset __P((struct mha_softc *)); 244 void mha_reset __P((struct mha_softc *)); 245 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 246 void mha_sense __P((struct mha_softc *, struct acb *)); 247 void mha_msgin __P((struct mha_softc *)); 248 void mha_msgout __P((struct mha_softc *)); 249 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 250 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_dataout __P((struct mha_softc *, u_char *, int)); 252 int mha_datain __P((struct mha_softc *, u_char *, int)); 253 void mha_abort __P((struct mha_softc *, struct acb *)); 254 void mha_init __P((struct mha_softc *)); 255 int mha_scsi_cmd __P((struct scsipi_xfer *)); 256 int mha_poll __P((struct mha_softc *, struct acb *)); 257 void mha_sched __P((struct mha_softc *)); 258 void mha_done __P((struct mha_softc *, struct acb *)); 259 int mhaintr __P((void*)); 260 void mha_timeout __P((void *)); 261 void mha_minphys __P((struct buf *)); 262 void mha_dequeue __P((struct mha_softc *, struct acb *)); 263 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 264 #if SPC_DEBUG 265 void mha_print_acb __P((struct acb *)); 266 void mha_show_scsi_cmd __P((struct acb *)); 267 void mha_print_active_acb __P((void)); 268 void mha_dump_driver __P((struct mha_softc *)); 269 #endif 270 271 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 272 273 struct cfattach mha_ca = { 274 sizeof(struct mha_softc), mhamatch, mhaattach 275 }; 276 277 extern struct cfdriver mha_cd; 278 279 struct scsipi_device mha_dev = { 280 NULL, /* Use default error handler */ 281 NULL, /* have a queue, served by this */ 282 NULL, /* have no async handler */ 283 NULL, /* Use default 'done' routine */ 284 }; 285 286 /* 288 * returns non-zero value if a controller is found. 289 */ 290 int 291 mhamatch(parent, cf, aux) 292 struct device *parent; 293 struct cfdata *cf; 294 void *aux; 295 { 296 struct intio_attach_args *ia = aux; 297 bus_space_tag_t iot = ia->ia_bst; 298 bus_space_handle_t ioh; 299 300 ia->ia_size=0x20; 301 if (ia->ia_addr != 0xea0000) 302 return 0; 303 304 if (intio_map_allocate_region(parent->dv_parent, ia, 305 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 306 return 0; 307 308 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 309 &ioh) < 0) 310 return 0; 311 if (!badaddr (INTIO_ADDR(ia->ia_addr + 0))) 312 return 0; 313 bus_space_unmap(iot, ioh, 0x20); 314 315 return 1; 316 } 317 318 /* 319 */ 320 321 struct mha_softc *tmpsc; 322 323 void 324 mhaattach(parent, self, aux) 325 struct device *parent, *self; 326 void *aux; 327 { 328 struct mha_softc *sc = (void *)self; 329 struct intio_attach_args *ia = aux; 330 331 tmpsc = sc; /* XXX */ 332 333 SPC_TRACE(("mhaattach ")); 334 sc->sc_state = SPC_INIT; 335 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 336 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 337 /* XXX: FAKE */ 338 sc->sc_dmat = ia->ia_dmat; 339 340 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 341 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 342 sc->sc_pcx = &sc->sc_pc[0x10]; 343 344 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 345 346 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 347 348 mha_init(sc); /* Init chip and driver */ 349 350 printf("\n%s: Resetting SCSI bus... ", self->dv_xname); 351 mha_scsi_reset(sc); /* XXX: some devices need this. */ 352 printf("done\n"); 353 354 sc->sc_phase = BUSFREE_PHASE; 355 356 /* 357 * Fill in the adapter. 358 */ 359 sc->sc_adapter.scsipi_cmd = mha_scsi_cmd; 360 sc->sc_adapter.scsipi_minphys = mha_minphys; 361 362 /* 363 * Fill in the prototype scsi_link 364 */ 365 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 366 sc->sc_link.adapter_softc = sc; 367 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 368 sc->sc_link.adapter = &sc->sc_adapter; 369 sc->sc_link.device = &mha_dev; 370 sc->sc_link.openings = 2; 371 sc->sc_link.scsipi_scsi.max_target = 7; 372 sc->sc_link.scsipi_scsi.max_lun = 7; 373 sc->sc_link.type = BUS_SCSI; 374 375 sc->sc_spcinitialized = 0; 376 WAR = WA_INITWIN; 377 #if 1 378 CCR = 0x14; 379 OIR = sc->sc_id; 380 AMR = 0x00; 381 SMR = 0x00; 382 SRR = 0x00; 383 STR = 0x20; 384 RTR = 0x40; 385 ATR = 0x01; 386 PER = 0xc9; 387 #endif 388 IER = IE_ALL; /* */ 389 #if 1 390 GLR = 0x00; 391 DMR = 0x30; 392 IMR = 0x00; 393 #endif 394 WAR = WA_MCSBUFWIN; 395 396 /* drop off */ 397 while (SSR & SS_IREQUEST) 398 { 399 unsigned a = ISCSR; 400 } 401 402 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 403 404 SPC_TRACE(("waiting for intr...")); 405 while (!(SSR & SS_IREQUEST)) 406 delay(10); 407 mhaintr (sc); 408 409 tmpsc = NULL; 410 411 config_found(self, &sc->sc_link, scsiprint); 412 } 413 414 #if 0 415 void 416 mha_reset(sc) 417 struct mha_softc *sc; 418 { 419 u_short dummy; 420 printf("reset..."); 421 CMR = CMD_SOFT_RESET; 422 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 423 dummy = sc->sc_ps[-1]; 424 dummy = sc->sc_ps[-1]; 425 dummy = sc->sc_ps[-1]; 426 dummy = sc->sc_ps[-1]; 427 asm volatile ("nop"); 428 CMR = CMD_SOFT_RESET; 429 sc->sc_spcinitialized = 0; 430 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 431 while(!sc->sc_spcinitialized); 432 433 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 434 printf("done.\n"); 435 } 436 #endif 437 438 /* 439 * Pull the SCSI RST line for 500us. 440 */ 441 void 442 mha_scsi_reset(sc) /* FINISH? */ 443 struct mha_softc *sc; 444 { 445 446 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 447 while (!(SSR&SS_IREQUEST)) 448 delay(10); 449 } 450 451 /* 452 * Initialize mha SCSI driver. 453 */ 454 void 455 mha_init(sc) 456 struct mha_softc *sc; 457 { 458 struct acb *acb; 459 int r; 460 461 if (sc->sc_state == SPC_INIT) { 462 /* First time through; initialize. */ 463 TAILQ_INIT(&sc->ready_list); 464 TAILQ_INIT(&sc->nexus_list); 465 TAILQ_INIT(&sc->free_list); 466 sc->sc_nexus = NULL; 467 acb = sc->sc_acb; 468 bzero(acb, sizeof(sc->sc_acb)); 469 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 470 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 471 acb++; 472 } 473 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 474 475 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 476 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 477 BUS_DMA_NOWAIT); 478 if (r) 479 panic("mha_init: cannot allocate dma memory"); 480 if (sc->sc_ndmasegs != 1) 481 panic("mha_init: number of segment > 1??"); 482 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 483 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 484 if (r) 485 panic("mha_init: cannot map dma memory"); 486 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 487 MAXBSIZE, 0, BUS_DMA_NOWAIT, 488 &sc->sc_dmamap); 489 if (r) 490 panic("mha_init: cannot create dmamap structure"); 491 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 492 sc->sc_dmabuf, MAXBSIZE, NULL, 493 BUS_DMA_NOWAIT); 494 if (r) 495 panic("mha_init: cannot load dma buffer into dmamap"); 496 sc->sc_p = 0; 497 } else { 498 /* Cancel any active commands. */ 499 sc->sc_flags |= SPC_ABORTING; 500 sc->sc_state = SPC_IDLE; 501 if ((acb = sc->sc_nexus) != NULL) { 502 acb->xs->error = XS_DRIVER_STUFFUP; 503 mha_done(sc, acb); 504 } 505 while ((acb = sc->nexus_list.tqh_first) != NULL) { 506 acb->xs->error = XS_DRIVER_STUFFUP; 507 mha_done(sc, acb); 508 } 509 } 510 511 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 512 for (r = 0; r < 8; r++) { 513 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 514 515 ti->flags = 0; 516 #if SPC_USE_SYNCHRONOUS 517 ti->flags |= T_SYNCMODE; 518 ti->period = sc->sc_minsync; 519 ti->offset = SPC_SYNC_REQ_ACK_OFS; 520 #else 521 ti->period = ti->offset = 0; 522 #endif 523 ti->width = 0; 524 } 525 526 sc->sc_state = SPC_IDLE; 527 } 528 529 void 530 mha_free_acb(sc, acb, flags) 531 struct mha_softc *sc; 532 struct acb *acb; 533 int flags; 534 { 535 int s; 536 537 s = splbio(); 538 539 acb->flags = 0; 540 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 541 542 /* 543 * If there were none, wake anybody waiting for one to come free, 544 * starting with queued entries. 545 */ 546 if (acb->chain.tqe_next == 0) 547 wakeup(&sc->free_list); 548 549 splx(s); 550 } 551 552 553 /* 555 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 556 */ 557 558 /* 559 * Expected sequence: 560 * 1) Command inserted into ready list 561 * 2) Command selected for execution 562 * 3) Command won arbitration and has selected target device 563 * 4) Send message out (identify message, eventually also sync.negotiations) 564 * 5) Send command 565 * 5a) Receive disconnect message, disconnect. 566 * 5b) Reselected by target 567 * 5c) Receive identify message from target. 568 * 6) Send or receive data 569 * 7) Receive status 570 * 8) Receive message (command complete etc.) 571 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 572 * Repeat 2-8 (no disconnects please...) 573 */ 574 575 /* 576 * Start a selection. This is used by mha_sched() to select an idle target, 577 * and by mha_done() to immediately reselect a target to get sense information. 578 */ 579 void 580 mhaselect(sc, target, lun, cmd, clen) 581 struct mha_softc *sc; 582 u_char target, lun; 583 u_char *cmd; 584 u_char clen; 585 { 586 #if 0 587 struct scsi_link *sc_link = acb->xs->sc_link; 588 #endif 589 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 590 int i; 591 int s; 592 593 s = splbio(); /* XXX */ 594 595 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 596 597 /* CDB SPC MCS REG */ 598 /* Now the command into the FIFO */ 599 WAIT; 600 #if 1 601 SPC_MISC(("[cmd:")); 602 for (i = 0; i < clen; i++) 603 { 604 unsigned c = cmd[i]; 605 if (i == 1) 606 c |= lun << 5; 607 SPC_MISC((" %02x", c)); 608 sc->sc_pcx[i] = c; 609 } 610 SPC_MISC(("], target=%d\n", target)); 611 #else 612 bcopy(cmd, sc->sc_pcx, clen); 613 #endif 614 if (NSR & 0x80) 615 panic("scsistart: already selected..."); 616 sc->sc_phase = COMMAND_PHASE; 617 618 /* new state ASP_SELECTING */ 619 sc->sc_state = SPC_SELECTING; 620 621 SIR = target; 622 #if 0 623 CMR = CMD_SELECT; 624 #else 625 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 626 #endif 627 splx(s); 628 } 629 630 #if 0 631 int 632 mha_reselect(sc, message) 633 struct mha_softc *sc; 634 u_char message; 635 { 636 u_char selid, target, lun; 637 struct acb *acb; 638 struct scsipi_link *sc_link; 639 struct spc_tinfo *ti; 640 641 /* 642 * The SCSI chip made a snapshot of the data bus while the reselection 643 * was being negotiated. This enables us to determine which target did 644 * the reselect. 645 */ 646 selid = sc->sc_selid & ~(1 << sc->sc_id); 647 if (selid & (selid - 1)) { 648 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 649 sc->sc_dev.dv_xname, selid); 650 SPC_BREAK(); 651 goto reset; 652 } 653 654 /* 655 * Search wait queue for disconnected cmd 656 * The list should be short, so I haven't bothered with 657 * any more sophisticated structures than a simple 658 * singly linked list. 659 */ 660 target = ffs(selid) - 1; 661 lun = message & 0x07; 662 for (acb = sc->nexus_list.tqh_first; acb != NULL; 663 acb = acb->chain.tqe_next) { 664 sc_link = acb->xs->sc_link; 665 if (sc_link->scsipi_scsi.target == target && 666 sc_link->scsipi_scsi.lun == lun) 667 break; 668 } 669 if (acb == NULL) { 670 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 671 sc->sc_dev.dv_xname, target, lun); 672 SPC_BREAK(); 673 goto abort; 674 } 675 676 /* Make this nexus active again. */ 677 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 678 sc->sc_state = SPC_HASNEXUS; 679 sc->sc_nexus = acb; 680 ti = &sc->sc_tinfo[target]; 681 ti->lubusy |= (1 << lun); 682 mha_setsync(sc, ti); 683 684 if (acb->flags & ACB_RESET) 685 mha_sched_msgout(sc, SEND_DEV_RESET); 686 else if (acb->flags & ACB_ABORTED) 687 mha_sched_msgout(sc, SEND_ABORT); 688 689 /* Do an implicit RESTORE POINTERS. */ 690 sc->sc_dp = acb->daddr; 691 sc->sc_dleft = acb->dleft; 692 sc->sc_cp = (u_char *)&acb->cmd; 693 sc->sc_cleft = acb->clen; 694 695 return (0); 696 697 reset: 698 mha_sched_msgout(sc, SEND_DEV_RESET); 699 return (1); 700 701 abort: 702 mha_sched_msgout(sc, SEND_ABORT); 703 return (1); 704 } 705 #endif 706 /* 707 * Start a SCSI-command 708 * This function is called by the higher level SCSI-driver to queue/run 709 * SCSI-commands. 710 */ 711 int 712 mha_scsi_cmd(xs) 713 struct scsipi_xfer *xs; 714 { 715 struct scsipi_link *sc_link = xs->sc_link; 716 struct mha_softc *sc = sc_link->adapter_softc; 717 struct acb *acb; 718 int s, flags; 719 720 SPC_TRACE(("[mha_scsi_cmd] ")); 721 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 722 sc_link->scsipi_scsi.target)); 723 724 flags = xs->flags; 725 726 /* Get a mha command block */ 727 s = splbio(); 728 acb = sc->free_list.tqh_first; 729 if (acb) { 730 TAILQ_REMOVE(&sc->free_list, acb, chain); 731 ACB_SETQ(acb, ACB_QNONE); 732 } 733 splx(s); 734 735 if (acb == NULL) { 736 SPC_MISC(("TRY_AGAIN_LATER")); 737 return TRY_AGAIN_LATER; 738 } 739 740 /* Initialize acb */ 741 acb->xs = xs; 742 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 743 acb->clen = xs->cmdlen; 744 acb->daddr = xs->data; 745 acb->dleft = xs->datalen; 746 acb->stat = 0; 747 748 s = splbio(); 749 ACB_SETQ(acb, ACB_QREADY); 750 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 751 #if 1 752 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 753 #endif 754 755 /* 756 * 757 */ 758 if (sc->sc_state == SPC_IDLE) 759 mha_sched(sc); 760 761 splx(s); 762 763 if (flags & SCSI_POLL) { 764 /* Not allowed to use interrupts, use polling instead */ 765 return mha_poll(sc, acb); 766 } 767 768 SPC_MISC(("SUCCESSFULLY_QUEUED")); 769 return SUCCESSFULLY_QUEUED; 770 } 771 772 /* 773 * Adjust transfer size in buffer structure 774 */ 775 void 776 mha_minphys(bp) 777 struct buf *bp; 778 { 779 780 SPC_TRACE(("mha_minphys ")); 781 minphys(bp); 782 } 783 784 /* 785 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 786 */ 787 int 788 mha_poll(sc, acb) 789 struct mha_softc *sc; 790 struct acb *acb; 791 { 792 struct scsipi_xfer *xs = acb->xs; 793 int count = xs->timeout * 100; 794 int s = splbio(); 795 796 SPC_TRACE(("[mha_poll] ")); 797 798 while (count) { 799 /* 800 * If we had interrupts enabled, would we 801 * have got an interrupt? 802 */ 803 if (SSR & SS_IREQUEST) 804 mhaintr(sc); 805 if ((xs->flags & ITSDONE) != 0) 806 break; 807 DELAY(10); 808 #if 1 809 if (sc->sc_state == SPC_IDLE) { 810 SPC_TRACE(("[mha_poll: rescheduling] ")); 811 mha_sched(sc); 812 } 813 #endif 814 count--; 815 } 816 817 if (count == 0) { 818 SPC_MISC(("mha_poll: timeout")); 819 mha_timeout((caddr_t)acb); 820 } 821 splx(s); 822 return COMPLETE; 823 } 824 825 /* 827 * LOW LEVEL SCSI UTILITIES 828 */ 829 830 /* 831 * Set synchronous transfer offset and period. 832 */ 833 inline void 834 mha_setsync(sc, ti) 835 struct mha_softc *sc; 836 struct spc_tinfo *ti; 837 { 838 } 839 840 841 /* 843 * Schedule a SCSI operation. This has now been pulled out of the interrupt 844 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 845 * save us an unecessary interrupt just to get things going. Should only be 846 * called when state == SPC_IDLE and at bio pl. 847 */ 848 void 849 mha_sched(sc) 850 register struct mha_softc *sc; 851 { 852 struct scsipi_link *sc_link; 853 struct acb *acb; 854 int t; 855 856 SPC_TRACE(("[mha_sched] ")); 857 if (sc->sc_state != SPC_IDLE) 858 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 859 860 if (sc->sc_flags & SPC_ABORTING) 861 return; 862 863 /* 864 * Find first acb in ready queue that is for a target/lunit 865 * combinations that is not busy. 866 */ 867 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 868 struct spc_tinfo *ti; 869 sc_link = acb->xs->sc_link; 870 t = sc_link->scsipi_scsi.target; 871 ti = &sc->sc_tinfo[t]; 872 if (!(ti->lubusy & (1 << sc_link->scsipi_scsi.lun))) { 873 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 874 panic("mha: busy entry on ready list"); 875 TAILQ_REMOVE(&sc->ready_list, acb, chain); 876 ACB_SETQ(acb, ACB_QNONE); 877 sc->sc_nexus = acb; 878 sc->sc_flags = 0; 879 sc->sc_prevphase = INVALID_PHASE; 880 sc->sc_dp = acb->daddr; 881 sc->sc_dleft = acb->dleft; 882 ti->lubusy |= (1<<sc_link->scsipi_scsi.lun); 883 mhaselect(sc, t, sc_link->scsipi_scsi.lun, 884 (u_char *)&acb->cmd, acb->clen); 885 break; 886 } else { 887 SPC_MISC(("%d:%d busy\n", 888 sc_link->scsipi_scsi.target, 889 sc_link->scsipi_scsi.lun)); 890 } 891 } 892 } 893 894 void 896 mha_sense(sc, acb) 897 struct mha_softc *sc; 898 struct acb *acb; 899 { 900 struct scsipi_xfer *xs = acb->xs; 901 struct scsipi_link *sc_link = xs->sc_link; 902 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 903 struct scsipi_sense *ss = (void *)&acb->cmd; 904 905 SPC_MISC(("requesting sense ")); 906 /* Next, setup a request sense command block */ 907 bzero(ss, sizeof(*ss)); 908 ss->opcode = REQUEST_SENSE; 909 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 910 ss->length = sizeof(struct scsipi_sense_data); 911 acb->clen = sizeof(*ss); 912 acb->daddr = (char *)&xs->sense; 913 acb->dleft = sizeof(struct scsipi_sense_data); 914 acb->flags |= ACB_CHKSENSE; 915 ti->senses++; 916 if (acb->flags & ACB_QNEXUS) 917 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 918 if (acb == sc->sc_nexus) { 919 mhaselect(sc, sc_link->scsipi_scsi.target, 920 sc_link->scsipi_scsi.lun, 921 (void *)&acb->cmd, acb->clen); 922 } else { 923 mha_dequeue(sc, acb); 924 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 925 if (sc->sc_state == SPC_IDLE) 926 mha_sched(sc); 927 } 928 } 929 930 /* 931 * POST PROCESSING OF SCSI_CMD (usually current) 932 */ 933 void 934 mha_done(sc, acb) 935 struct mha_softc *sc; 936 struct acb *acb; 937 { 938 struct scsipi_xfer *xs = acb->xs; 939 struct scsipi_link *sc_link = xs->sc_link; 940 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 941 942 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 943 944 #if 1 945 untimeout(mha_timeout, acb); 946 #endif 947 948 /* 949 * Now, if we've come here with no error code, i.e. we've kept the 950 * initial XS_NOERROR, and the status code signals that we should 951 * check sense, we'll need to set up a request sense cmd block and 952 * push the command back into the ready queue *before* any other 953 * commands for this target/lunit, else we lose the sense info. 954 * We don't support chk sense conditions for the request sense cmd. 955 */ 956 if (xs->error == XS_NOERROR) { 957 if ((acb->flags & ACB_ABORTED) != 0) { 958 xs->error = XS_TIMEOUT; 959 } else if (acb->flags & ACB_CHKSENSE) { 960 xs->error = XS_SENSE; 961 } else { 962 switch (acb->stat & ST_MASK) { 963 case SCSI_CHECK: 964 { 965 struct scsipi_sense *ss = (void *)&acb->cmd; 966 SPC_MISC(("requesting sense ")); 967 /* First, save the return values */ 968 xs->resid = acb->dleft; 969 xs->status = acb->stat; 970 /* Next, setup a request sense command block */ 971 bzero(ss, sizeof(*ss)); 972 ss->opcode = REQUEST_SENSE; 973 /*ss->byte2 = sc_link->lun << 5;*/ 974 ss->length = sizeof(struct scsipi_sense_data); 975 acb->clen = sizeof(*ss); 976 acb->daddr = (char *)&xs->sense; 977 acb->dleft = sizeof(struct scsipi_sense_data); 978 acb->flags |= ACB_CHKSENSE; 979 /*XXX - must take off queue here */ 980 if (acb != sc->sc_nexus) { 981 panic("%s: mha_sched: floating acb %p", 982 sc->sc_dev.dv_xname, acb); 983 } 984 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 985 ACB_SETQ(acb, ACB_QREADY); 986 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 987 ti->senses++; 988 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 989 if (sc->sc_nexus == acb) { 990 sc->sc_nexus = NULL; 991 sc->sc_state = SPC_IDLE; 992 mha_sched(sc); 993 } 994 #if 0 995 mha_sense(sc, acb); 996 #endif 997 return; 998 } 999 case SCSI_BUSY: 1000 xs->error = XS_BUSY; 1001 break; 1002 case SCSI_OK: 1003 xs->resid = acb->dleft; 1004 break; 1005 default: 1006 xs->error = XS_DRIVER_STUFFUP; 1007 #if SPC_DEBUG 1008 printf("%s: mha_done: bad stat 0x%x\n", 1009 sc->sc_dev.dv_xname, acb->stat); 1010 #endif 1011 break; 1012 } 1013 } 1014 } 1015 1016 xs->flags |= ITSDONE; 1017 1018 #if SPC_DEBUG 1019 if ((mha_debug & SPC_SHOWMISC) != 0) { 1020 if (xs->resid != 0) 1021 printf("resid=%d ", xs->resid); 1022 if (xs->error == XS_SENSE) 1023 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 1024 else 1025 printf("error=%d\n", xs->error); 1026 } 1027 #endif 1028 1029 /* 1030 * Remove the ACB from whatever queue it's on. 1031 */ 1032 switch (acb->flags & ACB_QBITS) { 1033 case ACB_QNONE: 1034 if (acb != sc->sc_nexus) { 1035 panic("%s: floating acb", sc->sc_dev.dv_xname); 1036 } 1037 sc->sc_nexus = NULL; 1038 sc->sc_state = SPC_IDLE; 1039 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1040 mha_sched(sc); 1041 break; 1042 case ACB_QREADY: 1043 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1044 break; 1045 case ACB_QNEXUS: 1046 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1047 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1048 break; 1049 case ACB_QFREE: 1050 panic("%s: dequeue: busy acb on free list", 1051 sc->sc_dev.dv_xname); 1052 break; 1053 default: 1054 panic("%s: dequeue: unknown queue %d", 1055 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1056 } 1057 1058 /* Put it on the free list, and clear flags. */ 1059 #if 0 1060 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1061 acb->flags = ACB_QFREE; 1062 #else 1063 mha_free_acb(sc, acb, xs->flags); 1064 #endif 1065 1066 ti->cmds++; 1067 scsipi_done(xs); 1068 } 1069 1070 void 1071 mha_dequeue(sc, acb) 1072 struct mha_softc *sc; 1073 struct acb *acb; 1074 { 1075 1076 if (acb->flags & ACB_QNEXUS) { 1077 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1078 } else { 1079 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1080 } 1081 } 1082 1083 /* 1085 * INTERRUPT/PROTOCOL ENGINE 1086 */ 1087 1088 /* 1089 * Schedule an outgoing message by prioritizing it, and asserting 1090 * attention on the bus. We can only do this when we are the initiator 1091 * else there will be an illegal command interrupt. 1092 */ 1093 #define mha_sched_msgout(m) \ 1094 do { \ 1095 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1096 CMR = CMD_SET_ATN; \ 1097 sc->sc_msgpriq |= (m); \ 1098 } while (0) 1099 1100 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1101 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1102 #define ISEXTMSG(m) ((m) == 0x01) 1103 1104 /* 1105 * Precondition: 1106 * The SCSI bus is already in the MSGI phase and there is a message byte 1107 * on the bus, along with an asserted REQ signal. 1108 */ 1109 void 1110 mha_msgin(sc) 1111 register struct mha_softc *sc; 1112 { 1113 register int v; 1114 int n; 1115 1116 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1117 1118 /* 1119 * Prepare for a new message. A message should (according 1120 * to the SCSI standard) be transmitted in one single 1121 * MESSAGE_IN_PHASE. If we have been in some other phase, 1122 * then this is a new message. 1123 */ 1124 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1125 sc->sc_flags &= ~SPC_DROP_MSGI; 1126 sc->sc_imlen = 0; 1127 } 1128 1129 WAIT; 1130 1131 v = MBR; /* modified byte */ 1132 v = sc->sc_pcx[0]; 1133 1134 sc->sc_imess[sc->sc_imlen] = v; 1135 1136 /* 1137 * If we're going to reject the message, don't bother storing 1138 * the incoming bytes. But still, we need to ACK them. 1139 */ 1140 1141 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1142 CMR = CMD_SET_ATN; 1143 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1144 printf("<dropping msg byte %x>", 1145 sc->sc_imess[sc->sc_imlen]); 1146 return; 1147 } 1148 1149 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1150 mha_sched_msgout(SEND_REJECT); 1151 sc->sc_flags |= SPC_DROP_MSGI; 1152 } else { 1153 sc->sc_imlen++; 1154 /* 1155 * This testing is suboptimal, but most 1156 * messages will be of the one byte variety, so 1157 * it should not effect performance 1158 * significantly. 1159 */ 1160 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1161 goto gotit; 1162 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1163 goto gotit; 1164 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1165 sc->sc_imlen == sc->sc_imess[1] + 2) 1166 goto gotit; 1167 } 1168 #if 0 1169 /* Ack what we have so far */ 1170 ESPCMD(sc, ESPCMD_MSGOK); 1171 #endif 1172 return; 1173 1174 gotit: 1175 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1176 /* 1177 * Now we should have a complete message (1 byte, 2 byte 1178 * and moderately long extended messages). We only handle 1179 * extended messages which total length is shorter than 1180 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1181 */ 1182 if (sc->sc_state == SPC_HASNEXUS) { 1183 struct acb *acb = sc->sc_nexus; 1184 struct spc_tinfo *ti = 1185 &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1186 1187 switch (sc->sc_imess[0]) { 1188 case MSG_CMDCOMPLETE: 1189 SPC_MSGS(("cmdcomplete ")); 1190 if (sc->sc_dleft < 0) { 1191 struct scsipi_link *sc_link = acb->xs->sc_link; 1192 printf("mha: %d extra bytes from %d:%d\n", 1193 -sc->sc_dleft, 1194 sc_link->scsipi_scsi.target, 1195 sc_link->scsipi_scsi.lun); 1196 sc->sc_dleft = 0; 1197 } 1198 acb->xs->resid = acb->dleft = sc->sc_dleft; 1199 sc->sc_flags |= SPC_BUSFREE_OK; 1200 break; 1201 1202 case MSG_MESSAGE_REJECT: 1203 #if SPC_DEBUG 1204 if (mha_debug & SPC_SHOWMSGS) 1205 printf("%s: our msg rejected by target\n", 1206 sc->sc_dev.dv_xname); 1207 #endif 1208 #if 1 /* XXX - must remember last message */ 1209 scsi_print_addr(acb->xs->sc_link); 1210 printf("MSG_MESSAGE_REJECT>>"); 1211 #endif 1212 if (sc->sc_flags & SPC_SYNCHNEGO) { 1213 ti->period = ti->offset = 0; 1214 sc->sc_flags &= ~SPC_SYNCHNEGO; 1215 ti->flags &= ~T_NEGOTIATE; 1216 } 1217 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1218 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1219 mha_sched_msgout(SEND_ABORT); 1220 break; 1221 case MSG_NOOP: 1222 SPC_MSGS(("noop ")); 1223 break; 1224 case MSG_DISCONNECT: 1225 SPC_MSGS(("disconnect ")); 1226 ti->dconns++; 1227 sc->sc_flags |= SPC_DISCON; 1228 sc->sc_flags |= SPC_BUSFREE_OK; 1229 if ((acb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1230 break; 1231 /*FALLTHROUGH*/ 1232 case MSG_SAVEDATAPOINTER: 1233 SPC_MSGS(("save datapointer ")); 1234 acb->dleft = sc->sc_dleft; 1235 acb->daddr = sc->sc_dp; 1236 break; 1237 case MSG_RESTOREPOINTERS: 1238 SPC_MSGS(("restore datapointer ")); 1239 if (!acb) { 1240 mha_sched_msgout(SEND_ABORT); 1241 printf("%s: no DATAPOINTERs to restore\n", 1242 sc->sc_dev.dv_xname); 1243 break; 1244 } 1245 sc->sc_dp = acb->daddr; 1246 sc->sc_dleft = acb->dleft; 1247 break; 1248 case MSG_PARITY_ERROR: 1249 printf("%s:target%d: MSG_PARITY_ERROR\n", 1250 sc->sc_dev.dv_xname, 1251 acb->xs->sc_link->scsipi_scsi.target); 1252 break; 1253 case MSG_EXTENDED: 1254 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1255 switch (sc->sc_imess[2]) { 1256 case MSG_EXT_SDTR: 1257 SPC_MSGS(("SDTR period %d, offset %d ", 1258 sc->sc_imess[3], sc->sc_imess[4])); 1259 ti->period = sc->sc_imess[3]; 1260 ti->offset = sc->sc_imess[4]; 1261 if (sc->sc_minsync == 0) { 1262 /* We won't do synch */ 1263 ti->offset = 0; 1264 mha_sched_msgout(SEND_SDTR); 1265 } else if (ti->offset == 0) { 1266 printf("%s:%d: async\n", "mha", 1267 acb->xs->sc_link->scsipi_scsi.target); 1268 ti->offset = 0; 1269 sc->sc_flags &= ~SPC_SYNCHNEGO; 1270 } else if (ti->period > 124) { 1271 printf("%s:%d: async\n", "mha", 1272 acb->xs->sc_link->scsipi_scsi.target); 1273 ti->offset = 0; 1274 mha_sched_msgout(SEND_SDTR); 1275 } else { 1276 int r = 250/ti->period; 1277 int s = (100*250)/ti->period - 100*r; 1278 int p; 1279 #if 0 1280 p = mha_stp2cpb(sc, ti->period); 1281 ti->period = mha_cpb2stp(sc, p); 1282 #endif 1283 1284 #if SPC_DEBUG 1285 scsi_print_addr(acb->xs->sc_link); 1286 #endif 1287 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1288 /* Target initiated negotiation */ 1289 if (ti->flags & T_SYNCMODE) { 1290 ti->flags &= ~T_SYNCMODE; 1291 #if SPC_DEBUG 1292 printf("renegotiated "); 1293 #endif 1294 } 1295 TMR=TM_ASYNC; 1296 /* Clamp to our maxima */ 1297 if (ti->period < sc->sc_minsync) 1298 ti->period = sc->sc_minsync; 1299 if (ti->offset > 15) 1300 ti->offset = 15; 1301 mha_sched_msgout(SEND_SDTR); 1302 } else { 1303 /* we are sync */ 1304 sc->sc_flags &= ~SPC_SYNCHNEGO; 1305 TMR = TM_SYNC; 1306 ti->flags |= T_SYNCMODE; 1307 } 1308 #if SPC_DEBUG 1309 printf("max sync rate %d.%02dMb/s\n", 1310 r, s); 1311 #endif 1312 } 1313 ti->flags &= ~T_NEGOTIATE; 1314 break; 1315 default: /* Extended messages we don't handle */ 1316 CMR = CMD_SET_ATN; /* XXX? */ 1317 break; 1318 } 1319 break; 1320 default: 1321 SPC_MSGS(("ident ")); 1322 /* thanks for that ident... */ 1323 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1324 SPC_MISC(("unknown ")); 1325 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1326 CMR = CMD_SET_ATN; /* XXX? */ 1327 } 1328 break; 1329 } 1330 } else if (sc->sc_state == SPC_RESELECTED) { 1331 struct scsipi_link *sc_link = NULL; 1332 struct acb *acb; 1333 struct spc_tinfo *ti; 1334 u_char lunit; 1335 1336 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1337 SPC_MISC(("searching ")); 1338 /* 1339 * Search wait queue for disconnected cmd 1340 * The list should be short, so I haven't bothered with 1341 * any more sophisticated structures than a simple 1342 * singly linked list. 1343 */ 1344 lunit = sc->sc_imess[0] & 0x07; 1345 for (acb = sc->nexus_list.tqh_first; acb; 1346 acb = acb->chain.tqe_next) { 1347 sc_link = acb->xs->sc_link; 1348 if (sc_link->scsipi_scsi.lun == lunit && 1349 sc->sc_selid == (1<<sc_link->scsipi_scsi.target)) { 1350 TAILQ_REMOVE(&sc->nexus_list, acb, 1351 chain); 1352 ACB_SETQ(acb, ACB_QNONE); 1353 break; 1354 } 1355 } 1356 1357 if (!acb) { /* Invalid reselection! */ 1358 mha_sched_msgout(SEND_ABORT); 1359 printf("mha: invalid reselect (idbit=0x%2x)\n", 1360 sc->sc_selid); 1361 } else { /* Reestablish nexus */ 1362 /* 1363 * Setup driver data structures and 1364 * do an implicit RESTORE POINTERS 1365 */ 1366 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1367 sc->sc_nexus = acb; 1368 sc->sc_dp = acb->daddr; 1369 sc->sc_dleft = acb->dleft; 1370 sc->sc_tinfo[sc_link->scsipi_scsi.target].lubusy 1371 |= (1<<sc_link->scsipi_scsi.lun); 1372 if (ti->flags & T_SYNCMODE) { 1373 TMR = TM_SYNC; /* XXX */ 1374 } else { 1375 TMR = TM_ASYNC; 1376 } 1377 SPC_MISC(("... found acb")); 1378 sc->sc_state = SPC_HASNEXUS; 1379 } 1380 } else { 1381 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1382 sc->sc_dev.dv_xname, sc->sc_selid); 1383 mha_sched_msgout(SEND_DEV_RESET); 1384 } 1385 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1386 printf("%s: unexpected message in; will send DEV_RESET\n", 1387 sc->sc_dev.dv_xname); 1388 mha_sched_msgout(SEND_DEV_RESET); 1389 } 1390 1391 /* Ack last message byte */ 1392 #if 0 1393 ESPCMD(sc, ESPCMD_MSGOK); 1394 #endif 1395 1396 /* Done, reset message pointer. */ 1397 sc->sc_flags &= ~SPC_DROP_MSGI; 1398 sc->sc_imlen = 0; 1399 } 1400 1401 /* 1402 * Send the highest priority, scheduled message. 1403 */ 1404 void 1405 mha_msgout(sc) 1406 register struct mha_softc *sc; 1407 { 1408 struct spc_tinfo *ti; 1409 int n; 1410 1411 SPC_TRACE(("mha_msgout ")); 1412 1413 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1414 if (sc->sc_omp == sc->sc_omess) { 1415 /* 1416 * This is a retransmission. 1417 * 1418 * We get here if the target stayed in MESSAGE OUT 1419 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1420 * that all of the previously transmitted messages must 1421 * be sent again, in the same order. Therefore, we 1422 * requeue all the previously transmitted messages, and 1423 * start again from the top. Our simple priority 1424 * scheme keeps the messages in the right order. 1425 */ 1426 SPC_MISC(("retransmitting ")); 1427 sc->sc_msgpriq |= sc->sc_msgoutq; 1428 /* 1429 * Set ATN. If we're just sending a trivial 1-byte 1430 * message, we'll clear ATN later on anyway. 1431 */ 1432 CMR = CMD_SET_ATN; /* XXX? */ 1433 } else { 1434 /* This is a continuation of the previous message. */ 1435 n = sc->sc_omp - sc->sc_omess; 1436 goto nextbyte; 1437 } 1438 } 1439 1440 /* No messages transmitted so far. */ 1441 sc->sc_msgoutq = 0; 1442 sc->sc_lastmsg = 0; 1443 1444 nextmsg: 1445 /* Pick up highest priority message. */ 1446 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1447 sc->sc_msgpriq &= ~sc->sc_currmsg; 1448 sc->sc_msgoutq |= sc->sc_currmsg; 1449 1450 /* Build the outgoing message data. */ 1451 switch (sc->sc_currmsg) { 1452 case SEND_IDENTIFY: 1453 SPC_ASSERT(sc->sc_nexus != NULL); 1454 sc->sc_omess[0] = 1455 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1456 n = 1; 1457 break; 1458 1459 #if SPC_USE_SYNCHRONOUS 1460 case SEND_SDTR: 1461 SPC_ASSERT(sc->sc_nexus != NULL); 1462 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1463 sc->sc_omess[4] = MSG_EXTENDED; 1464 sc->sc_omess[3] = 3; 1465 sc->sc_omess[2] = MSG_EXT_SDTR; 1466 sc->sc_omess[1] = ti->period >> 2; 1467 sc->sc_omess[0] = ti->offset; 1468 n = 5; 1469 break; 1470 #endif 1471 1472 #if SPC_USE_WIDE 1473 case SEND_WDTR: 1474 SPC_ASSERT(sc->sc_nexus != NULL); 1475 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1476 sc->sc_omess[3] = MSG_EXTENDED; 1477 sc->sc_omess[2] = 2; 1478 sc->sc_omess[1] = MSG_EXT_WDTR; 1479 sc->sc_omess[0] = ti->width; 1480 n = 4; 1481 break; 1482 #endif 1483 1484 case SEND_DEV_RESET: 1485 sc->sc_flags |= SPC_ABORTING; 1486 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1487 n = 1; 1488 break; 1489 1490 case SEND_REJECT: 1491 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1492 n = 1; 1493 break; 1494 1495 case SEND_PARITY_ERROR: 1496 sc->sc_omess[0] = MSG_PARITY_ERROR; 1497 n = 1; 1498 break; 1499 1500 case SEND_INIT_DET_ERR: 1501 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1502 n = 1; 1503 break; 1504 1505 case SEND_ABORT: 1506 sc->sc_flags |= SPC_ABORTING; 1507 sc->sc_omess[0] = MSG_ABORT; 1508 n = 1; 1509 break; 1510 1511 default: 1512 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1513 sc->sc_dev.dv_xname); 1514 SPC_BREAK(); 1515 sc->sc_omess[0] = MSG_NOOP; 1516 n = 1; 1517 break; 1518 } 1519 sc->sc_omp = &sc->sc_omess[n]; 1520 1521 nextbyte: 1522 /* Send message bytes. */ 1523 /* send TRANSFER command. */ 1524 sc->sc_ps[3] = 1; 1525 sc->sc_ps[4] = n >> 8; 1526 sc->sc_pc[10] = n; 1527 sc->sc_ps[-1] = 0x000F; /* burst */ 1528 asm volatile ("nop"); 1529 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1530 for (;;) { 1531 if ((SSR & SS_BUSY) != 0) 1532 break; 1533 if (SSR & SS_IREQUEST) 1534 goto out; 1535 } 1536 for (;;) { 1537 #if 0 1538 for (;;) { 1539 if ((PSNS & PSNS_REQ) != 0) 1540 break; 1541 /* Wait for REQINIT. XXX Need timeout. */ 1542 } 1543 #endif 1544 if (SSR & SS_IREQUEST) { 1545 /* 1546 * Target left MESSAGE OUT, possibly to reject 1547 * our message. 1548 * 1549 * If this is the last message being sent, then we 1550 * deassert ATN, since either the target is going to 1551 * ignore this message, or it's going to ask for a 1552 * retransmission via MESSAGE PARITY ERROR (in which 1553 * case we reassert ATN anyway). 1554 */ 1555 #if 0 1556 if (sc->sc_msgpriq == 0) 1557 CMR = CMD_RESET_ATN; 1558 #endif 1559 goto out; 1560 } 1561 1562 #if 0 1563 /* Clear ATN before last byte if this is the last message. */ 1564 if (n == 1 && sc->sc_msgpriq == 0) 1565 CMR = CMD_RESET_ATN; 1566 #endif 1567 1568 while ((SSR & SS_DREG_FULL) != 0) 1569 ; 1570 /* Send message byte. */ 1571 sc->sc_pc[0] = *--sc->sc_omp; 1572 --n; 1573 /* Keep track of the last message we've sent any bytes of. */ 1574 sc->sc_lastmsg = sc->sc_currmsg; 1575 1576 if (n == 0) 1577 break; 1578 } 1579 1580 /* We get here only if the entire message has been transmitted. */ 1581 if (sc->sc_msgpriq != 0) { 1582 /* There are more outgoing messages. */ 1583 goto nextmsg; 1584 } 1585 1586 /* 1587 * The last message has been transmitted. We need to remember the last 1588 * message transmitted (in case the target switches to MESSAGE IN phase 1589 * and sends a MESSAGE REJECT), and the list of messages transmitted 1590 * this time around (in case the target stays in MESSAGE OUT phase to 1591 * request a retransmit). 1592 */ 1593 1594 out: 1595 /* Disable REQ/ACK protocol. */ 1596 } 1597 1598 1599 /*************************************************************** 1601 * 1602 * datain/dataout 1603 * 1604 */ 1605 1606 int 1607 mha_datain_pio(sc, p, n) 1608 register struct mha_softc *sc; 1609 u_char *p; 1610 int n; 1611 { 1612 u_short d; 1613 int a; 1614 int total_n = n; 1615 1616 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1617 1618 WAIT; 1619 sc->sc_ps[3] = 1; 1620 sc->sc_ps[4] = n >> 8; 1621 sc->sc_pc[10] = n; 1622 /* */ 1623 CMR = CMD_RECEIVE_TO_MPU; 1624 for (;;) { 1625 a = SSR; 1626 if (a & 0x04) { 1627 d = sc->sc_ps[0]; 1628 *p++ = d >> 8; 1629 if (--n > 0) { 1630 *p++ = d; 1631 --n; 1632 } 1633 a = SSR; 1634 } 1635 if (a & 0x40) 1636 continue; 1637 if (a & 0x80) 1638 break; 1639 } 1640 SPC_TRACE(("...%d resd]", n)); 1641 return total_n - n; 1642 } 1643 1644 int 1645 mha_dataout_pio(sc, p, n) 1646 register struct mha_softc *sc; 1647 u_char *p; 1648 int n; 1649 { 1650 u_short d; 1651 int a; 1652 int total_n = n; 1653 1654 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1655 1656 WAIT; 1657 sc->sc_ps[3] = 1; 1658 sc->sc_ps[4] = n >> 8; 1659 sc->sc_pc[10] = n; 1660 /* */ 1661 CMR = CMD_SEND_FROM_MPU; 1662 for (;;) { 1663 a = SSR; 1664 if (a & 0x04) { 1665 d = *p++ << 8; 1666 if (--n > 0) { 1667 d |= *p++; 1668 --n; 1669 } 1670 sc->sc_ps[0] = d; 1671 a = SSR; 1672 } 1673 if (a & 0x40) 1674 continue; 1675 if (a & 0x80) 1676 break; 1677 } 1678 SPC_TRACE(("...%d resd]", n)); 1679 return total_n - n; 1680 } 1681 1682 static int 1683 mha_dataio_dma(dw, cw, sc, p, n) 1684 int dw; /* DMA word */ 1685 int cw; /* CMR word */ 1686 register struct mha_softc *sc; 1687 u_char *p; 1688 int n; 1689 { 1690 char *paddr, *vaddr; 1691 1692 if (n > MAXBSIZE) 1693 panic("transfer size exceeds MAXBSIZE"); 1694 if (sc->sc_dmasize > 0) 1695 panic("DMA request while another DMA transfer is in pregress"); 1696 1697 memcpy(sc->sc_dmabuf, p, n); 1698 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, 1699 (cw == CMD_SEND_FROM_DMA)?BUS_DMASYNC_PREWRITE 1700 :BUS_DMASYNC_PREREAD); 1701 sc->sc_p = p; 1702 sc->sc_dmasize = n; 1703 1704 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1705 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1706 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1707 dw &= ~(1 << 3); 1708 #endif 1709 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1710 #if 0 1711 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1712 PCIA(); /* XXX */ 1713 #endif 1714 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1715 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1716 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1717 WAIT; 1718 sc->sc_ps[3] = 1; 1719 sc->sc_ps[4] = n >> 8; 1720 sc->sc_pc[10] = n; 1721 /* DMA 1722 3 ... short bus cycle 1723 2 ... MAXIMUM XFER. 1724 1 ... BURST XFER. 1725 0 ... R/W */ 1726 sc->sc_ps[-1] = dw; /* burst */ 1727 asm volatile ("nop"); 1728 CMR = cw; /* receive to DMA */ 1729 return n; 1730 } 1731 int 1732 mha_dataout(sc, p, n) 1733 register struct mha_softc *sc; 1734 u_char *p; 1735 int n; 1736 { 1737 register struct acb *acb = sc->sc_nexus; 1738 1739 if (n == 0) 1740 return n; 1741 1742 if (n & 1) 1743 return mha_dataout_pio(sc, p, n); 1744 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1745 } 1746 1747 int 1749 mha_datain(sc, p, n) 1750 register struct mha_softc *sc; 1751 u_char *p; 1752 int n; 1753 { 1754 int ts; 1755 register struct acb *acb = sc->sc_nexus; 1756 char *paddr, *vaddr; 1757 1758 if (n == 0) 1759 return n; 1760 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1761 return mha_datain_pio(sc, p, n); 1762 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1763 } 1764 1765 1767 /* 1768 * Catch an interrupt from the adaptor 1769 */ 1770 /* 1771 * This is the workhorse routine of the driver. 1772 * Deficiencies (for now): 1773 * 1) always uses programmed I/O 1774 */ 1775 int 1776 mhaintr(arg) 1777 void *arg; 1778 { 1779 struct mha_softc *sc = arg; 1780 #if 0 1781 u_char ints; 1782 #endif 1783 struct acb *acb; 1784 struct scsipi_link *sc_link; 1785 struct spc_tinfo *ti; 1786 u_char ph; 1787 u_short r; 1788 int n; 1789 1790 #if 1 /* XXX called during attach? */ 1791 if (tmpsc != NULL) { 1792 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1793 sc = tmpsc; 1794 } else { 1795 #endif 1796 1797 #if 1 /* XXX */ 1798 } 1799 #endif 1800 1801 #if 0 1802 /* 1803 * 1804 */ 1805 SCTL &= ~SCTL_INTR_ENAB; 1806 #endif 1807 1808 SPC_TRACE(("[mhaintr]")); 1809 1810 loop: 1811 /* 1812 * 1813 */ 1814 /* 1815 * First check for abnormal conditions, such as reset. 1816 */ 1817 #if 0 1818 #if 1 /* XXX? */ 1819 while (((ints = SSR) & SS_IREQUEST) == 0) 1820 delay(1); 1821 SPC_MISC(("ints = 0x%x ", ints)); 1822 #else /* usually? */ 1823 ints = SSR; 1824 #endif 1825 #endif 1826 while (SSR & SS_IREQUEST) { 1827 acb = sc->sc_nexus; 1828 r = ISCSR; 1829 SPC_MISC(("[r=0x%x]", r)); 1830 switch (r >> 8) { 1831 default: 1832 printf("[addr=%x\n" 1833 "result=0x%x\n" 1834 "cmd=0x%x\n" 1835 "ph=0x%x(ought to be %d)]\n", 1836 &ISCSR, 1837 r, 1838 acb->xs->cmd->opcode, 1839 SCR, sc->sc_phase); 1840 panic("unexpected result."); 1841 case 0x82: /* selection timeout */ 1842 SPC_MISC(("selection timeout ")); 1843 sc->sc_phase = BUSFREE_PHASE; 1844 SPC_ASSERT(sc->sc_nexus != NULL); 1845 acb = sc->sc_nexus; 1846 delay(250); 1847 acb->xs->error = XS_SELTIMEOUT; 1848 mha_done(sc, acb); 1849 continue; /* XXX ??? msaitoh */ 1850 case 0x60: /* command completed */ 1851 sc->sc_spcinitialized++; 1852 if (sc->sc_phase == BUSFREE_PHASE) 1853 continue; 1854 ph = SCR; 1855 if (ph & PSNS_ACK) { 1856 int s; 1857 /* */ 1858 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1859 ph & PHASE_MASK, sc->sc_phase)); 1860 #if 0 1861 /* switch (sc->sc_phase) {*/ 1862 #else 1863 switch (ph & PHASE_MASK) { 1864 #endif 1865 case STATUS_PHASE: 1866 if (sc->sc_state != SPC_HASNEXUS) 1867 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1868 sc->sc_state); 1869 SPC_ASSERT(sc->sc_nexus != NULL); 1870 acb = sc->sc_nexus; 1871 WAIT; 1872 s = MBR; 1873 SPC_ASSERT(s == 1); 1874 acb->stat = sc->sc_pcx[0]; /* XXX */ 1875 SPC_MISC(("stat=0x%02x ", acb->stat)); 1876 sc->sc_prevphase = STATUS_PHASE; 1877 break; 1878 case MESSAGE_IN_PHASE: 1879 mha_msgin(sc); 1880 sc->sc_prevphase = MESSAGE_IN_PHASE; 1881 /* thru */ 1882 case DATA_IN_PHASE: 1883 if (sc->sc_dmasize == 0) 1884 break; 1885 bus_dmamap_sync(sc->sc_dmat, 1886 sc->sc_dmamap, 1887 0, sc->sc_dmasize, 1888 BUS_DMASYNC_POSTREAD); 1889 memcpy(sc->sc_p, sc->sc_dmabuf, 1890 sc->sc_dmasize); 1891 sc->sc_dmasize = 0; 1892 break; 1893 case DATA_OUT_PHASE: 1894 if (sc->sc_dmasize == 0) 1895 break; 1896 bus_dmamap_sync(sc->sc_dmat, 1897 sc->sc_dmamap, 1898 0, sc->sc_dmasize, 1899 BUS_DMASYNC_POSTWRITE); 1900 sc->sc_dmasize = 0; 1901 break; 1902 } 1903 WAIT; 1904 CMR = CMD_RESET_ACK; /* reset ack */ 1905 /*mha_done(sc, acb); XXX */ 1906 continue; 1907 } else if (NSR & 0x80) { /* nexus */ 1908 #if 1 1909 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1910 sc->sc_state = SPC_HASNEXUS; 1911 /* 1912 initial-phase error(0x54) 1913 1914 0x65 ? */ 1915 WAIT; 1916 if (SSR & SS_IREQUEST) 1917 continue; 1918 switch (sc->sc_phase) { 1919 default: 1920 panic(" phase "); 1921 case MESSAGE_IN_PHASE: 1922 /* */ 1923 continue; 1924 case STATUS_PHASE: 1925 sc->sc_phase = MESSAGE_IN_PHASE; 1926 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1927 continue; 1928 case DATA_IN_PHASE: 1929 sc->sc_prevphase = DATA_IN_PHASE; 1930 if (sc->sc_dleft == 0) { 1931 /* 1932 */ 1933 sc->sc_phase = STATUS_PHASE; 1934 CMR = CMD_RECEIVE_STS; /* receive sts */ 1935 continue; 1936 } 1937 n = mha_datain(sc, sc->sc_dp, 1938 sc->sc_dleft); 1939 sc->sc_dp += n; 1940 sc->sc_dleft -= n; 1941 continue; 1942 case DATA_OUT_PHASE: 1943 sc->sc_prevphase = DATA_OUT_PHASE; 1944 if (sc->sc_dleft == 0) { 1945 /* 1946 */ 1947 sc->sc_phase = STATUS_PHASE; 1948 CMR = CMD_RECEIVE_STS; /* receive sts */ 1949 continue; 1950 } 1951 /* data phase */ 1952 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1953 sc->sc_dp += n; 1954 sc->sc_dleft -= n; 1955 continue; 1956 case COMMAND_PHASE: 1957 /* CMD PHASE */ 1958 if (acb->dleft) { 1959 /* */ 1960 if (acb->xs->flags & SCSI_DATA_IN) { 1961 sc->sc_phase = DATA_IN_PHASE; 1962 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1963 sc->sc_dp += n; 1964 sc->sc_dleft -= n; 1965 } 1966 else if (acb->xs->flags & SCSI_DATA_OUT) { 1967 sc->sc_phase = DATA_OUT_PHASE; 1968 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1969 sc->sc_dp += n; 1970 sc->sc_dleft -= n; 1971 } 1972 continue; 1973 } 1974 else { 1975 /* ?! */ 1976 WAIT; 1977 sc->sc_phase = STATUS_PHASE; 1978 CMR = CMD_RECEIVE_STS; /* receive sts */ 1979 continue; 1980 } 1981 } 1982 #endif 1983 } 1984 continue; 1985 case 0x31: /* disconnected in xfer progress. */ 1986 SPC_MISC(("[0x31]")); 1987 case 0x70: /* disconnected. */ 1988 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1989 sc->sc_phase = BUSFREE_PHASE; 1990 sc->sc_state = SPC_IDLE; 1991 #if 1 1992 acb = sc->sc_nexus; 1993 SPC_ASSERT(sc->sc_nexus != NULL); 1994 acb->xs->error = XS_NOERROR; 1995 mha_done(sc, acb); 1996 #else 1997 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1998 mha_sched(sc); 1999 #endif 2000 continue; 2001 case 0x32: /* phase error in xfer progress. */ 2002 SPC_MISC(("[0x32]")); 2003 #if 0 2004 case 0x65: /* invalid command. 2005 2006 */ 2007 #if 1 2008 SPC_MISC(("[0x%04x]", r)); 2009 #endif 2010 #endif 2011 case 0x54: /* initial-phase error. */ 2012 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 2013 NSR, 2014 SCR, sc->sc_phase)); 2015 /* thru */ 2016 case 0x71: /* assert req */ 2017 WAIT; 2018 if (SSR & 0x40) { 2019 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 2020 SSR, r, NSR, SCR); 2021 WAIT; 2022 } 2023 ph = SCR; 2024 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 2025 sc->sc_state = SPC_HASNEXUS; 2026 } 2027 if (ph & 0x80) { 2028 switch (ph & PHASE_MASK) { 2029 default: 2030 printf("phase = %x\n", ph); 2031 panic("assert req: the phase I don't know!"); 2032 case DATA_IN_PHASE: 2033 sc->sc_prevphase = DATA_IN_PHASE; 2034 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 2035 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 2036 sc->sc_dp += n; 2037 sc->sc_dleft -= n; 2038 SPC_MISC(("done\n")); 2039 continue; 2040 case DATA_OUT_PHASE: 2041 sc->sc_prevphase = DATA_OUT_PHASE; 2042 SPC_MISC(("DATAOUT\n")); 2043 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 2044 sc->sc_dp += n; 2045 sc->sc_dleft -= n; 2046 continue; 2047 case STATUS_PHASE: 2048 sc->sc_phase = STATUS_PHASE; 2049 SPC_MISC(("[RECV_STS]")); 2050 WAIT; 2051 CMR = CMD_RECEIVE_STS; /* receive sts */ 2052 continue; 2053 case MESSAGE_IN_PHASE: 2054 sc->sc_phase = MESSAGE_IN_PHASE; 2055 WAIT; 2056 CMR = CMD_RECEIVE_MSG; 2057 continue; 2058 } 2059 } 2060 continue; 2061 } 2062 } 2063 } 2064 2065 void 2066 mha_abort(sc, acb) 2067 struct mha_softc *sc; 2068 struct acb *acb; 2069 { 2070 acb->flags |= ACB_ABORTED; 2071 2072 if (acb == sc->sc_nexus) { 2073 /* 2074 * If we're still selecting, the message will be scheduled 2075 * after selection is complete. 2076 */ 2077 if (sc->sc_state == SPC_HASNEXUS) { 2078 sc->sc_flags |= SPC_ABORTING; 2079 mha_sched_msgout(SEND_ABORT); 2080 } 2081 } else { 2082 if (sc->sc_state == SPC_IDLE) 2083 mha_sched(sc); 2084 } 2085 } 2086 2087 void 2088 mha_timeout(arg) 2089 void *arg; 2090 { 2091 int s = splbio(); 2092 struct acb *acb = (struct acb *)arg; 2093 struct scsipi_xfer *xs = acb->xs; 2094 struct scsipi_link *sc_link = xs->sc_link; 2095 struct mha_softc *sc = sc_link->adapter_softc; 2096 2097 scsi_print_addr(sc_link); 2098 again: 2099 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2100 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2101 sc->sc_dev.dv_xname, 2102 acb, acb->flags, acb->dleft, acb->stat, 2103 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2104 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2105 ); 2106 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2107 panic("timeout, ouch!"); 2108 2109 if (acb->flags & ACB_ABORTED) { 2110 /* abort timed out */ 2111 printf(" AGAIN\n"); 2112 #if 0 2113 mha_init(sc, 1); /* XXX 1?*/ 2114 #endif 2115 } else { 2116 /* abort the operation that has timed out */ 2117 printf("\n"); 2118 xs->error = XS_TIMEOUT; 2119 mha_abort(sc, acb); 2120 } 2121 2122 splx(s); 2123 } 2124 2125 #if SPC_DEBUG 2127 /* 2128 * The following functions are mostly used for debugging purposes, either 2129 * directly called from the driver or from the kernel debugger. 2130 */ 2131 2132 void 2133 mha_show_scsi_cmd(acb) 2134 struct acb *acb; 2135 { 2136 u_char *b = (u_char *)&acb->cmd; 2137 struct scsipi_link *sc_link = acb->xs->sc_link; 2138 int i; 2139 2140 scsi_print_addr(sc_link); 2141 if ((acb->xs->flags & SCSI_RESET) == 0) { 2142 for (i = 0; i < acb->clen; i++) { 2143 if (i) 2144 printf(","); 2145 printf("%x", b[i]); 2146 } 2147 printf("\n"); 2148 } else 2149 printf("RESET\n"); 2150 } 2151 2152 void 2153 mha_print_acb(acb) 2154 struct acb *acb; 2155 { 2156 2157 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2158 printf(" dp=%x dleft=%d stat=%x\n", 2159 (long)acb->daddr, acb->dleft, acb->stat); 2160 mha_show_scsi_cmd(acb); 2161 } 2162 2163 void 2164 mha_print_active_acb() 2165 { 2166 struct acb *acb; 2167 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2168 2169 printf("ready list:\n"); 2170 for (acb = sc->ready_list.tqh_first; acb != NULL; 2171 acb = acb->chain.tqe_next) 2172 mha_print_acb(acb); 2173 printf("nexus:\n"); 2174 if (sc->sc_nexus != NULL) 2175 mha_print_acb(sc->sc_nexus); 2176 printf("nexus list:\n"); 2177 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2178 acb = acb->chain.tqe_next) 2179 mha_print_acb(acb); 2180 } 2181 2182 void 2183 mha_dump_driver(sc) 2184 struct mha_softc *sc; 2185 { 2186 struct spc_tinfo *ti; 2187 int i; 2188 2189 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2190 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2191 sc->sc_state, sc->sc_imess[0], 2192 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2193 for (i = 0; i < 7; i++) { 2194 ti = &sc->sc_tinfo[i]; 2195 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2196 i, ti->cmds, ti->dconns, ti->touts); 2197 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2198 } 2199 } 2200 #endif 2201
Indexes created Sun Oct 19 02:09:48 GMT 2025