mha.c revision 1.17
1 /* $NetBSD: mha.c,v 1.17 1999/09/30 23:01:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 190 #define Debugger() panic("should call debugger here (mha.c)") 191 #endif /* ! DDB */ 192 193 194 #if SPC_DEBUG 195 #define SPC_SHOWACBS 0x01 196 #define SPC_SHOWINTS 0x02 197 #define SPC_SHOWCMDS 0x04 198 #define SPC_SHOWMISC 0x08 199 #define SPC_SHOWTRAC 0x10 200 #define SPC_SHOWSTART 0x20 201 #define SPC_SHOWPHASE 0x40 202 #define SPC_SHOWDMA 0x80 203 #define SPC_SHOWCCMDS 0x100 204 #define SPC_SHOWMSGS 0x200 205 #define SPC_DOBREAK 0x400 206 207 int mha_debug = 208 #if 0 209 0x7FF; 210 #else 211 SPC_SHOWSTART|SPC_SHOWTRAC; 212 #endif 213 214 215 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 216 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 217 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 218 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 219 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 220 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 221 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 222 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 223 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 224 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 225 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 226 #else 227 #define SPC_ACBS(str) 228 #define SPC_MISC(str) 229 #define SPC_INTS(str) 230 #define SPC_TRACE(str) 231 #define SPC_CMDS(str) 232 #define SPC_START(str) 233 #define SPC_PHASE(str) 234 #define SPC_DMA(str) 235 #define SPC_MSGS(str) 236 #define SPC_BREAK() 237 #define SPC_ASSERT(x) 238 #endif 239 240 int mhamatch __P((struct device *, struct cfdata *, void *)); 241 void mhaattach __P((struct device *, struct device *, void *)); 242 void mhaselect __P((struct mha_softc *, 243 u_char, u_char, u_char *, u_char)); 244 void mha_scsi_reset __P((struct mha_softc *)); 245 void mha_reset __P((struct mha_softc *)); 246 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 247 void mha_sense __P((struct mha_softc *, struct acb *)); 248 void mha_msgin __P((struct mha_softc *)); 249 void mha_msgout __P((struct mha_softc *)); 250 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 252 int mha_dataout __P((struct mha_softc *, u_char *, int)); 253 int mha_datain __P((struct mha_softc *, u_char *, int)); 254 void mha_abort __P((struct mha_softc *, struct acb *)); 255 void mha_init __P((struct mha_softc *)); 256 int mha_scsi_cmd __P((struct scsipi_xfer *)); 257 int mha_poll __P((struct mha_softc *, struct acb *)); 258 void mha_sched __P((struct mha_softc *)); 259 void mha_done __P((struct mha_softc *, struct acb *)); 260 int mhaintr __P((void*)); 261 void mha_timeout __P((void *)); 262 void mha_minphys __P((struct buf *)); 263 void mha_dequeue __P((struct mha_softc *, struct acb *)); 264 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 265 #if SPC_DEBUG 266 void mha_print_acb __P((struct acb *)); 267 void mha_show_scsi_cmd __P((struct acb *)); 268 void mha_print_active_acb __P((void)); 269 void mha_dump_driver __P((struct mha_softc *)); 270 #endif 271 272 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 273 274 struct cfattach mha_ca = { 275 sizeof(struct mha_softc), mhamatch, mhaattach 276 }; 277 278 extern struct cfdriver mha_cd; 279 280 struct scsipi_device mha_dev = { 281 NULL, /* Use default error handler */ 282 NULL, /* have a queue, served by this */ 283 NULL, /* have no async handler */ 284 NULL, /* Use default 'done' routine */ 285 }; 286 287 /* 289 * returns non-zero value if a controller is found. 290 */ 291 int 292 mhamatch(parent, cf, aux) 293 struct device *parent; 294 struct cfdata *cf; 295 void *aux; 296 { 297 struct intio_attach_args *ia = aux; 298 bus_space_tag_t iot = ia->ia_bst; 299 bus_space_handle_t ioh; 300 301 ia->ia_size=0x20; 302 if (ia->ia_addr != 0xea0000) 303 return 0; 304 305 if (intio_map_allocate_region(parent->dv_parent, ia, 306 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 307 return 0; 308 309 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 310 &ioh) < 0) 311 return 0; 312 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 313 return 0; 314 bus_space_unmap(iot, ioh, 0x20); 315 316 return 1; 317 } 318 319 /* 320 */ 321 322 struct mha_softc *tmpsc; 323 324 void 325 mhaattach(parent, self, aux) 326 struct device *parent, *self; 327 void *aux; 328 { 329 struct mha_softc *sc = (void *)self; 330 struct intio_attach_args *ia = aux; 331 332 tmpsc = sc; /* XXX */ 333 334 SPC_TRACE(("mhaattach ")); 335 sc->sc_state = SPC_INIT; 336 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 337 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 338 /* XXX: FAKE */ 339 sc->sc_dmat = ia->ia_dmat; 340 341 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 342 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 343 sc->sc_pcx = &sc->sc_pc[0x10]; 344 345 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 346 347 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 348 349 mha_init(sc); /* Init chip and driver */ 350 351 printf("\n%s: Resetting SCSI bus... ", self->dv_xname); 352 mha_scsi_reset(sc); /* XXX: some devices need this. */ 353 printf("done\n"); 354 355 sc->sc_phase = BUSFREE_PHASE; 356 357 /* 358 * Fill in the adapter. 359 */ 360 sc->sc_adapter.scsipi_cmd = mha_scsi_cmd; 361 sc->sc_adapter.scsipi_minphys = mha_minphys; 362 363 /* 364 * Fill in the prototype scsi_link 365 */ 366 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 367 sc->sc_link.adapter_softc = sc; 368 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 369 sc->sc_link.adapter = &sc->sc_adapter; 370 sc->sc_link.device = &mha_dev; 371 sc->sc_link.openings = 2; 372 sc->sc_link.scsipi_scsi.max_target = 7; 373 sc->sc_link.scsipi_scsi.max_lun = 7; 374 sc->sc_link.type = BUS_SCSI; 375 376 sc->sc_spcinitialized = 0; 377 WAR = WA_INITWIN; 378 #if 1 379 CCR = 0x14; 380 OIR = sc->sc_id; 381 AMR = 0x00; 382 SMR = 0x00; 383 SRR = 0x00; 384 STR = 0x20; 385 RTR = 0x40; 386 ATR = 0x01; 387 PER = 0xc9; 388 #endif 389 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 390 #if 1 391 GLR = 0x00; 392 DMR = 0x30; 393 IMR = 0x00; 394 #endif 395 WAR = WA_MCSBUFWIN; 396 397 /* drop off */ 398 while (SSR & SS_IREQUEST) 399 { 400 unsigned a = ISCSR; 401 } 402 403 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 404 405 SPC_TRACE(("waiting for intr...")); 406 while (!(SSR & SS_IREQUEST)) 407 delay(10); 408 mhaintr (sc); 409 410 tmpsc = NULL; 411 412 config_found(self, &sc->sc_link, scsiprint); 413 } 414 415 #if 0 416 void 417 mha_reset(sc) 418 struct mha_softc *sc; 419 { 420 u_short dummy; 421 printf("reset..."); 422 CMR = CMD_SOFT_RESET; 423 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 424 dummy = sc->sc_ps[-1]; 425 dummy = sc->sc_ps[-1]; 426 dummy = sc->sc_ps[-1]; 427 dummy = sc->sc_ps[-1]; 428 asm volatile ("nop"); 429 CMR = CMD_SOFT_RESET; 430 sc->sc_spcinitialized = 0; 431 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 432 while(!sc->sc_spcinitialized); 433 434 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 435 printf("done.\n"); 436 } 437 #endif 438 439 /* 440 * Pull the SCSI RST line for 500us. 441 */ 442 void 443 mha_scsi_reset(sc) /* FINISH? */ 444 struct mha_softc *sc; 445 { 446 447 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 448 while (!(SSR&SS_IREQUEST)) 449 delay(10); 450 } 451 452 /* 453 * Initialize mha SCSI driver. 454 */ 455 void 456 mha_init(sc) 457 struct mha_softc *sc; 458 { 459 struct acb *acb; 460 int r; 461 462 if (sc->sc_state == SPC_INIT) { 463 /* First time through; initialize. */ 464 TAILQ_INIT(&sc->ready_list); 465 TAILQ_INIT(&sc->nexus_list); 466 TAILQ_INIT(&sc->free_list); 467 sc->sc_nexus = NULL; 468 acb = sc->sc_acb; 469 bzero(acb, sizeof(sc->sc_acb)); 470 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 471 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 472 acb++; 473 } 474 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 475 476 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 477 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 478 BUS_DMA_NOWAIT); 479 if (r) 480 panic("mha_init: cannot allocate dma memory"); 481 if (sc->sc_ndmasegs != 1) 482 panic("mha_init: number of segment > 1??"); 483 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 484 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 485 if (r) 486 panic("mha_init: cannot map dma memory"); 487 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 488 MAXBSIZE, 0, BUS_DMA_NOWAIT, 489 &sc->sc_dmamap); 490 if (r) 491 panic("mha_init: cannot create dmamap structure"); 492 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 493 sc->sc_dmabuf, MAXBSIZE, NULL, 494 BUS_DMA_NOWAIT); 495 if (r) 496 panic("mha_init: cannot load dma buffer into dmamap"); 497 sc->sc_p = 0; 498 } else { 499 /* Cancel any active commands. */ 500 sc->sc_flags |= SPC_ABORTING; 501 sc->sc_state = SPC_IDLE; 502 if ((acb = sc->sc_nexus) != NULL) { 503 acb->xs->error = XS_DRIVER_STUFFUP; 504 mha_done(sc, acb); 505 } 506 while ((acb = sc->nexus_list.tqh_first) != NULL) { 507 acb->xs->error = XS_DRIVER_STUFFUP; 508 mha_done(sc, acb); 509 } 510 } 511 512 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 513 for (r = 0; r < 8; r++) { 514 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 515 516 ti->flags = 0; 517 #if SPC_USE_SYNCHRONOUS 518 ti->flags |= T_SYNCMODE; 519 ti->period = sc->sc_minsync; 520 ti->offset = SPC_SYNC_REQ_ACK_OFS; 521 #else 522 ti->period = ti->offset = 0; 523 #endif 524 ti->width = 0; 525 } 526 527 sc->sc_state = SPC_IDLE; 528 } 529 530 void 531 mha_free_acb(sc, acb, flags) 532 struct mha_softc *sc; 533 struct acb *acb; 534 int flags; 535 { 536 int s; 537 538 s = splbio(); 539 540 acb->flags = 0; 541 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 542 543 /* 544 * If there were none, wake anybody waiting for one to come free, 545 * starting with queued entries. 546 */ 547 if (acb->chain.tqe_next == 0) 548 wakeup(&sc->free_list); 549 550 splx(s); 551 } 552 553 554 /* 556 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 557 */ 558 559 /* 560 * Expected sequence: 561 * 1) Command inserted into ready list 562 * 2) Command selected for execution 563 * 3) Command won arbitration and has selected target device 564 * 4) Send message out (identify message, eventually also sync.negotiations) 565 * 5) Send command 566 * 5a) Receive disconnect message, disconnect. 567 * 5b) Reselected by target 568 * 5c) Receive identify message from target. 569 * 6) Send or receive data 570 * 7) Receive status 571 * 8) Receive message (command complete etc.) 572 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 573 * Repeat 2-8 (no disconnects please...) 574 */ 575 576 /* 577 * Start a selection. This is used by mha_sched() to select an idle target, 578 * and by mha_done() to immediately reselect a target to get sense information. 579 */ 580 void 581 mhaselect(sc, target, lun, cmd, clen) 582 struct mha_softc *sc; 583 u_char target, lun; 584 u_char *cmd; 585 u_char clen; 586 { 587 #if 0 588 struct scsi_link *sc_link = acb->xs->sc_link; 589 #endif 590 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 591 int i; 592 int s; 593 594 s = splbio(); /* XXX */ 595 596 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 597 598 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 599 /* Now the command into the FIFO */ 600 WAIT; 601 #if 1 602 SPC_MISC(("[cmd:")); 603 for (i = 0; i < clen; i++) 604 { 605 unsigned c = cmd[i]; 606 if (i == 1) 607 c |= lun << 5; 608 SPC_MISC((" %02x", c)); 609 sc->sc_pcx[i] = c; 610 } 611 SPC_MISC(("], target=%d\n", target)); 612 #else 613 bcopy(cmd, sc->sc_pcx, clen); 614 #endif 615 if (NSR & 0x80) 616 panic("scsistart: already selected..."); 617 sc->sc_phase = COMMAND_PHASE; 618 619 /* new state ASP_SELECTING */ 620 sc->sc_state = SPC_SELECTING; 621 622 SIR = target; 623 #if 0 624 CMR = CMD_SELECT; 625 #else 626 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 627 #endif 628 splx(s); 629 } 630 631 #if 0 632 int 633 mha_reselect(sc, message) 634 struct mha_softc *sc; 635 u_char message; 636 { 637 u_char selid, target, lun; 638 struct acb *acb; 639 struct scsipi_link *sc_link; 640 struct spc_tinfo *ti; 641 642 /* 643 * The SCSI chip made a snapshot of the data bus while the reselection 644 * was being negotiated. This enables us to determine which target did 645 * the reselect. 646 */ 647 selid = sc->sc_selid & ~(1 << sc->sc_id); 648 if (selid & (selid - 1)) { 649 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 650 sc->sc_dev.dv_xname, selid); 651 SPC_BREAK(); 652 goto reset; 653 } 654 655 /* 656 * Search wait queue for disconnected cmd 657 * The list should be short, so I haven't bothered with 658 * any more sophisticated structures than a simple 659 * singly linked list. 660 */ 661 target = ffs(selid) - 1; 662 lun = message & 0x07; 663 for (acb = sc->nexus_list.tqh_first; acb != NULL; 664 acb = acb->chain.tqe_next) { 665 sc_link = acb->xs->sc_link; 666 if (sc_link->scsipi_scsi.target == target && 667 sc_link->scsipi_scsi.lun == lun) 668 break; 669 } 670 if (acb == NULL) { 671 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 672 sc->sc_dev.dv_xname, target, lun); 673 SPC_BREAK(); 674 goto abort; 675 } 676 677 /* Make this nexus active again. */ 678 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 679 sc->sc_state = SPC_HASNEXUS; 680 sc->sc_nexus = acb; 681 ti = &sc->sc_tinfo[target]; 682 ti->lubusy |= (1 << lun); 683 mha_setsync(sc, ti); 684 685 if (acb->flags & ACB_RESET) 686 mha_sched_msgout(sc, SEND_DEV_RESET); 687 else if (acb->flags & ACB_ABORTED) 688 mha_sched_msgout(sc, SEND_ABORT); 689 690 /* Do an implicit RESTORE POINTERS. */ 691 sc->sc_dp = acb->daddr; 692 sc->sc_dleft = acb->dleft; 693 sc->sc_cp = (u_char *)&acb->cmd; 694 sc->sc_cleft = acb->clen; 695 696 return (0); 697 698 reset: 699 mha_sched_msgout(sc, SEND_DEV_RESET); 700 return (1); 701 702 abort: 703 mha_sched_msgout(sc, SEND_ABORT); 704 return (1); 705 } 706 #endif 707 /* 708 * Start a SCSI-command 709 * This function is called by the higher level SCSI-driver to queue/run 710 * SCSI-commands. 711 */ 712 int 713 mha_scsi_cmd(xs) 714 struct scsipi_xfer *xs; 715 { 716 struct scsipi_link *sc_link = xs->sc_link; 717 struct mha_softc *sc = sc_link->adapter_softc; 718 struct acb *acb; 719 int s, flags; 720 721 SPC_TRACE(("[mha_scsi_cmd] ")); 722 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 723 sc_link->scsipi_scsi.target)); 724 725 flags = xs->xs_control; 726 727 /* Get a mha command block */ 728 s = splbio(); 729 acb = sc->free_list.tqh_first; 730 if (acb) { 731 TAILQ_REMOVE(&sc->free_list, acb, chain); 732 ACB_SETQ(acb, ACB_QNONE); 733 } 734 splx(s); 735 736 if (acb == NULL) { 737 SPC_MISC(("TRY_AGAIN_LATER")); 738 return TRY_AGAIN_LATER; 739 } 740 741 /* Initialize acb */ 742 acb->xs = xs; 743 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 744 acb->clen = xs->cmdlen; 745 acb->daddr = xs->data; 746 acb->dleft = xs->datalen; 747 acb->stat = 0; 748 749 s = splbio(); 750 ACB_SETQ(acb, ACB_QREADY); 751 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 752 #if 1 753 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 754 #endif 755 756 /* 757 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 758 */ 759 if (sc->sc_state == SPC_IDLE) 760 mha_sched(sc); 761 762 splx(s); 763 764 if (flags & XS_CTL_POLL) { 765 /* Not allowed to use interrupts, use polling instead */ 766 return mha_poll(sc, acb); 767 } 768 769 SPC_MISC(("SUCCESSFULLY_QUEUED")); 770 return SUCCESSFULLY_QUEUED; 771 } 772 773 /* 774 * Adjust transfer size in buffer structure 775 */ 776 void 777 mha_minphys(bp) 778 struct buf *bp; 779 { 780 781 SPC_TRACE(("mha_minphys ")); 782 minphys(bp); 783 } 784 785 /* 786 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 787 */ 788 int 789 mha_poll(sc, acb) 790 struct mha_softc *sc; 791 struct acb *acb; 792 { 793 struct scsipi_xfer *xs = acb->xs; 794 int count = xs->timeout * 100; 795 int s = splbio(); 796 797 SPC_TRACE(("[mha_poll] ")); 798 799 while (count) { 800 /* 801 * If we had interrupts enabled, would we 802 * have got an interrupt? 803 */ 804 if (SSR & SS_IREQUEST) 805 mhaintr(sc); 806 if ((xs->xs_status & XS_STS_DONE) != 0) 807 break; 808 DELAY(10); 809 #if 1 810 if (sc->sc_state == SPC_IDLE) { 811 SPC_TRACE(("[mha_poll: rescheduling] ")); 812 mha_sched(sc); 813 } 814 #endif 815 count--; 816 } 817 818 if (count == 0) { 819 SPC_MISC(("mha_poll: timeout")); 820 mha_timeout((caddr_t)acb); 821 } 822 splx(s); 823 return COMPLETE; 824 } 825 826 /* 828 * LOW LEVEL SCSI UTILITIES 829 */ 830 831 /* 832 * Set synchronous transfer offset and period. 833 */ 834 inline void 835 mha_setsync(sc, ti) 836 struct mha_softc *sc; 837 struct spc_tinfo *ti; 838 { 839 } 840 841 842 /* 844 * Schedule a SCSI operation. This has now been pulled out of the interrupt 845 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 846 * save us an unecessary interrupt just to get things going. Should only be 847 * called when state == SPC_IDLE and at bio pl. 848 */ 849 void 850 mha_sched(sc) 851 register struct mha_softc *sc; 852 { 853 struct scsipi_link *sc_link; 854 struct acb *acb; 855 int t; 856 857 SPC_TRACE(("[mha_sched] ")); 858 if (sc->sc_state != SPC_IDLE) 859 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 860 861 if (sc->sc_flags & SPC_ABORTING) 862 return; 863 864 /* 865 * Find first acb in ready queue that is for a target/lunit 866 * combinations that is not busy. 867 */ 868 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 869 struct spc_tinfo *ti; 870 sc_link = acb->xs->sc_link; 871 t = sc_link->scsipi_scsi.target; 872 ti = &sc->sc_tinfo[t]; 873 if (!(ti->lubusy & (1 << sc_link->scsipi_scsi.lun))) { 874 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 875 panic("mha: busy entry on ready list"); 876 TAILQ_REMOVE(&sc->ready_list, acb, chain); 877 ACB_SETQ(acb, ACB_QNONE); 878 sc->sc_nexus = acb; 879 sc->sc_flags = 0; 880 sc->sc_prevphase = INVALID_PHASE; 881 sc->sc_dp = acb->daddr; 882 sc->sc_dleft = acb->dleft; 883 ti->lubusy |= (1<<sc_link->scsipi_scsi.lun); 884 mhaselect(sc, t, sc_link->scsipi_scsi.lun, 885 (u_char *)&acb->cmd, acb->clen); 886 break; 887 } else { 888 SPC_MISC(("%d:%d busy\n", 889 sc_link->scsipi_scsi.target, 890 sc_link->scsipi_scsi.lun)); 891 } 892 } 893 } 894 895 void 897 mha_sense(sc, acb) 898 struct mha_softc *sc; 899 struct acb *acb; 900 { 901 struct scsipi_xfer *xs = acb->xs; 902 struct scsipi_link *sc_link = xs->sc_link; 903 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 904 struct scsipi_sense *ss = (void *)&acb->cmd; 905 906 SPC_MISC(("requesting sense ")); 907 /* Next, setup a request sense command block */ 908 bzero(ss, sizeof(*ss)); 909 ss->opcode = REQUEST_SENSE; 910 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 911 ss->length = sizeof(struct scsipi_sense_data); 912 acb->clen = sizeof(*ss); 913 acb->daddr = (char *)&xs->sense; 914 acb->dleft = sizeof(struct scsipi_sense_data); 915 acb->flags |= ACB_CHKSENSE; 916 ti->senses++; 917 if (acb->flags & ACB_QNEXUS) 918 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 919 if (acb == sc->sc_nexus) { 920 mhaselect(sc, sc_link->scsipi_scsi.target, 921 sc_link->scsipi_scsi.lun, 922 (void *)&acb->cmd, acb->clen); 923 } else { 924 mha_dequeue(sc, acb); 925 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 926 if (sc->sc_state == SPC_IDLE) 927 mha_sched(sc); 928 } 929 } 930 931 /* 932 * POST PROCESSING OF SCSI_CMD (usually current) 933 */ 934 void 935 mha_done(sc, acb) 936 struct mha_softc *sc; 937 struct acb *acb; 938 { 939 struct scsipi_xfer *xs = acb->xs; 940 struct scsipi_link *sc_link = xs->sc_link; 941 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 942 943 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 944 945 #if 1 946 untimeout(mha_timeout, acb); 947 #endif 948 949 /* 950 * Now, if we've come here with no error code, i.e. we've kept the 951 * initial XS_NOERROR, and the status code signals that we should 952 * check sense, we'll need to set up a request sense cmd block and 953 * push the command back into the ready queue *before* any other 954 * commands for this target/lunit, else we lose the sense info. 955 * We don't support chk sense conditions for the request sense cmd. 956 */ 957 if (xs->error == XS_NOERROR) { 958 if ((acb->flags & ACB_ABORTED) != 0) { 959 xs->error = XS_TIMEOUT; 960 } else if (acb->flags & ACB_CHKSENSE) { 961 xs->error = XS_SENSE; 962 } else { 963 switch (acb->stat & ST_MASK) { 964 case SCSI_CHECK: 965 { 966 struct scsipi_sense *ss = (void *)&acb->cmd; 967 SPC_MISC(("requesting sense ")); 968 /* First, save the return values */ 969 xs->resid = acb->dleft; 970 xs->status = acb->stat; 971 /* Next, setup a request sense command block */ 972 bzero(ss, sizeof(*ss)); 973 ss->opcode = REQUEST_SENSE; 974 /*ss->byte2 = sc_link->lun << 5;*/ 975 ss->length = sizeof(struct scsipi_sense_data); 976 acb->clen = sizeof(*ss); 977 acb->daddr = (char *)&xs->sense; 978 acb->dleft = sizeof(struct scsipi_sense_data); 979 acb->flags |= ACB_CHKSENSE; 980 /*XXX - must take off queue here */ 981 if (acb != sc->sc_nexus) { 982 panic("%s: mha_sched: floating acb %p", 983 sc->sc_dev.dv_xname, acb); 984 } 985 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 986 ACB_SETQ(acb, ACB_QREADY); 987 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 988 ti->senses++; 989 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 990 if (sc->sc_nexus == acb) { 991 sc->sc_nexus = NULL; 992 sc->sc_state = SPC_IDLE; 993 mha_sched(sc); 994 } 995 #if 0 996 mha_sense(sc, acb); 997 #endif 998 return; 999 } 1000 case SCSI_BUSY: 1001 xs->error = XS_BUSY; 1002 break; 1003 case SCSI_OK: 1004 xs->resid = acb->dleft; 1005 break; 1006 default: 1007 xs->error = XS_DRIVER_STUFFUP; 1008 #if SPC_DEBUG 1009 printf("%s: mha_done: bad stat 0x%x\n", 1010 sc->sc_dev.dv_xname, acb->stat); 1011 #endif 1012 break; 1013 } 1014 } 1015 } 1016 1017 xs->xs_status |= XS_STS_DONE; 1018 1019 #if SPC_DEBUG 1020 if ((mha_debug & SPC_SHOWMISC) != 0) { 1021 if (xs->resid != 0) 1022 printf("resid=%d ", xs->resid); 1023 if (xs->error == XS_SENSE) 1024 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 1025 else 1026 printf("error=%d\n", xs->error); 1027 } 1028 #endif 1029 1030 /* 1031 * Remove the ACB from whatever queue it's on. 1032 */ 1033 switch (acb->flags & ACB_QBITS) { 1034 case ACB_QNONE: 1035 if (acb != sc->sc_nexus) { 1036 panic("%s: floating acb", sc->sc_dev.dv_xname); 1037 } 1038 sc->sc_nexus = NULL; 1039 sc->sc_state = SPC_IDLE; 1040 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1041 mha_sched(sc); 1042 break; 1043 case ACB_QREADY: 1044 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1045 break; 1046 case ACB_QNEXUS: 1047 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1048 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1049 break; 1050 case ACB_QFREE: 1051 panic("%s: dequeue: busy acb on free list", 1052 sc->sc_dev.dv_xname); 1053 break; 1054 default: 1055 panic("%s: dequeue: unknown queue %d", 1056 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1057 } 1058 1059 /* Put it on the free list, and clear flags. */ 1060 #if 0 1061 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1062 acb->flags = ACB_QFREE; 1063 #else 1064 mha_free_acb(sc, acb, xs->xs_control); 1065 #endif 1066 1067 ti->cmds++; 1068 scsipi_done(xs); 1069 } 1070 1071 void 1072 mha_dequeue(sc, acb) 1073 struct mha_softc *sc; 1074 struct acb *acb; 1075 { 1076 1077 if (acb->flags & ACB_QNEXUS) { 1078 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1079 } else { 1080 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1081 } 1082 } 1083 1084 /* 1086 * INTERRUPT/PROTOCOL ENGINE 1087 */ 1088 1089 /* 1090 * Schedule an outgoing message by prioritizing it, and asserting 1091 * attention on the bus. We can only do this when we are the initiator 1092 * else there will be an illegal command interrupt. 1093 */ 1094 #define mha_sched_msgout(m) \ 1095 do { \ 1096 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1097 CMR = CMD_SET_ATN; \ 1098 sc->sc_msgpriq |= (m); \ 1099 } while (0) 1100 1101 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1102 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1103 #define ISEXTMSG(m) ((m) == 0x01) 1104 1105 /* 1106 * Precondition: 1107 * The SCSI bus is already in the MSGI phase and there is a message byte 1108 * on the bus, along with an asserted REQ signal. 1109 */ 1110 void 1111 mha_msgin(sc) 1112 register struct mha_softc *sc; 1113 { 1114 register int v; 1115 int n; 1116 1117 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1118 1119 /* 1120 * Prepare for a new message. A message should (according 1121 * to the SCSI standard) be transmitted in one single 1122 * MESSAGE_IN_PHASE. If we have been in some other phase, 1123 * then this is a new message. 1124 */ 1125 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1126 sc->sc_flags &= ~SPC_DROP_MSGI; 1127 sc->sc_imlen = 0; 1128 } 1129 1130 WAIT; 1131 1132 v = MBR; /* modified byte */ 1133 v = sc->sc_pcx[0]; 1134 1135 sc->sc_imess[sc->sc_imlen] = v; 1136 1137 /* 1138 * If we're going to reject the message, don't bother storing 1139 * the incoming bytes. But still, we need to ACK them. 1140 */ 1141 1142 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1143 CMR = CMD_SET_ATN; 1144 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1145 printf("<dropping msg byte %x>", 1146 sc->sc_imess[sc->sc_imlen]); 1147 return; 1148 } 1149 1150 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1151 mha_sched_msgout(SEND_REJECT); 1152 sc->sc_flags |= SPC_DROP_MSGI; 1153 } else { 1154 sc->sc_imlen++; 1155 /* 1156 * This testing is suboptimal, but most 1157 * messages will be of the one byte variety, so 1158 * it should not effect performance 1159 * significantly. 1160 */ 1161 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1162 goto gotit; 1163 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1164 goto gotit; 1165 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1166 sc->sc_imlen == sc->sc_imess[1] + 2) 1167 goto gotit; 1168 } 1169 #if 0 1170 /* Ack what we have so far */ 1171 ESPCMD(sc, ESPCMD_MSGOK); 1172 #endif 1173 return; 1174 1175 gotit: 1176 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1177 /* 1178 * Now we should have a complete message (1 byte, 2 byte 1179 * and moderately long extended messages). We only handle 1180 * extended messages which total length is shorter than 1181 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1182 */ 1183 if (sc->sc_state == SPC_HASNEXUS) { 1184 struct acb *acb = sc->sc_nexus; 1185 struct spc_tinfo *ti = 1186 &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1187 1188 switch (sc->sc_imess[0]) { 1189 case MSG_CMDCOMPLETE: 1190 SPC_MSGS(("cmdcomplete ")); 1191 if (sc->sc_dleft < 0) { 1192 struct scsipi_link *sc_link = acb->xs->sc_link; 1193 printf("mha: %d extra bytes from %d:%d\n", 1194 -sc->sc_dleft, 1195 sc_link->scsipi_scsi.target, 1196 sc_link->scsipi_scsi.lun); 1197 sc->sc_dleft = 0; 1198 } 1199 acb->xs->resid = acb->dleft = sc->sc_dleft; 1200 sc->sc_flags |= SPC_BUSFREE_OK; 1201 break; 1202 1203 case MSG_MESSAGE_REJECT: 1204 #if SPC_DEBUG 1205 if (mha_debug & SPC_SHOWMSGS) 1206 printf("%s: our msg rejected by target\n", 1207 sc->sc_dev.dv_xname); 1208 #endif 1209 #if 1 /* XXX - must remember last message */ 1210 scsi_print_addr(acb->xs->sc_link); 1211 printf("MSG_MESSAGE_REJECT>>"); 1212 #endif 1213 if (sc->sc_flags & SPC_SYNCHNEGO) { 1214 ti->period = ti->offset = 0; 1215 sc->sc_flags &= ~SPC_SYNCHNEGO; 1216 ti->flags &= ~T_NEGOTIATE; 1217 } 1218 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1219 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1220 mha_sched_msgout(SEND_ABORT); 1221 break; 1222 case MSG_NOOP: 1223 SPC_MSGS(("noop ")); 1224 break; 1225 case MSG_DISCONNECT: 1226 SPC_MSGS(("disconnect ")); 1227 ti->dconns++; 1228 sc->sc_flags |= SPC_DISCON; 1229 sc->sc_flags |= SPC_BUSFREE_OK; 1230 if ((acb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1231 break; 1232 /*FALLTHROUGH*/ 1233 case MSG_SAVEDATAPOINTER: 1234 SPC_MSGS(("save datapointer ")); 1235 acb->dleft = sc->sc_dleft; 1236 acb->daddr = sc->sc_dp; 1237 break; 1238 case MSG_RESTOREPOINTERS: 1239 SPC_MSGS(("restore datapointer ")); 1240 if (!acb) { 1241 mha_sched_msgout(SEND_ABORT); 1242 printf("%s: no DATAPOINTERs to restore\n", 1243 sc->sc_dev.dv_xname); 1244 break; 1245 } 1246 sc->sc_dp = acb->daddr; 1247 sc->sc_dleft = acb->dleft; 1248 break; 1249 case MSG_PARITY_ERROR: 1250 printf("%s:target%d: MSG_PARITY_ERROR\n", 1251 sc->sc_dev.dv_xname, 1252 acb->xs->sc_link->scsipi_scsi.target); 1253 break; 1254 case MSG_EXTENDED: 1255 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1256 switch (sc->sc_imess[2]) { 1257 case MSG_EXT_SDTR: 1258 SPC_MSGS(("SDTR period %d, offset %d ", 1259 sc->sc_imess[3], sc->sc_imess[4])); 1260 ti->period = sc->sc_imess[3]; 1261 ti->offset = sc->sc_imess[4]; 1262 if (sc->sc_minsync == 0) { 1263 /* We won't do synch */ 1264 ti->offset = 0; 1265 mha_sched_msgout(SEND_SDTR); 1266 } else if (ti->offset == 0) { 1267 printf("%s:%d: async\n", "mha", 1268 acb->xs->sc_link->scsipi_scsi.target); 1269 ti->offset = 0; 1270 sc->sc_flags &= ~SPC_SYNCHNEGO; 1271 } else if (ti->period > 124) { 1272 printf("%s:%d: async\n", "mha", 1273 acb->xs->sc_link->scsipi_scsi.target); 1274 ti->offset = 0; 1275 mha_sched_msgout(SEND_SDTR); 1276 } else { 1277 int r = 250/ti->period; 1278 int s = (100*250)/ti->period - 100*r; 1279 int p; 1280 #if 0 1281 p = mha_stp2cpb(sc, ti->period); 1282 ti->period = mha_cpb2stp(sc, p); 1283 #endif 1284 1285 #if SPC_DEBUG 1286 scsi_print_addr(acb->xs->sc_link); 1287 #endif 1288 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1289 /* Target initiated negotiation */ 1290 if (ti->flags & T_SYNCMODE) { 1291 ti->flags &= ~T_SYNCMODE; 1292 #if SPC_DEBUG 1293 printf("renegotiated "); 1294 #endif 1295 } 1296 TMR=TM_ASYNC; 1297 /* Clamp to our maxima */ 1298 if (ti->period < sc->sc_minsync) 1299 ti->period = sc->sc_minsync; 1300 if (ti->offset > 15) 1301 ti->offset = 15; 1302 mha_sched_msgout(SEND_SDTR); 1303 } else { 1304 /* we are sync */ 1305 sc->sc_flags &= ~SPC_SYNCHNEGO; 1306 TMR = TM_SYNC; 1307 ti->flags |= T_SYNCMODE; 1308 } 1309 #if SPC_DEBUG 1310 printf("max sync rate %d.%02dMb/s\n", 1311 r, s); 1312 #endif 1313 } 1314 ti->flags &= ~T_NEGOTIATE; 1315 break; 1316 default: /* Extended messages we don't handle */ 1317 CMR = CMD_SET_ATN; /* XXX? */ 1318 break; 1319 } 1320 break; 1321 default: 1322 SPC_MSGS(("ident ")); 1323 /* thanks for that ident... */ 1324 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1325 SPC_MISC(("unknown ")); 1326 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1327 CMR = CMD_SET_ATN; /* XXX? */ 1328 } 1329 break; 1330 } 1331 } else if (sc->sc_state == SPC_RESELECTED) { 1332 struct scsipi_link *sc_link = NULL; 1333 struct acb *acb; 1334 struct spc_tinfo *ti; 1335 u_char lunit; 1336 1337 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1338 SPC_MISC(("searching ")); 1339 /* 1340 * Search wait queue for disconnected cmd 1341 * The list should be short, so I haven't bothered with 1342 * any more sophisticated structures than a simple 1343 * singly linked list. 1344 */ 1345 lunit = sc->sc_imess[0] & 0x07; 1346 for (acb = sc->nexus_list.tqh_first; acb; 1347 acb = acb->chain.tqe_next) { 1348 sc_link = acb->xs->sc_link; 1349 if (sc_link->scsipi_scsi.lun == lunit && 1350 sc->sc_selid == (1<<sc_link->scsipi_scsi.target)) { 1351 TAILQ_REMOVE(&sc->nexus_list, acb, 1352 chain); 1353 ACB_SETQ(acb, ACB_QNONE); 1354 break; 1355 } 1356 } 1357 1358 if (!acb) { /* Invalid reselection! */ 1359 mha_sched_msgout(SEND_ABORT); 1360 printf("mha: invalid reselect (idbit=0x%2x)\n", 1361 sc->sc_selid); 1362 } else { /* Reestablish nexus */ 1363 /* 1364 * Setup driver data structures and 1365 * do an implicit RESTORE POINTERS 1366 */ 1367 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1368 sc->sc_nexus = acb; 1369 sc->sc_dp = acb->daddr; 1370 sc->sc_dleft = acb->dleft; 1371 sc->sc_tinfo[sc_link->scsipi_scsi.target].lubusy 1372 |= (1<<sc_link->scsipi_scsi.lun); 1373 if (ti->flags & T_SYNCMODE) { 1374 TMR = TM_SYNC; /* XXX */ 1375 } else { 1376 TMR = TM_ASYNC; 1377 } 1378 SPC_MISC(("... found acb")); 1379 sc->sc_state = SPC_HASNEXUS; 1380 } 1381 } else { 1382 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1383 sc->sc_dev.dv_xname, sc->sc_selid); 1384 mha_sched_msgout(SEND_DEV_RESET); 1385 } 1386 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1387 printf("%s: unexpected message in; will send DEV_RESET\n", 1388 sc->sc_dev.dv_xname); 1389 mha_sched_msgout(SEND_DEV_RESET); 1390 } 1391 1392 /* Ack last message byte */ 1393 #if 0 1394 ESPCMD(sc, ESPCMD_MSGOK); 1395 #endif 1396 1397 /* Done, reset message pointer. */ 1398 sc->sc_flags &= ~SPC_DROP_MSGI; 1399 sc->sc_imlen = 0; 1400 } 1401 1402 /* 1403 * Send the highest priority, scheduled message. 1404 */ 1405 void 1406 mha_msgout(sc) 1407 register struct mha_softc *sc; 1408 { 1409 struct spc_tinfo *ti; 1410 int n; 1411 1412 SPC_TRACE(("mha_msgout ")); 1413 1414 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1415 if (sc->sc_omp == sc->sc_omess) { 1416 /* 1417 * This is a retransmission. 1418 * 1419 * We get here if the target stayed in MESSAGE OUT 1420 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1421 * that all of the previously transmitted messages must 1422 * be sent again, in the same order. Therefore, we 1423 * requeue all the previously transmitted messages, and 1424 * start again from the top. Our simple priority 1425 * scheme keeps the messages in the right order. 1426 */ 1427 SPC_MISC(("retransmitting ")); 1428 sc->sc_msgpriq |= sc->sc_msgoutq; 1429 /* 1430 * Set ATN. If we're just sending a trivial 1-byte 1431 * message, we'll clear ATN later on anyway. 1432 */ 1433 CMR = CMD_SET_ATN; /* XXX? */ 1434 } else { 1435 /* This is a continuation of the previous message. */ 1436 n = sc->sc_omp - sc->sc_omess; 1437 goto nextbyte; 1438 } 1439 } 1440 1441 /* No messages transmitted so far. */ 1442 sc->sc_msgoutq = 0; 1443 sc->sc_lastmsg = 0; 1444 1445 nextmsg: 1446 /* Pick up highest priority message. */ 1447 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1448 sc->sc_msgpriq &= ~sc->sc_currmsg; 1449 sc->sc_msgoutq |= sc->sc_currmsg; 1450 1451 /* Build the outgoing message data. */ 1452 switch (sc->sc_currmsg) { 1453 case SEND_IDENTIFY: 1454 SPC_ASSERT(sc->sc_nexus != NULL); 1455 sc->sc_omess[0] = 1456 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1457 n = 1; 1458 break; 1459 1460 #if SPC_USE_SYNCHRONOUS 1461 case SEND_SDTR: 1462 SPC_ASSERT(sc->sc_nexus != NULL); 1463 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1464 sc->sc_omess[4] = MSG_EXTENDED; 1465 sc->sc_omess[3] = 3; 1466 sc->sc_omess[2] = MSG_EXT_SDTR; 1467 sc->sc_omess[1] = ti->period >> 2; 1468 sc->sc_omess[0] = ti->offset; 1469 n = 5; 1470 break; 1471 #endif 1472 1473 #if SPC_USE_WIDE 1474 case SEND_WDTR: 1475 SPC_ASSERT(sc->sc_nexus != NULL); 1476 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1477 sc->sc_omess[3] = MSG_EXTENDED; 1478 sc->sc_omess[2] = 2; 1479 sc->sc_omess[1] = MSG_EXT_WDTR; 1480 sc->sc_omess[0] = ti->width; 1481 n = 4; 1482 break; 1483 #endif 1484 1485 case SEND_DEV_RESET: 1486 sc->sc_flags |= SPC_ABORTING; 1487 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1488 n = 1; 1489 break; 1490 1491 case SEND_REJECT: 1492 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1493 n = 1; 1494 break; 1495 1496 case SEND_PARITY_ERROR: 1497 sc->sc_omess[0] = MSG_PARITY_ERROR; 1498 n = 1; 1499 break; 1500 1501 case SEND_INIT_DET_ERR: 1502 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1503 n = 1; 1504 break; 1505 1506 case SEND_ABORT: 1507 sc->sc_flags |= SPC_ABORTING; 1508 sc->sc_omess[0] = MSG_ABORT; 1509 n = 1; 1510 break; 1511 1512 default: 1513 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1514 sc->sc_dev.dv_xname); 1515 SPC_BREAK(); 1516 sc->sc_omess[0] = MSG_NOOP; 1517 n = 1; 1518 break; 1519 } 1520 sc->sc_omp = &sc->sc_omess[n]; 1521 1522 nextbyte: 1523 /* Send message bytes. */ 1524 /* send TRANSFER command. */ 1525 sc->sc_ps[3] = 1; 1526 sc->sc_ps[4] = n >> 8; 1527 sc->sc_pc[10] = n; 1528 sc->sc_ps[-1] = 0x000F; /* burst */ 1529 asm volatile ("nop"); 1530 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1531 for (;;) { 1532 if ((SSR & SS_BUSY) != 0) 1533 break; 1534 if (SSR & SS_IREQUEST) 1535 goto out; 1536 } 1537 for (;;) { 1538 #if 0 1539 for (;;) { 1540 if ((PSNS & PSNS_REQ) != 0) 1541 break; 1542 /* Wait for REQINIT. XXX Need timeout. */ 1543 } 1544 #endif 1545 if (SSR & SS_IREQUEST) { 1546 /* 1547 * Target left MESSAGE OUT, possibly to reject 1548 * our message. 1549 * 1550 * If this is the last message being sent, then we 1551 * deassert ATN, since either the target is going to 1552 * ignore this message, or it's going to ask for a 1553 * retransmission via MESSAGE PARITY ERROR (in which 1554 * case we reassert ATN anyway). 1555 */ 1556 #if 0 1557 if (sc->sc_msgpriq == 0) 1558 CMR = CMD_RESET_ATN; 1559 #endif 1560 goto out; 1561 } 1562 1563 #if 0 1564 /* Clear ATN before last byte if this is the last message. */ 1565 if (n == 1 && sc->sc_msgpriq == 0) 1566 CMR = CMD_RESET_ATN; 1567 #endif 1568 1569 while ((SSR & SS_DREG_FULL) != 0) 1570 ; 1571 /* Send message byte. */ 1572 sc->sc_pc[0] = *--sc->sc_omp; 1573 --n; 1574 /* Keep track of the last message we've sent any bytes of. */ 1575 sc->sc_lastmsg = sc->sc_currmsg; 1576 1577 if (n == 0) 1578 break; 1579 } 1580 1581 /* We get here only if the entire message has been transmitted. */ 1582 if (sc->sc_msgpriq != 0) { 1583 /* There are more outgoing messages. */ 1584 goto nextmsg; 1585 } 1586 1587 /* 1588 * The last message has been transmitted. We need to remember the last 1589 * message transmitted (in case the target switches to MESSAGE IN phase 1590 * and sends a MESSAGE REJECT), and the list of messages transmitted 1591 * this time around (in case the target stays in MESSAGE OUT phase to 1592 * request a retransmit). 1593 */ 1594 1595 out: 1596 /* Disable REQ/ACK protocol. */ 1597 } 1598 1599 1600 /*************************************************************** 1602 * 1603 * datain/dataout 1604 * 1605 */ 1606 1607 int 1608 mha_datain_pio(sc, p, n) 1609 register struct mha_softc *sc; 1610 u_char *p; 1611 int n; 1612 { 1613 u_short d; 1614 int a; 1615 int total_n = n; 1616 1617 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1618 1619 WAIT; 1620 sc->sc_ps[3] = 1; 1621 sc->sc_ps[4] = n >> 8; 1622 sc->sc_pc[10] = n; 1623 /* $BHa$7$-%=%U%HE>Aw(B */ 1624 CMR = CMD_RECEIVE_TO_MPU; 1625 for (;;) { 1626 a = SSR; 1627 if (a & 0x04) { 1628 d = sc->sc_ps[0]; 1629 *p++ = d >> 8; 1630 if (--n > 0) { 1631 *p++ = d; 1632 --n; 1633 } 1634 a = SSR; 1635 } 1636 if (a & 0x40) 1637 continue; 1638 if (a & 0x80) 1639 break; 1640 } 1641 SPC_TRACE(("...%d resd]", n)); 1642 return total_n - n; 1643 } 1644 1645 int 1646 mha_dataout_pio(sc, p, n) 1647 register struct mha_softc *sc; 1648 u_char *p; 1649 int n; 1650 { 1651 u_short d; 1652 int a; 1653 int total_n = n; 1654 1655 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1656 1657 WAIT; 1658 sc->sc_ps[3] = 1; 1659 sc->sc_ps[4] = n >> 8; 1660 sc->sc_pc[10] = n; 1661 /* $BHa$7$-%=%U%HE>Aw(B */ 1662 CMR = CMD_SEND_FROM_MPU; 1663 for (;;) { 1664 a = SSR; 1665 if (a & 0x04) { 1666 d = *p++ << 8; 1667 if (--n > 0) { 1668 d |= *p++; 1669 --n; 1670 } 1671 sc->sc_ps[0] = d; 1672 a = SSR; 1673 } 1674 if (a & 0x40) 1675 continue; 1676 if (a & 0x80) 1677 break; 1678 } 1679 SPC_TRACE(("...%d resd]", n)); 1680 return total_n - n; 1681 } 1682 1683 static int 1684 mha_dataio_dma(dw, cw, sc, p, n) 1685 int dw; /* DMA word */ 1686 int cw; /* CMR word */ 1687 register struct mha_softc *sc; 1688 u_char *p; 1689 int n; 1690 { 1691 char *paddr, *vaddr; 1692 1693 if (n > MAXBSIZE) 1694 panic("transfer size exceeds MAXBSIZE"); 1695 if (sc->sc_dmasize > 0) 1696 panic("DMA request while another DMA transfer is in pregress"); 1697 1698 if (cw == CMD_SEND_FROM_DMA) { 1699 memcpy(sc->sc_dmabuf, p, n); 1700 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1701 } else { 1702 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1703 } 1704 sc->sc_p = p; 1705 sc->sc_dmasize = n; 1706 1707 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1708 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1709 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1710 dw &= ~(1 << 3); 1711 #endif 1712 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1713 #if 0 1714 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1715 PCIA(); /* XXX */ 1716 #endif 1717 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1718 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1719 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1720 WAIT; 1721 sc->sc_ps[3] = 1; 1722 sc->sc_ps[4] = n >> 8; 1723 sc->sc_pc[10] = n; 1724 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1725 3 ... short bus cycle 1726 2 ... MAXIMUM XFER. 1727 1 ... BURST XFER. 1728 0 ... R/W */ 1729 sc->sc_ps[-1] = dw; /* burst */ 1730 asm volatile ("nop"); 1731 CMR = cw; /* receive to DMA */ 1732 return n; 1733 } 1734 int 1735 mha_dataout(sc, p, n) 1736 register struct mha_softc *sc; 1737 u_char *p; 1738 int n; 1739 { 1740 register struct acb *acb = sc->sc_nexus; 1741 1742 if (n == 0) 1743 return n; 1744 1745 if (n & 1) 1746 return mha_dataout_pio(sc, p, n); 1747 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1748 } 1749 1750 int 1752 mha_datain(sc, p, n) 1753 register struct mha_softc *sc; 1754 u_char *p; 1755 int n; 1756 { 1757 int ts; 1758 register struct acb *acb = sc->sc_nexus; 1759 char *paddr, *vaddr; 1760 1761 if (n == 0) 1762 return n; 1763 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1764 return mha_datain_pio(sc, p, n); 1765 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1766 } 1767 1768 1770 /* 1771 * Catch an interrupt from the adaptor 1772 */ 1773 /* 1774 * This is the workhorse routine of the driver. 1775 * Deficiencies (for now): 1776 * 1) always uses programmed I/O 1777 */ 1778 int 1779 mhaintr(arg) 1780 void *arg; 1781 { 1782 struct mha_softc *sc = arg; 1783 #if 0 1784 u_char ints; 1785 #endif 1786 struct acb *acb; 1787 struct scsipi_link *sc_link; 1788 struct spc_tinfo *ti; 1789 u_char ph; 1790 u_short r; 1791 int n; 1792 1793 #if 1 /* XXX called during attach? */ 1794 if (tmpsc != NULL) { 1795 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1796 sc = tmpsc; 1797 } else { 1798 #endif 1799 1800 #if 1 /* XXX */ 1801 } 1802 #endif 1803 1804 #if 0 1805 /* 1806 * $B3d$j9~$_6X;_$K$9$k(B 1807 */ 1808 SCTL &= ~SCTL_INTR_ENAB; 1809 #endif 1810 1811 SPC_TRACE(("[mhaintr]")); 1812 1813 loop: 1814 /* 1815 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1816 */ 1817 /* 1818 * First check for abnormal conditions, such as reset. 1819 */ 1820 #if 0 1821 #if 1 /* XXX? */ 1822 while (((ints = SSR) & SS_IREQUEST) == 0) 1823 delay(1); 1824 SPC_MISC(("ints = 0x%x ", ints)); 1825 #else /* usually? */ 1826 ints = SSR; 1827 #endif 1828 #endif 1829 while (SSR & SS_IREQUEST) { 1830 acb = sc->sc_nexus; 1831 r = ISCSR; 1832 SPC_MISC(("[r=0x%x]", r)); 1833 switch (r >> 8) { 1834 default: 1835 printf("[addr=%x\n" 1836 "result=0x%x\n" 1837 "cmd=0x%x\n" 1838 "ph=0x%x(ought to be %d)]\n", 1839 &ISCSR, 1840 r, 1841 acb->xs->cmd->opcode, 1842 SCR, sc->sc_phase); 1843 panic("unexpected result."); 1844 case 0x82: /* selection timeout */ 1845 SPC_MISC(("selection timeout ")); 1846 sc->sc_phase = BUSFREE_PHASE; 1847 SPC_ASSERT(sc->sc_nexus != NULL); 1848 acb = sc->sc_nexus; 1849 delay(250); 1850 acb->xs->error = XS_SELTIMEOUT; 1851 mha_done(sc, acb); 1852 continue; /* XXX ??? msaitoh */ 1853 case 0x60: /* command completed */ 1854 sc->sc_spcinitialized++; 1855 if (sc->sc_phase == BUSFREE_PHASE) 1856 continue; 1857 ph = SCR; 1858 if (ph & PSNS_ACK) { 1859 int s; 1860 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1861 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1862 ph & PHASE_MASK, sc->sc_phase)); 1863 #if 0 1864 /* switch (sc->sc_phase) {*/ 1865 #else 1866 switch (ph & PHASE_MASK) { 1867 #endif 1868 case STATUS_PHASE: 1869 if (sc->sc_state != SPC_HASNEXUS) 1870 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1871 sc->sc_state); 1872 SPC_ASSERT(sc->sc_nexus != NULL); 1873 acb = sc->sc_nexus; 1874 WAIT; 1875 s = MBR; 1876 SPC_ASSERT(s == 1); 1877 acb->stat = sc->sc_pcx[0]; /* XXX */ 1878 SPC_MISC(("stat=0x%02x ", acb->stat)); 1879 sc->sc_prevphase = STATUS_PHASE; 1880 break; 1881 case MESSAGE_IN_PHASE: 1882 mha_msgin(sc); 1883 sc->sc_prevphase = MESSAGE_IN_PHASE; 1884 /* thru */ 1885 case DATA_IN_PHASE: 1886 if (sc->sc_dmasize == 0) 1887 break; 1888 bus_dmamap_sync(sc->sc_dmat, 1889 sc->sc_dmamap, 1890 0, sc->sc_dmasize, 1891 BUS_DMASYNC_POSTREAD); 1892 memcpy(sc->sc_p, sc->sc_dmabuf, 1893 sc->sc_dmasize); 1894 sc->sc_dmasize = 0; 1895 break; 1896 case DATA_OUT_PHASE: 1897 if (sc->sc_dmasize == 0) 1898 break; 1899 bus_dmamap_sync(sc->sc_dmat, 1900 sc->sc_dmamap, 1901 0, sc->sc_dmasize, 1902 BUS_DMASYNC_POSTWRITE); 1903 sc->sc_dmasize = 0; 1904 break; 1905 } 1906 WAIT; 1907 CMR = CMD_RESET_ACK; /* reset ack */ 1908 /*mha_done(sc, acb); XXX */ 1909 continue; 1910 } else if (NSR & 0x80) { /* nexus */ 1911 #if 1 1912 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1913 sc->sc_state = SPC_HASNEXUS; 1914 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1915 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1916 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1917 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1918 WAIT; 1919 if (SSR & SS_IREQUEST) 1920 continue; 1921 switch (sc->sc_phase) { 1922 default: 1923 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1924 case MESSAGE_IN_PHASE: 1925 /* $B2?$b$7$J$$(B */ 1926 continue; 1927 case STATUS_PHASE: 1928 sc->sc_phase = MESSAGE_IN_PHASE; 1929 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1930 continue; 1931 case DATA_IN_PHASE: 1932 sc->sc_prevphase = DATA_IN_PHASE; 1933 if (sc->sc_dleft == 0) { 1934 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1935 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1936 sc->sc_phase = STATUS_PHASE; 1937 CMR = CMD_RECEIVE_STS; /* receive sts */ 1938 continue; 1939 } 1940 n = mha_datain(sc, sc->sc_dp, 1941 sc->sc_dleft); 1942 sc->sc_dp += n; 1943 sc->sc_dleft -= n; 1944 continue; 1945 case DATA_OUT_PHASE: 1946 sc->sc_prevphase = DATA_OUT_PHASE; 1947 if (sc->sc_dleft == 0) { 1948 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1949 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1950 sc->sc_phase = STATUS_PHASE; 1951 CMR = CMD_RECEIVE_STS; /* receive sts */ 1952 continue; 1953 } 1954 /* data phase $B$NB3$-$r$d$m$&(B */ 1955 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1956 sc->sc_dp += n; 1957 sc->sc_dleft -= n; 1958 continue; 1959 case COMMAND_PHASE: 1960 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1961 if (acb->dleft) { 1962 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1963 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1964 sc->sc_phase = DATA_IN_PHASE; 1965 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1966 sc->sc_dp += n; 1967 sc->sc_dleft -= n; 1968 } 1969 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1970 sc->sc_phase = DATA_OUT_PHASE; 1971 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1972 sc->sc_dp += n; 1973 sc->sc_dleft -= n; 1974 } 1975 continue; 1976 } 1977 else { 1978 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1979 WAIT; 1980 sc->sc_phase = STATUS_PHASE; 1981 CMR = CMD_RECEIVE_STS; /* receive sts */ 1982 continue; 1983 } 1984 } 1985 #endif 1986 } 1987 continue; 1988 case 0x31: /* disconnected in xfer progress. */ 1989 SPC_MISC(("[0x31]")); 1990 case 0x70: /* disconnected. */ 1991 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1992 sc->sc_phase = BUSFREE_PHASE; 1993 sc->sc_state = SPC_IDLE; 1994 #if 1 1995 acb = sc->sc_nexus; 1996 SPC_ASSERT(sc->sc_nexus != NULL); 1997 acb->xs->error = XS_NOERROR; 1998 mha_done(sc, acb); 1999 #else 2000 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 2001 mha_sched(sc); 2002 #endif 2003 continue; 2004 case 0x32: /* phase error in xfer progress. */ 2005 SPC_MISC(("[0x32]")); 2006 #if 0 2007 case 0x65: /* invalid command. 2008 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 2009 $B26$K$OA4$/M}2r$G$-$J$$(B */ 2010 #if 1 2011 SPC_MISC(("[0x%04x]", r)); 2012 #endif 2013 #endif 2014 case 0x54: /* initial-phase error. */ 2015 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 2016 NSR, 2017 SCR, sc->sc_phase)); 2018 /* thru */ 2019 case 0x71: /* assert req */ 2020 WAIT; 2021 if (SSR & 0x40) { 2022 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 2023 SSR, r, NSR, SCR); 2024 WAIT; 2025 } 2026 ph = SCR; 2027 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 2028 sc->sc_state = SPC_HASNEXUS; 2029 } 2030 if (ph & 0x80) { 2031 switch (ph & PHASE_MASK) { 2032 default: 2033 printf("phase = %x\n", ph); 2034 panic("assert req: the phase I don't know!"); 2035 case DATA_IN_PHASE: 2036 sc->sc_prevphase = DATA_IN_PHASE; 2037 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 2038 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 2039 sc->sc_dp += n; 2040 sc->sc_dleft -= n; 2041 SPC_MISC(("done\n")); 2042 continue; 2043 case DATA_OUT_PHASE: 2044 sc->sc_prevphase = DATA_OUT_PHASE; 2045 SPC_MISC(("DATAOUT\n")); 2046 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 2047 sc->sc_dp += n; 2048 sc->sc_dleft -= n; 2049 continue; 2050 case STATUS_PHASE: 2051 sc->sc_phase = STATUS_PHASE; 2052 SPC_MISC(("[RECV_STS]")); 2053 WAIT; 2054 CMR = CMD_RECEIVE_STS; /* receive sts */ 2055 continue; 2056 case MESSAGE_IN_PHASE: 2057 sc->sc_phase = MESSAGE_IN_PHASE; 2058 WAIT; 2059 CMR = CMD_RECEIVE_MSG; 2060 continue; 2061 } 2062 } 2063 continue; 2064 } 2065 } 2066 } 2067 2068 void 2069 mha_abort(sc, acb) 2070 struct mha_softc *sc; 2071 struct acb *acb; 2072 { 2073 acb->flags |= ACB_ABORTED; 2074 2075 if (acb == sc->sc_nexus) { 2076 /* 2077 * If we're still selecting, the message will be scheduled 2078 * after selection is complete. 2079 */ 2080 if (sc->sc_state == SPC_HASNEXUS) { 2081 sc->sc_flags |= SPC_ABORTING; 2082 mha_sched_msgout(SEND_ABORT); 2083 } 2084 } else { 2085 if (sc->sc_state == SPC_IDLE) 2086 mha_sched(sc); 2087 } 2088 } 2089 2090 void 2091 mha_timeout(arg) 2092 void *arg; 2093 { 2094 int s = splbio(); 2095 struct acb *acb = (struct acb *)arg; 2096 struct scsipi_xfer *xs = acb->xs; 2097 struct scsipi_link *sc_link = xs->sc_link; 2098 struct mha_softc *sc = sc_link->adapter_softc; 2099 2100 scsi_print_addr(sc_link); 2101 again: 2102 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2103 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2104 sc->sc_dev.dv_xname, 2105 acb, acb->flags, acb->dleft, acb->stat, 2106 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2107 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2108 ); 2109 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2110 panic("timeout, ouch!"); 2111 2112 if (acb->flags & ACB_ABORTED) { 2113 /* abort timed out */ 2114 printf(" AGAIN\n"); 2115 #if 0 2116 mha_init(sc, 1); /* XXX 1?*/ 2117 #endif 2118 } else { 2119 /* abort the operation that has timed out */ 2120 printf("\n"); 2121 xs->error = XS_TIMEOUT; 2122 mha_abort(sc, acb); 2123 } 2124 2125 splx(s); 2126 } 2127 2128 #if SPC_DEBUG 2130 /* 2131 * The following functions are mostly used for debugging purposes, either 2132 * directly called from the driver or from the kernel debugger. 2133 */ 2134 2135 void 2136 mha_show_scsi_cmd(acb) 2137 struct acb *acb; 2138 { 2139 u_char *b = (u_char *)&acb->cmd; 2140 struct scsipi_link *sc_link = acb->xs->sc_link; 2141 int i; 2142 2143 scsi_print_addr(sc_link); 2144 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2145 for (i = 0; i < acb->clen; i++) { 2146 if (i) 2147 printf(","); 2148 printf("%x", b[i]); 2149 } 2150 printf("\n"); 2151 } else 2152 printf("RESET\n"); 2153 } 2154 2155 void 2156 mha_print_acb(acb) 2157 struct acb *acb; 2158 { 2159 2160 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2161 printf(" dp=%x dleft=%d stat=%x\n", 2162 (long)acb->daddr, acb->dleft, acb->stat); 2163 mha_show_scsi_cmd(acb); 2164 } 2165 2166 void 2167 mha_print_active_acb() 2168 { 2169 struct acb *acb; 2170 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2171 2172 printf("ready list:\n"); 2173 for (acb = sc->ready_list.tqh_first; acb != NULL; 2174 acb = acb->chain.tqe_next) 2175 mha_print_acb(acb); 2176 printf("nexus:\n"); 2177 if (sc->sc_nexus != NULL) 2178 mha_print_acb(sc->sc_nexus); 2179 printf("nexus list:\n"); 2180 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2181 acb = acb->chain.tqe_next) 2182 mha_print_acb(acb); 2183 } 2184 2185 void 2186 mha_dump_driver(sc) 2187 struct mha_softc *sc; 2188 { 2189 struct spc_tinfo *ti; 2190 int i; 2191 2192 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2193 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2194 sc->sc_state, sc->sc_imess[0], 2195 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2196 for (i = 0; i < 7; i++) { 2197 ti = &sc->sc_tinfo[i]; 2198 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2199 i, ti->cmds, ti->dconns, ti->touts); 2200 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2201 } 2202 } 2203 #endif 2204
Indexes created Sat Oct 18 17:09:52 GMT 2025