mha.c revision 1.18
1 /* $NetBSD: mha.c,v 1.18 1999/11/18 15:03:03 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 190 #define Debugger() panic("should call debugger here (mha.c)") 191 #endif /* ! DDB */ 192 193 194 #if SPC_DEBUG 195 #define SPC_SHOWACBS 0x01 196 #define SPC_SHOWINTS 0x02 197 #define SPC_SHOWCMDS 0x04 198 #define SPC_SHOWMISC 0x08 199 #define SPC_SHOWTRAC 0x10 200 #define SPC_SHOWSTART 0x20 201 #define SPC_SHOWPHASE 0x40 202 #define SPC_SHOWDMA 0x80 203 #define SPC_SHOWCCMDS 0x100 204 #define SPC_SHOWMSGS 0x200 205 #define SPC_DOBREAK 0x400 206 207 int mha_debug = 208 #if 0 209 0x7FF; 210 #else 211 SPC_SHOWSTART|SPC_SHOWTRAC; 212 #endif 213 214 215 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 216 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 217 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 218 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 219 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 220 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 221 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 222 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 223 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 224 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 225 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 226 #else 227 #define SPC_ACBS(str) 228 #define SPC_MISC(str) 229 #define SPC_INTS(str) 230 #define SPC_TRACE(str) 231 #define SPC_CMDS(str) 232 #define SPC_START(str) 233 #define SPC_PHASE(str) 234 #define SPC_DMA(str) 235 #define SPC_MSGS(str) 236 #define SPC_BREAK() 237 #define SPC_ASSERT(x) 238 #endif 239 240 int mhamatch __P((struct device *, struct cfdata *, void *)); 241 void mhaattach __P((struct device *, struct device *, void *)); 242 void mhaselect __P((struct mha_softc *, 243 u_char, u_char, u_char *, u_char)); 244 void mha_reset __P((struct mha_softc *)); 245 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 246 void mha_sense __P((struct mha_softc *, struct acb *)); 247 void mha_msgin __P((struct mha_softc *)); 248 void mha_msgout __P((struct mha_softc *)); 249 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 250 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_dataout __P((struct mha_softc *, u_char *, int)); 252 int mha_datain __P((struct mha_softc *, u_char *, int)); 253 void mha_abort __P((struct mha_softc *, struct acb *)); 254 void mha_init __P((struct mha_softc *)); 255 int mha_scsi_cmd __P((struct scsipi_xfer *)); 256 int mha_poll __P((struct mha_softc *, struct acb *)); 257 void mha_sched __P((struct mha_softc *)); 258 void mha_done __P((struct mha_softc *, struct acb *)); 259 int mhaintr __P((void*)); 260 void mha_timeout __P((void *)); 261 void mha_minphys __P((struct buf *)); 262 void mha_dequeue __P((struct mha_softc *, struct acb *)); 263 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 264 #if SPC_DEBUG 265 void mha_print_acb __P((struct acb *)); 266 void mha_show_scsi_cmd __P((struct acb *)); 267 void mha_print_active_acb __P((void)); 268 void mha_dump_driver __P((struct mha_softc *)); 269 #endif 270 271 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 272 273 struct cfattach mha_ca = { 274 sizeof(struct mha_softc), mhamatch, mhaattach 275 }; 276 277 extern struct cfdriver mha_cd; 278 279 struct scsipi_device mha_dev = { 280 NULL, /* Use default error handler */ 281 NULL, /* have a queue, served by this */ 282 NULL, /* have no async handler */ 283 NULL, /* Use default 'done' routine */ 284 }; 285 286 /* 288 * returns non-zero value if a controller is found. 289 */ 290 int 291 mhamatch(parent, cf, aux) 292 struct device *parent; 293 struct cfdata *cf; 294 void *aux; 295 { 296 struct intio_attach_args *ia = aux; 297 bus_space_tag_t iot = ia->ia_bst; 298 bus_space_handle_t ioh; 299 300 ia->ia_size=0x20; 301 if (ia->ia_addr != 0xea0000) 302 return 0; 303 304 if (intio_map_allocate_region(parent->dv_parent, ia, 305 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 306 return 0; 307 308 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 309 &ioh) < 0) 310 return 0; 311 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 312 return 0; 313 bus_space_unmap(iot, ioh, 0x20); 314 315 return 1; 316 } 317 318 /* 319 */ 320 321 struct mha_softc *tmpsc; 322 323 void 324 mhaattach(parent, self, aux) 325 struct device *parent, *self; 326 void *aux; 327 { 328 struct mha_softc *sc = (void *)self; 329 struct intio_attach_args *ia = aux; 330 331 tmpsc = sc; /* XXX */ 332 333 SPC_TRACE(("mhaattach ")); 334 sc->sc_state = SPC_INIT; 335 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 336 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 337 /* XXX: FAKE */ 338 sc->sc_dmat = ia->ia_dmat; 339 340 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 341 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 342 sc->sc_pcx = &sc->sc_pc[0x10]; 343 344 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 345 346 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 347 348 mha_init(sc); /* Init chip and driver */ 349 350 sc->sc_phase = BUSFREE_PHASE; 351 352 /* 353 * Fill in the adapter. 354 */ 355 sc->sc_adapter.scsipi_cmd = mha_scsi_cmd; 356 sc->sc_adapter.scsipi_minphys = mha_minphys; 357 358 /* 359 * Fill in the prototype scsi_link 360 */ 361 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 362 sc->sc_link.adapter_softc = sc; 363 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 364 sc->sc_link.adapter = &sc->sc_adapter; 365 sc->sc_link.device = &mha_dev; 366 sc->sc_link.openings = 2; 367 sc->sc_link.scsipi_scsi.max_target = 7; 368 sc->sc_link.scsipi_scsi.max_lun = 7; 369 sc->sc_link.type = BUS_SCSI; 370 371 sc->sc_spcinitialized = 0; 372 WAR = WA_INITWIN; 373 #if 1 374 CCR = 0x14; 375 OIR = sc->sc_id; 376 AMR = 0x00; 377 SMR = 0x00; 378 SRR = 0x00; 379 STR = 0x20; 380 RTR = 0x40; 381 ATR = 0x01; 382 PER = 0xc9; 383 #endif 384 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 385 #if 1 386 GLR = 0x00; 387 DMR = 0x30; 388 IMR = 0x00; 389 #endif 390 WAR = WA_MCSBUFWIN; 391 392 /* drop off */ 393 while (SSR & SS_IREQUEST) 394 { 395 unsigned a = ISCSR; 396 } 397 398 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 399 400 SPC_TRACE(("waiting for intr...")); 401 while (!(SSR & SS_IREQUEST)) 402 delay(10); 403 mhaintr (sc); 404 405 tmpsc = NULL; 406 407 config_found(self, &sc->sc_link, scsiprint); 408 } 409 410 #if 0 411 void 412 mha_reset(sc) 413 struct mha_softc *sc; 414 { 415 u_short dummy; 416 printf("reset..."); 417 CMR = CMD_SOFT_RESET; 418 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 419 dummy = sc->sc_ps[-1]; 420 dummy = sc->sc_ps[-1]; 421 dummy = sc->sc_ps[-1]; 422 dummy = sc->sc_ps[-1]; 423 asm volatile ("nop"); 424 CMR = CMD_SOFT_RESET; 425 sc->sc_spcinitialized = 0; 426 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 427 while(!sc->sc_spcinitialized); 428 429 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 430 printf("done.\n"); 431 } 432 #endif 433 434 /* 435 * Initialize mha SCSI driver. 436 */ 437 void 438 mha_init(sc) 439 struct mha_softc *sc; 440 { 441 struct acb *acb; 442 int r; 443 444 if (sc->sc_state == SPC_INIT) { 445 /* First time through; initialize. */ 446 TAILQ_INIT(&sc->ready_list); 447 TAILQ_INIT(&sc->nexus_list); 448 TAILQ_INIT(&sc->free_list); 449 sc->sc_nexus = NULL; 450 acb = sc->sc_acb; 451 bzero(acb, sizeof(sc->sc_acb)); 452 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 453 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 454 acb++; 455 } 456 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 457 458 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 459 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 460 BUS_DMA_NOWAIT); 461 if (r) 462 panic("mha_init: cannot allocate dma memory"); 463 if (sc->sc_ndmasegs != 1) 464 panic("mha_init: number of segment > 1??"); 465 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 466 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 467 if (r) 468 panic("mha_init: cannot map dma memory"); 469 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 470 MAXBSIZE, 0, BUS_DMA_NOWAIT, 471 &sc->sc_dmamap); 472 if (r) 473 panic("mha_init: cannot create dmamap structure"); 474 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 475 sc->sc_dmabuf, MAXBSIZE, NULL, 476 BUS_DMA_NOWAIT); 477 if (r) 478 panic("mha_init: cannot load dma buffer into dmamap"); 479 sc->sc_p = 0; 480 } else { 481 /* Cancel any active commands. */ 482 sc->sc_flags |= SPC_ABORTING; 483 sc->sc_state = SPC_IDLE; 484 if ((acb = sc->sc_nexus) != NULL) { 485 acb->xs->error = XS_DRIVER_STUFFUP; 486 mha_done(sc, acb); 487 } 488 while ((acb = sc->nexus_list.tqh_first) != NULL) { 489 acb->xs->error = XS_DRIVER_STUFFUP; 490 mha_done(sc, acb); 491 } 492 } 493 494 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 495 for (r = 0; r < 8; r++) { 496 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 497 498 ti->flags = 0; 499 #if SPC_USE_SYNCHRONOUS 500 ti->flags |= T_SYNCMODE; 501 ti->period = sc->sc_minsync; 502 ti->offset = SPC_SYNC_REQ_ACK_OFS; 503 #else 504 ti->period = ti->offset = 0; 505 #endif 506 ti->width = 0; 507 } 508 509 sc->sc_state = SPC_IDLE; 510 } 511 512 void 513 mha_free_acb(sc, acb, flags) 514 struct mha_softc *sc; 515 struct acb *acb; 516 int flags; 517 { 518 int s; 519 520 s = splbio(); 521 522 acb->flags = 0; 523 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 524 525 /* 526 * If there were none, wake anybody waiting for one to come free, 527 * starting with queued entries. 528 */ 529 if (acb->chain.tqe_next == 0) 530 wakeup(&sc->free_list); 531 532 splx(s); 533 } 534 535 536 /* 538 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 539 */ 540 541 /* 542 * Expected sequence: 543 * 1) Command inserted into ready list 544 * 2) Command selected for execution 545 * 3) Command won arbitration and has selected target device 546 * 4) Send message out (identify message, eventually also sync.negotiations) 547 * 5) Send command 548 * 5a) Receive disconnect message, disconnect. 549 * 5b) Reselected by target 550 * 5c) Receive identify message from target. 551 * 6) Send or receive data 552 * 7) Receive status 553 * 8) Receive message (command complete etc.) 554 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 555 * Repeat 2-8 (no disconnects please...) 556 */ 557 558 /* 559 * Start a selection. This is used by mha_sched() to select an idle target, 560 * and by mha_done() to immediately reselect a target to get sense information. 561 */ 562 void 563 mhaselect(sc, target, lun, cmd, clen) 564 struct mha_softc *sc; 565 u_char target, lun; 566 u_char *cmd; 567 u_char clen; 568 { 569 #if 0 570 struct scsi_link *sc_link = acb->xs->sc_link; 571 #endif 572 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 573 int i; 574 int s; 575 576 s = splbio(); /* XXX */ 577 578 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 579 580 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 581 /* Now the command into the FIFO */ 582 WAIT; 583 #if 1 584 SPC_MISC(("[cmd:")); 585 for (i = 0; i < clen; i++) 586 { 587 unsigned c = cmd[i]; 588 if (i == 1) 589 c |= lun << 5; 590 SPC_MISC((" %02x", c)); 591 sc->sc_pcx[i] = c; 592 } 593 SPC_MISC(("], target=%d\n", target)); 594 #else 595 bcopy(cmd, sc->sc_pcx, clen); 596 #endif 597 if (NSR & 0x80) 598 panic("scsistart: already selected..."); 599 sc->sc_phase = COMMAND_PHASE; 600 601 /* new state ASP_SELECTING */ 602 sc->sc_state = SPC_SELECTING; 603 604 SIR = target; 605 #if 0 606 CMR = CMD_SELECT; 607 #else 608 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 609 #endif 610 splx(s); 611 } 612 613 #if 0 614 int 615 mha_reselect(sc, message) 616 struct mha_softc *sc; 617 u_char message; 618 { 619 u_char selid, target, lun; 620 struct acb *acb; 621 struct scsipi_link *sc_link; 622 struct spc_tinfo *ti; 623 624 /* 625 * The SCSI chip made a snapshot of the data bus while the reselection 626 * was being negotiated. This enables us to determine which target did 627 * the reselect. 628 */ 629 selid = sc->sc_selid & ~(1 << sc->sc_id); 630 if (selid & (selid - 1)) { 631 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 632 sc->sc_dev.dv_xname, selid); 633 SPC_BREAK(); 634 goto reset; 635 } 636 637 /* 638 * Search wait queue for disconnected cmd 639 * The list should be short, so I haven't bothered with 640 * any more sophisticated structures than a simple 641 * singly linked list. 642 */ 643 target = ffs(selid) - 1; 644 lun = message & 0x07; 645 for (acb = sc->nexus_list.tqh_first; acb != NULL; 646 acb = acb->chain.tqe_next) { 647 sc_link = acb->xs->sc_link; 648 if (sc_link->scsipi_scsi.target == target && 649 sc_link->scsipi_scsi.lun == lun) 650 break; 651 } 652 if (acb == NULL) { 653 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 654 sc->sc_dev.dv_xname, target, lun); 655 SPC_BREAK(); 656 goto abort; 657 } 658 659 /* Make this nexus active again. */ 660 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 661 sc->sc_state = SPC_HASNEXUS; 662 sc->sc_nexus = acb; 663 ti = &sc->sc_tinfo[target]; 664 ti->lubusy |= (1 << lun); 665 mha_setsync(sc, ti); 666 667 if (acb->flags & ACB_RESET) 668 mha_sched_msgout(sc, SEND_DEV_RESET); 669 else if (acb->flags & ACB_ABORTED) 670 mha_sched_msgout(sc, SEND_ABORT); 671 672 /* Do an implicit RESTORE POINTERS. */ 673 sc->sc_dp = acb->daddr; 674 sc->sc_dleft = acb->dleft; 675 sc->sc_cp = (u_char *)&acb->cmd; 676 sc->sc_cleft = acb->clen; 677 678 return (0); 679 680 reset: 681 mha_sched_msgout(sc, SEND_DEV_RESET); 682 return (1); 683 684 abort: 685 mha_sched_msgout(sc, SEND_ABORT); 686 return (1); 687 } 688 #endif 689 /* 690 * Start a SCSI-command 691 * This function is called by the higher level SCSI-driver to queue/run 692 * SCSI-commands. 693 */ 694 int 695 mha_scsi_cmd(xs) 696 struct scsipi_xfer *xs; 697 { 698 struct scsipi_link *sc_link = xs->sc_link; 699 struct mha_softc *sc = sc_link->adapter_softc; 700 struct acb *acb; 701 int s, flags; 702 703 SPC_TRACE(("[mha_scsi_cmd] ")); 704 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 705 sc_link->scsipi_scsi.target)); 706 707 flags = xs->xs_control; 708 709 /* Get a mha command block */ 710 s = splbio(); 711 acb = sc->free_list.tqh_first; 712 if (acb) { 713 TAILQ_REMOVE(&sc->free_list, acb, chain); 714 ACB_SETQ(acb, ACB_QNONE); 715 } 716 splx(s); 717 718 if (acb == NULL) { 719 SPC_MISC(("TRY_AGAIN_LATER")); 720 return TRY_AGAIN_LATER; 721 } 722 723 /* Initialize acb */ 724 acb->xs = xs; 725 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 726 acb->clen = xs->cmdlen; 727 acb->daddr = xs->data; 728 acb->dleft = xs->datalen; 729 acb->stat = 0; 730 731 s = splbio(); 732 ACB_SETQ(acb, ACB_QREADY); 733 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 734 #if 1 735 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 736 #endif 737 738 /* 739 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 740 */ 741 if (sc->sc_state == SPC_IDLE) 742 mha_sched(sc); 743 744 splx(s); 745 746 if (flags & XS_CTL_POLL) { 747 /* Not allowed to use interrupts, use polling instead */ 748 return mha_poll(sc, acb); 749 } 750 751 SPC_MISC(("SUCCESSFULLY_QUEUED")); 752 return SUCCESSFULLY_QUEUED; 753 } 754 755 /* 756 * Adjust transfer size in buffer structure 757 */ 758 void 759 mha_minphys(bp) 760 struct buf *bp; 761 { 762 763 SPC_TRACE(("mha_minphys ")); 764 minphys(bp); 765 } 766 767 /* 768 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 769 */ 770 int 771 mha_poll(sc, acb) 772 struct mha_softc *sc; 773 struct acb *acb; 774 { 775 struct scsipi_xfer *xs = acb->xs; 776 int count = xs->timeout * 100; 777 int s = splbio(); 778 779 SPC_TRACE(("[mha_poll] ")); 780 781 while (count) { 782 /* 783 * If we had interrupts enabled, would we 784 * have got an interrupt? 785 */ 786 if (SSR & SS_IREQUEST) 787 mhaintr(sc); 788 if ((xs->xs_status & XS_STS_DONE) != 0) 789 break; 790 DELAY(10); 791 #if 1 792 if (sc->sc_state == SPC_IDLE) { 793 SPC_TRACE(("[mha_poll: rescheduling] ")); 794 mha_sched(sc); 795 } 796 #endif 797 count--; 798 } 799 800 if (count == 0) { 801 SPC_MISC(("mha_poll: timeout")); 802 mha_timeout((caddr_t)acb); 803 } 804 splx(s); 805 return COMPLETE; 806 } 807 808 /* 810 * LOW LEVEL SCSI UTILITIES 811 */ 812 813 /* 814 * Set synchronous transfer offset and period. 815 */ 816 inline void 817 mha_setsync(sc, ti) 818 struct mha_softc *sc; 819 struct spc_tinfo *ti; 820 { 821 } 822 823 824 /* 826 * Schedule a SCSI operation. This has now been pulled out of the interrupt 827 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 828 * save us an unecessary interrupt just to get things going. Should only be 829 * called when state == SPC_IDLE and at bio pl. 830 */ 831 void 832 mha_sched(sc) 833 register struct mha_softc *sc; 834 { 835 struct scsipi_link *sc_link; 836 struct acb *acb; 837 int t; 838 839 SPC_TRACE(("[mha_sched] ")); 840 if (sc->sc_state != SPC_IDLE) 841 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 842 843 if (sc->sc_flags & SPC_ABORTING) 844 return; 845 846 /* 847 * Find first acb in ready queue that is for a target/lunit 848 * combinations that is not busy. 849 */ 850 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 851 struct spc_tinfo *ti; 852 sc_link = acb->xs->sc_link; 853 t = sc_link->scsipi_scsi.target; 854 ti = &sc->sc_tinfo[t]; 855 if (!(ti->lubusy & (1 << sc_link->scsipi_scsi.lun))) { 856 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 857 panic("mha: busy entry on ready list"); 858 TAILQ_REMOVE(&sc->ready_list, acb, chain); 859 ACB_SETQ(acb, ACB_QNONE); 860 sc->sc_nexus = acb; 861 sc->sc_flags = 0; 862 sc->sc_prevphase = INVALID_PHASE; 863 sc->sc_dp = acb->daddr; 864 sc->sc_dleft = acb->dleft; 865 ti->lubusy |= (1<<sc_link->scsipi_scsi.lun); 866 mhaselect(sc, t, sc_link->scsipi_scsi.lun, 867 (u_char *)&acb->cmd, acb->clen); 868 break; 869 } else { 870 SPC_MISC(("%d:%d busy\n", 871 sc_link->scsipi_scsi.target, 872 sc_link->scsipi_scsi.lun)); 873 } 874 } 875 } 876 877 void 879 mha_sense(sc, acb) 880 struct mha_softc *sc; 881 struct acb *acb; 882 { 883 struct scsipi_xfer *xs = acb->xs; 884 struct scsipi_link *sc_link = xs->sc_link; 885 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 886 struct scsipi_sense *ss = (void *)&acb->cmd; 887 888 SPC_MISC(("requesting sense ")); 889 /* Next, setup a request sense command block */ 890 bzero(ss, sizeof(*ss)); 891 ss->opcode = REQUEST_SENSE; 892 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 893 ss->length = sizeof(struct scsipi_sense_data); 894 acb->clen = sizeof(*ss); 895 acb->daddr = (char *)&xs->sense; 896 acb->dleft = sizeof(struct scsipi_sense_data); 897 acb->flags |= ACB_CHKSENSE; 898 ti->senses++; 899 if (acb->flags & ACB_QNEXUS) 900 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 901 if (acb == sc->sc_nexus) { 902 mhaselect(sc, sc_link->scsipi_scsi.target, 903 sc_link->scsipi_scsi.lun, 904 (void *)&acb->cmd, acb->clen); 905 } else { 906 mha_dequeue(sc, acb); 907 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 908 if (sc->sc_state == SPC_IDLE) 909 mha_sched(sc); 910 } 911 } 912 913 /* 914 * POST PROCESSING OF SCSI_CMD (usually current) 915 */ 916 void 917 mha_done(sc, acb) 918 struct mha_softc *sc; 919 struct acb *acb; 920 { 921 struct scsipi_xfer *xs = acb->xs; 922 struct scsipi_link *sc_link = xs->sc_link; 923 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 924 925 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 926 927 #if 1 928 untimeout(mha_timeout, acb); 929 #endif 930 931 /* 932 * Now, if we've come here with no error code, i.e. we've kept the 933 * initial XS_NOERROR, and the status code signals that we should 934 * check sense, we'll need to set up a request sense cmd block and 935 * push the command back into the ready queue *before* any other 936 * commands for this target/lunit, else we lose the sense info. 937 * We don't support chk sense conditions for the request sense cmd. 938 */ 939 if (xs->error == XS_NOERROR) { 940 if ((acb->flags & ACB_ABORTED) != 0) { 941 xs->error = XS_TIMEOUT; 942 } else if (acb->flags & ACB_CHKSENSE) { 943 xs->error = XS_SENSE; 944 } else { 945 switch (acb->stat & ST_MASK) { 946 case SCSI_CHECK: 947 { 948 struct scsipi_sense *ss = (void *)&acb->cmd; 949 SPC_MISC(("requesting sense ")); 950 /* First, save the return values */ 951 xs->resid = acb->dleft; 952 xs->status = acb->stat; 953 /* Next, setup a request sense command block */ 954 bzero(ss, sizeof(*ss)); 955 ss->opcode = REQUEST_SENSE; 956 /*ss->byte2 = sc_link->lun << 5;*/ 957 ss->length = sizeof(struct scsipi_sense_data); 958 acb->clen = sizeof(*ss); 959 acb->daddr = (char *)&xs->sense; 960 acb->dleft = sizeof(struct scsipi_sense_data); 961 acb->flags |= ACB_CHKSENSE; 962 /*XXX - must take off queue here */ 963 if (acb != sc->sc_nexus) { 964 panic("%s: mha_sched: floating acb %p", 965 sc->sc_dev.dv_xname, acb); 966 } 967 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 968 ACB_SETQ(acb, ACB_QREADY); 969 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 970 ti->senses++; 971 timeout(mha_timeout, acb, (xs->timeout*hz)/1000); 972 if (sc->sc_nexus == acb) { 973 sc->sc_nexus = NULL; 974 sc->sc_state = SPC_IDLE; 975 mha_sched(sc); 976 } 977 #if 0 978 mha_sense(sc, acb); 979 #endif 980 return; 981 } 982 case SCSI_BUSY: 983 xs->error = XS_BUSY; 984 break; 985 case SCSI_OK: 986 xs->resid = acb->dleft; 987 break; 988 default: 989 xs->error = XS_DRIVER_STUFFUP; 990 #if SPC_DEBUG 991 printf("%s: mha_done: bad stat 0x%x\n", 992 sc->sc_dev.dv_xname, acb->stat); 993 #endif 994 break; 995 } 996 } 997 } 998 999 xs->xs_status |= XS_STS_DONE; 1000 1001 #if SPC_DEBUG 1002 if ((mha_debug & SPC_SHOWMISC) != 0) { 1003 if (xs->resid != 0) 1004 printf("resid=%d ", xs->resid); 1005 if (xs->error == XS_SENSE) 1006 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 1007 else 1008 printf("error=%d\n", xs->error); 1009 } 1010 #endif 1011 1012 /* 1013 * Remove the ACB from whatever queue it's on. 1014 */ 1015 switch (acb->flags & ACB_QBITS) { 1016 case ACB_QNONE: 1017 if (acb != sc->sc_nexus) { 1018 panic("%s: floating acb", sc->sc_dev.dv_xname); 1019 } 1020 sc->sc_nexus = NULL; 1021 sc->sc_state = SPC_IDLE; 1022 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1023 mha_sched(sc); 1024 break; 1025 case ACB_QREADY: 1026 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1027 break; 1028 case ACB_QNEXUS: 1029 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1030 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1031 break; 1032 case ACB_QFREE: 1033 panic("%s: dequeue: busy acb on free list", 1034 sc->sc_dev.dv_xname); 1035 break; 1036 default: 1037 panic("%s: dequeue: unknown queue %d", 1038 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1039 } 1040 1041 /* Put it on the free list, and clear flags. */ 1042 #if 0 1043 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1044 acb->flags = ACB_QFREE; 1045 #else 1046 mha_free_acb(sc, acb, xs->xs_control); 1047 #endif 1048 1049 ti->cmds++; 1050 scsipi_done(xs); 1051 } 1052 1053 void 1054 mha_dequeue(sc, acb) 1055 struct mha_softc *sc; 1056 struct acb *acb; 1057 { 1058 1059 if (acb->flags & ACB_QNEXUS) { 1060 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1061 } else { 1062 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1063 } 1064 } 1065 1066 /* 1068 * INTERRUPT/PROTOCOL ENGINE 1069 */ 1070 1071 /* 1072 * Schedule an outgoing message by prioritizing it, and asserting 1073 * attention on the bus. We can only do this when we are the initiator 1074 * else there will be an illegal command interrupt. 1075 */ 1076 #define mha_sched_msgout(m) \ 1077 do { \ 1078 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1079 CMR = CMD_SET_ATN; \ 1080 sc->sc_msgpriq |= (m); \ 1081 } while (0) 1082 1083 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1084 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1085 #define ISEXTMSG(m) ((m) == 0x01) 1086 1087 /* 1088 * Precondition: 1089 * The SCSI bus is already in the MSGI phase and there is a message byte 1090 * on the bus, along with an asserted REQ signal. 1091 */ 1092 void 1093 mha_msgin(sc) 1094 register struct mha_softc *sc; 1095 { 1096 register int v; 1097 int n; 1098 1099 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1100 1101 /* 1102 * Prepare for a new message. A message should (according 1103 * to the SCSI standard) be transmitted in one single 1104 * MESSAGE_IN_PHASE. If we have been in some other phase, 1105 * then this is a new message. 1106 */ 1107 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1108 sc->sc_flags &= ~SPC_DROP_MSGI; 1109 sc->sc_imlen = 0; 1110 } 1111 1112 WAIT; 1113 1114 v = MBR; /* modified byte */ 1115 v = sc->sc_pcx[0]; 1116 1117 sc->sc_imess[sc->sc_imlen] = v; 1118 1119 /* 1120 * If we're going to reject the message, don't bother storing 1121 * the incoming bytes. But still, we need to ACK them. 1122 */ 1123 1124 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1125 CMR = CMD_SET_ATN; 1126 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1127 printf("<dropping msg byte %x>", 1128 sc->sc_imess[sc->sc_imlen]); 1129 return; 1130 } 1131 1132 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1133 mha_sched_msgout(SEND_REJECT); 1134 sc->sc_flags |= SPC_DROP_MSGI; 1135 } else { 1136 sc->sc_imlen++; 1137 /* 1138 * This testing is suboptimal, but most 1139 * messages will be of the one byte variety, so 1140 * it should not effect performance 1141 * significantly. 1142 */ 1143 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1144 goto gotit; 1145 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1146 goto gotit; 1147 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1148 sc->sc_imlen == sc->sc_imess[1] + 2) 1149 goto gotit; 1150 } 1151 #if 0 1152 /* Ack what we have so far */ 1153 ESPCMD(sc, ESPCMD_MSGOK); 1154 #endif 1155 return; 1156 1157 gotit: 1158 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1159 /* 1160 * Now we should have a complete message (1 byte, 2 byte 1161 * and moderately long extended messages). We only handle 1162 * extended messages which total length is shorter than 1163 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1164 */ 1165 if (sc->sc_state == SPC_HASNEXUS) { 1166 struct acb *acb = sc->sc_nexus; 1167 struct spc_tinfo *ti = 1168 &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1169 1170 switch (sc->sc_imess[0]) { 1171 case MSG_CMDCOMPLETE: 1172 SPC_MSGS(("cmdcomplete ")); 1173 if (sc->sc_dleft < 0) { 1174 struct scsipi_link *sc_link = acb->xs->sc_link; 1175 printf("mha: %d extra bytes from %d:%d\n", 1176 -sc->sc_dleft, 1177 sc_link->scsipi_scsi.target, 1178 sc_link->scsipi_scsi.lun); 1179 sc->sc_dleft = 0; 1180 } 1181 acb->xs->resid = acb->dleft = sc->sc_dleft; 1182 sc->sc_flags |= SPC_BUSFREE_OK; 1183 break; 1184 1185 case MSG_MESSAGE_REJECT: 1186 #if SPC_DEBUG 1187 if (mha_debug & SPC_SHOWMSGS) 1188 printf("%s: our msg rejected by target\n", 1189 sc->sc_dev.dv_xname); 1190 #endif 1191 #if 1 /* XXX - must remember last message */ 1192 scsi_print_addr(acb->xs->sc_link); 1193 printf("MSG_MESSAGE_REJECT>>"); 1194 #endif 1195 if (sc->sc_flags & SPC_SYNCHNEGO) { 1196 ti->period = ti->offset = 0; 1197 sc->sc_flags &= ~SPC_SYNCHNEGO; 1198 ti->flags &= ~T_NEGOTIATE; 1199 } 1200 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1201 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1202 mha_sched_msgout(SEND_ABORT); 1203 break; 1204 case MSG_NOOP: 1205 SPC_MSGS(("noop ")); 1206 break; 1207 case MSG_DISCONNECT: 1208 SPC_MSGS(("disconnect ")); 1209 ti->dconns++; 1210 sc->sc_flags |= SPC_DISCON; 1211 sc->sc_flags |= SPC_BUSFREE_OK; 1212 if ((acb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1213 break; 1214 /*FALLTHROUGH*/ 1215 case MSG_SAVEDATAPOINTER: 1216 SPC_MSGS(("save datapointer ")); 1217 acb->dleft = sc->sc_dleft; 1218 acb->daddr = sc->sc_dp; 1219 break; 1220 case MSG_RESTOREPOINTERS: 1221 SPC_MSGS(("restore datapointer ")); 1222 if (!acb) { 1223 mha_sched_msgout(SEND_ABORT); 1224 printf("%s: no DATAPOINTERs to restore\n", 1225 sc->sc_dev.dv_xname); 1226 break; 1227 } 1228 sc->sc_dp = acb->daddr; 1229 sc->sc_dleft = acb->dleft; 1230 break; 1231 case MSG_PARITY_ERROR: 1232 printf("%s:target%d: MSG_PARITY_ERROR\n", 1233 sc->sc_dev.dv_xname, 1234 acb->xs->sc_link->scsipi_scsi.target); 1235 break; 1236 case MSG_EXTENDED: 1237 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1238 switch (sc->sc_imess[2]) { 1239 case MSG_EXT_SDTR: 1240 SPC_MSGS(("SDTR period %d, offset %d ", 1241 sc->sc_imess[3], sc->sc_imess[4])); 1242 ti->period = sc->sc_imess[3]; 1243 ti->offset = sc->sc_imess[4]; 1244 if (sc->sc_minsync == 0) { 1245 /* We won't do synch */ 1246 ti->offset = 0; 1247 mha_sched_msgout(SEND_SDTR); 1248 } else if (ti->offset == 0) { 1249 printf("%s:%d: async\n", "mha", 1250 acb->xs->sc_link->scsipi_scsi.target); 1251 ti->offset = 0; 1252 sc->sc_flags &= ~SPC_SYNCHNEGO; 1253 } else if (ti->period > 124) { 1254 printf("%s:%d: async\n", "mha", 1255 acb->xs->sc_link->scsipi_scsi.target); 1256 ti->offset = 0; 1257 mha_sched_msgout(SEND_SDTR); 1258 } else { 1259 int r = 250/ti->period; 1260 int s = (100*250)/ti->period - 100*r; 1261 int p; 1262 #if 0 1263 p = mha_stp2cpb(sc, ti->period); 1264 ti->period = mha_cpb2stp(sc, p); 1265 #endif 1266 1267 #if SPC_DEBUG 1268 scsi_print_addr(acb->xs->sc_link); 1269 #endif 1270 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1271 /* Target initiated negotiation */ 1272 if (ti->flags & T_SYNCMODE) { 1273 ti->flags &= ~T_SYNCMODE; 1274 #if SPC_DEBUG 1275 printf("renegotiated "); 1276 #endif 1277 } 1278 TMR=TM_ASYNC; 1279 /* Clamp to our maxima */ 1280 if (ti->period < sc->sc_minsync) 1281 ti->period = sc->sc_minsync; 1282 if (ti->offset > 15) 1283 ti->offset = 15; 1284 mha_sched_msgout(SEND_SDTR); 1285 } else { 1286 /* we are sync */ 1287 sc->sc_flags &= ~SPC_SYNCHNEGO; 1288 TMR = TM_SYNC; 1289 ti->flags |= T_SYNCMODE; 1290 } 1291 #if SPC_DEBUG 1292 printf("max sync rate %d.%02dMb/s\n", 1293 r, s); 1294 #endif 1295 } 1296 ti->flags &= ~T_NEGOTIATE; 1297 break; 1298 default: /* Extended messages we don't handle */ 1299 CMR = CMD_SET_ATN; /* XXX? */ 1300 break; 1301 } 1302 break; 1303 default: 1304 SPC_MSGS(("ident ")); 1305 /* thanks for that ident... */ 1306 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1307 SPC_MISC(("unknown ")); 1308 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1309 CMR = CMD_SET_ATN; /* XXX? */ 1310 } 1311 break; 1312 } 1313 } else if (sc->sc_state == SPC_RESELECTED) { 1314 struct scsipi_link *sc_link = NULL; 1315 struct acb *acb; 1316 struct spc_tinfo *ti; 1317 u_char lunit; 1318 1319 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1320 SPC_MISC(("searching ")); 1321 /* 1322 * Search wait queue for disconnected cmd 1323 * The list should be short, so I haven't bothered with 1324 * any more sophisticated structures than a simple 1325 * singly linked list. 1326 */ 1327 lunit = sc->sc_imess[0] & 0x07; 1328 for (acb = sc->nexus_list.tqh_first; acb; 1329 acb = acb->chain.tqe_next) { 1330 sc_link = acb->xs->sc_link; 1331 if (sc_link->scsipi_scsi.lun == lunit && 1332 sc->sc_selid == (1<<sc_link->scsipi_scsi.target)) { 1333 TAILQ_REMOVE(&sc->nexus_list, acb, 1334 chain); 1335 ACB_SETQ(acb, ACB_QNONE); 1336 break; 1337 } 1338 } 1339 1340 if (!acb) { /* Invalid reselection! */ 1341 mha_sched_msgout(SEND_ABORT); 1342 printf("mha: invalid reselect (idbit=0x%2x)\n", 1343 sc->sc_selid); 1344 } else { /* Reestablish nexus */ 1345 /* 1346 * Setup driver data structures and 1347 * do an implicit RESTORE POINTERS 1348 */ 1349 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1350 sc->sc_nexus = acb; 1351 sc->sc_dp = acb->daddr; 1352 sc->sc_dleft = acb->dleft; 1353 sc->sc_tinfo[sc_link->scsipi_scsi.target].lubusy 1354 |= (1<<sc_link->scsipi_scsi.lun); 1355 if (ti->flags & T_SYNCMODE) { 1356 TMR = TM_SYNC; /* XXX */ 1357 } else { 1358 TMR = TM_ASYNC; 1359 } 1360 SPC_MISC(("... found acb")); 1361 sc->sc_state = SPC_HASNEXUS; 1362 } 1363 } else { 1364 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1365 sc->sc_dev.dv_xname, sc->sc_selid); 1366 mha_sched_msgout(SEND_DEV_RESET); 1367 } 1368 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1369 printf("%s: unexpected message in; will send DEV_RESET\n", 1370 sc->sc_dev.dv_xname); 1371 mha_sched_msgout(SEND_DEV_RESET); 1372 } 1373 1374 /* Ack last message byte */ 1375 #if 0 1376 ESPCMD(sc, ESPCMD_MSGOK); 1377 #endif 1378 1379 /* Done, reset message pointer. */ 1380 sc->sc_flags &= ~SPC_DROP_MSGI; 1381 sc->sc_imlen = 0; 1382 } 1383 1384 /* 1385 * Send the highest priority, scheduled message. 1386 */ 1387 void 1388 mha_msgout(sc) 1389 register struct mha_softc *sc; 1390 { 1391 struct spc_tinfo *ti; 1392 int n; 1393 1394 SPC_TRACE(("mha_msgout ")); 1395 1396 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1397 if (sc->sc_omp == sc->sc_omess) { 1398 /* 1399 * This is a retransmission. 1400 * 1401 * We get here if the target stayed in MESSAGE OUT 1402 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1403 * that all of the previously transmitted messages must 1404 * be sent again, in the same order. Therefore, we 1405 * requeue all the previously transmitted messages, and 1406 * start again from the top. Our simple priority 1407 * scheme keeps the messages in the right order. 1408 */ 1409 SPC_MISC(("retransmitting ")); 1410 sc->sc_msgpriq |= sc->sc_msgoutq; 1411 /* 1412 * Set ATN. If we're just sending a trivial 1-byte 1413 * message, we'll clear ATN later on anyway. 1414 */ 1415 CMR = CMD_SET_ATN; /* XXX? */ 1416 } else { 1417 /* This is a continuation of the previous message. */ 1418 n = sc->sc_omp - sc->sc_omess; 1419 goto nextbyte; 1420 } 1421 } 1422 1423 /* No messages transmitted so far. */ 1424 sc->sc_msgoutq = 0; 1425 sc->sc_lastmsg = 0; 1426 1427 nextmsg: 1428 /* Pick up highest priority message. */ 1429 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1430 sc->sc_msgpriq &= ~sc->sc_currmsg; 1431 sc->sc_msgoutq |= sc->sc_currmsg; 1432 1433 /* Build the outgoing message data. */ 1434 switch (sc->sc_currmsg) { 1435 case SEND_IDENTIFY: 1436 SPC_ASSERT(sc->sc_nexus != NULL); 1437 sc->sc_omess[0] = 1438 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1439 n = 1; 1440 break; 1441 1442 #if SPC_USE_SYNCHRONOUS 1443 case SEND_SDTR: 1444 SPC_ASSERT(sc->sc_nexus != NULL); 1445 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1446 sc->sc_omess[4] = MSG_EXTENDED; 1447 sc->sc_omess[3] = 3; 1448 sc->sc_omess[2] = MSG_EXT_SDTR; 1449 sc->sc_omess[1] = ti->period >> 2; 1450 sc->sc_omess[0] = ti->offset; 1451 n = 5; 1452 break; 1453 #endif 1454 1455 #if SPC_USE_WIDE 1456 case SEND_WDTR: 1457 SPC_ASSERT(sc->sc_nexus != NULL); 1458 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1459 sc->sc_omess[3] = MSG_EXTENDED; 1460 sc->sc_omess[2] = 2; 1461 sc->sc_omess[1] = MSG_EXT_WDTR; 1462 sc->sc_omess[0] = ti->width; 1463 n = 4; 1464 break; 1465 #endif 1466 1467 case SEND_DEV_RESET: 1468 sc->sc_flags |= SPC_ABORTING; 1469 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1470 n = 1; 1471 break; 1472 1473 case SEND_REJECT: 1474 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1475 n = 1; 1476 break; 1477 1478 case SEND_PARITY_ERROR: 1479 sc->sc_omess[0] = MSG_PARITY_ERROR; 1480 n = 1; 1481 break; 1482 1483 case SEND_INIT_DET_ERR: 1484 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1485 n = 1; 1486 break; 1487 1488 case SEND_ABORT: 1489 sc->sc_flags |= SPC_ABORTING; 1490 sc->sc_omess[0] = MSG_ABORT; 1491 n = 1; 1492 break; 1493 1494 default: 1495 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1496 sc->sc_dev.dv_xname); 1497 SPC_BREAK(); 1498 sc->sc_omess[0] = MSG_NOOP; 1499 n = 1; 1500 break; 1501 } 1502 sc->sc_omp = &sc->sc_omess[n]; 1503 1504 nextbyte: 1505 /* Send message bytes. */ 1506 /* send TRANSFER command. */ 1507 sc->sc_ps[3] = 1; 1508 sc->sc_ps[4] = n >> 8; 1509 sc->sc_pc[10] = n; 1510 sc->sc_ps[-1] = 0x000F; /* burst */ 1511 asm volatile ("nop"); 1512 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1513 for (;;) { 1514 if ((SSR & SS_BUSY) != 0) 1515 break; 1516 if (SSR & SS_IREQUEST) 1517 goto out; 1518 } 1519 for (;;) { 1520 #if 0 1521 for (;;) { 1522 if ((PSNS & PSNS_REQ) != 0) 1523 break; 1524 /* Wait for REQINIT. XXX Need timeout. */ 1525 } 1526 #endif 1527 if (SSR & SS_IREQUEST) { 1528 /* 1529 * Target left MESSAGE OUT, possibly to reject 1530 * our message. 1531 * 1532 * If this is the last message being sent, then we 1533 * deassert ATN, since either the target is going to 1534 * ignore this message, or it's going to ask for a 1535 * retransmission via MESSAGE PARITY ERROR (in which 1536 * case we reassert ATN anyway). 1537 */ 1538 #if 0 1539 if (sc->sc_msgpriq == 0) 1540 CMR = CMD_RESET_ATN; 1541 #endif 1542 goto out; 1543 } 1544 1545 #if 0 1546 /* Clear ATN before last byte if this is the last message. */ 1547 if (n == 1 && sc->sc_msgpriq == 0) 1548 CMR = CMD_RESET_ATN; 1549 #endif 1550 1551 while ((SSR & SS_DREG_FULL) != 0) 1552 ; 1553 /* Send message byte. */ 1554 sc->sc_pc[0] = *--sc->sc_omp; 1555 --n; 1556 /* Keep track of the last message we've sent any bytes of. */ 1557 sc->sc_lastmsg = sc->sc_currmsg; 1558 1559 if (n == 0) 1560 break; 1561 } 1562 1563 /* We get here only if the entire message has been transmitted. */ 1564 if (sc->sc_msgpriq != 0) { 1565 /* There are more outgoing messages. */ 1566 goto nextmsg; 1567 } 1568 1569 /* 1570 * The last message has been transmitted. We need to remember the last 1571 * message transmitted (in case the target switches to MESSAGE IN phase 1572 * and sends a MESSAGE REJECT), and the list of messages transmitted 1573 * this time around (in case the target stays in MESSAGE OUT phase to 1574 * request a retransmit). 1575 */ 1576 1577 out: 1578 /* Disable REQ/ACK protocol. */ 1579 } 1580 1581 1582 /*************************************************************** 1584 * 1585 * datain/dataout 1586 * 1587 */ 1588 1589 int 1590 mha_datain_pio(sc, p, n) 1591 register struct mha_softc *sc; 1592 u_char *p; 1593 int n; 1594 { 1595 u_short d; 1596 int a; 1597 int total_n = n; 1598 1599 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1600 1601 WAIT; 1602 sc->sc_ps[3] = 1; 1603 sc->sc_ps[4] = n >> 8; 1604 sc->sc_pc[10] = n; 1605 /* $BHa$7$-%=%U%HE>Aw(B */ 1606 CMR = CMD_RECEIVE_TO_MPU; 1607 for (;;) { 1608 a = SSR; 1609 if (a & 0x04) { 1610 d = sc->sc_ps[0]; 1611 *p++ = d >> 8; 1612 if (--n > 0) { 1613 *p++ = d; 1614 --n; 1615 } 1616 a = SSR; 1617 } 1618 if (a & 0x40) 1619 continue; 1620 if (a & 0x80) 1621 break; 1622 } 1623 SPC_TRACE(("...%d resd]", n)); 1624 return total_n - n; 1625 } 1626 1627 int 1628 mha_dataout_pio(sc, p, n) 1629 register struct mha_softc *sc; 1630 u_char *p; 1631 int n; 1632 { 1633 u_short d; 1634 int a; 1635 int total_n = n; 1636 1637 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1638 1639 WAIT; 1640 sc->sc_ps[3] = 1; 1641 sc->sc_ps[4] = n >> 8; 1642 sc->sc_pc[10] = n; 1643 /* $BHa$7$-%=%U%HE>Aw(B */ 1644 CMR = CMD_SEND_FROM_MPU; 1645 for (;;) { 1646 a = SSR; 1647 if (a & 0x04) { 1648 d = *p++ << 8; 1649 if (--n > 0) { 1650 d |= *p++; 1651 --n; 1652 } 1653 sc->sc_ps[0] = d; 1654 a = SSR; 1655 } 1656 if (a & 0x40) 1657 continue; 1658 if (a & 0x80) 1659 break; 1660 } 1661 SPC_TRACE(("...%d resd]", n)); 1662 return total_n - n; 1663 } 1664 1665 static int 1666 mha_dataio_dma(dw, cw, sc, p, n) 1667 int dw; /* DMA word */ 1668 int cw; /* CMR word */ 1669 register struct mha_softc *sc; 1670 u_char *p; 1671 int n; 1672 { 1673 char *paddr, *vaddr; 1674 1675 if (n > MAXBSIZE) 1676 panic("transfer size exceeds MAXBSIZE"); 1677 if (sc->sc_dmasize > 0) 1678 panic("DMA request while another DMA transfer is in pregress"); 1679 1680 if (cw == CMD_SEND_FROM_DMA) { 1681 memcpy(sc->sc_dmabuf, p, n); 1682 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1683 } else { 1684 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1685 } 1686 sc->sc_p = p; 1687 sc->sc_dmasize = n; 1688 1689 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1690 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1691 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1692 dw &= ~(1 << 3); 1693 #endif 1694 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1695 #if 0 1696 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1697 PCIA(); /* XXX */ 1698 #endif 1699 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1700 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1701 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1702 WAIT; 1703 sc->sc_ps[3] = 1; 1704 sc->sc_ps[4] = n >> 8; 1705 sc->sc_pc[10] = n; 1706 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1707 3 ... short bus cycle 1708 2 ... MAXIMUM XFER. 1709 1 ... BURST XFER. 1710 0 ... R/W */ 1711 sc->sc_ps[-1] = dw; /* burst */ 1712 asm volatile ("nop"); 1713 CMR = cw; /* receive to DMA */ 1714 return n; 1715 } 1716 int 1717 mha_dataout(sc, p, n) 1718 register struct mha_softc *sc; 1719 u_char *p; 1720 int n; 1721 { 1722 register struct acb *acb = sc->sc_nexus; 1723 1724 if (n == 0) 1725 return n; 1726 1727 if (n & 1) 1728 return mha_dataout_pio(sc, p, n); 1729 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1730 } 1731 1732 int 1734 mha_datain(sc, p, n) 1735 register struct mha_softc *sc; 1736 u_char *p; 1737 int n; 1738 { 1739 int ts; 1740 register struct acb *acb = sc->sc_nexus; 1741 char *paddr, *vaddr; 1742 1743 if (n == 0) 1744 return n; 1745 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1746 return mha_datain_pio(sc, p, n); 1747 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1748 } 1749 1750 1752 /* 1753 * Catch an interrupt from the adaptor 1754 */ 1755 /* 1756 * This is the workhorse routine of the driver. 1757 * Deficiencies (for now): 1758 * 1) always uses programmed I/O 1759 */ 1760 int 1761 mhaintr(arg) 1762 void *arg; 1763 { 1764 struct mha_softc *sc = arg; 1765 #if 0 1766 u_char ints; 1767 #endif 1768 struct acb *acb; 1769 struct scsipi_link *sc_link; 1770 struct spc_tinfo *ti; 1771 u_char ph; 1772 u_short r; 1773 int n; 1774 1775 #if 1 /* XXX called during attach? */ 1776 if (tmpsc != NULL) { 1777 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1778 sc = tmpsc; 1779 } else { 1780 #endif 1781 1782 #if 1 /* XXX */ 1783 } 1784 #endif 1785 1786 #if 0 1787 /* 1788 * $B3d$j9~$_6X;_$K$9$k(B 1789 */ 1790 SCTL &= ~SCTL_INTR_ENAB; 1791 #endif 1792 1793 SPC_TRACE(("[mhaintr]")); 1794 1795 loop: 1796 /* 1797 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1798 */ 1799 /* 1800 * First check for abnormal conditions, such as reset. 1801 */ 1802 #if 0 1803 #if 1 /* XXX? */ 1804 while (((ints = SSR) & SS_IREQUEST) == 0) 1805 delay(1); 1806 SPC_MISC(("ints = 0x%x ", ints)); 1807 #else /* usually? */ 1808 ints = SSR; 1809 #endif 1810 #endif 1811 while (SSR & SS_IREQUEST) { 1812 acb = sc->sc_nexus; 1813 r = ISCSR; 1814 SPC_MISC(("[r=0x%x]", r)); 1815 switch (r >> 8) { 1816 default: 1817 printf("[addr=%x\n" 1818 "result=0x%x\n" 1819 "cmd=0x%x\n" 1820 "ph=0x%x(ought to be %d)]\n", 1821 &ISCSR, 1822 r, 1823 acb->xs->cmd->opcode, 1824 SCR, sc->sc_phase); 1825 panic("unexpected result."); 1826 case 0x82: /* selection timeout */ 1827 SPC_MISC(("selection timeout ")); 1828 sc->sc_phase = BUSFREE_PHASE; 1829 SPC_ASSERT(sc->sc_nexus != NULL); 1830 acb = sc->sc_nexus; 1831 delay(250); 1832 acb->xs->error = XS_SELTIMEOUT; 1833 mha_done(sc, acb); 1834 continue; /* XXX ??? msaitoh */ 1835 case 0x60: /* command completed */ 1836 sc->sc_spcinitialized++; 1837 if (sc->sc_phase == BUSFREE_PHASE) 1838 continue; 1839 ph = SCR; 1840 if (ph & PSNS_ACK) { 1841 int s; 1842 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1843 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1844 ph & PHASE_MASK, sc->sc_phase)); 1845 #if 0 1846 /* switch (sc->sc_phase) {*/ 1847 #else 1848 switch (ph & PHASE_MASK) { 1849 #endif 1850 case STATUS_PHASE: 1851 if (sc->sc_state != SPC_HASNEXUS) 1852 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1853 sc->sc_state); 1854 SPC_ASSERT(sc->sc_nexus != NULL); 1855 acb = sc->sc_nexus; 1856 WAIT; 1857 s = MBR; 1858 SPC_ASSERT(s == 1); 1859 acb->stat = sc->sc_pcx[0]; /* XXX */ 1860 SPC_MISC(("stat=0x%02x ", acb->stat)); 1861 sc->sc_prevphase = STATUS_PHASE; 1862 break; 1863 case MESSAGE_IN_PHASE: 1864 mha_msgin(sc); 1865 sc->sc_prevphase = MESSAGE_IN_PHASE; 1866 /* thru */ 1867 case DATA_IN_PHASE: 1868 if (sc->sc_dmasize == 0) 1869 break; 1870 bus_dmamap_sync(sc->sc_dmat, 1871 sc->sc_dmamap, 1872 0, sc->sc_dmasize, 1873 BUS_DMASYNC_POSTREAD); 1874 memcpy(sc->sc_p, sc->sc_dmabuf, 1875 sc->sc_dmasize); 1876 sc->sc_dmasize = 0; 1877 break; 1878 case DATA_OUT_PHASE: 1879 if (sc->sc_dmasize == 0) 1880 break; 1881 bus_dmamap_sync(sc->sc_dmat, 1882 sc->sc_dmamap, 1883 0, sc->sc_dmasize, 1884 BUS_DMASYNC_POSTWRITE); 1885 sc->sc_dmasize = 0; 1886 break; 1887 } 1888 WAIT; 1889 CMR = CMD_RESET_ACK; /* reset ack */ 1890 /*mha_done(sc, acb); XXX */ 1891 continue; 1892 } else if (NSR & 0x80) { /* nexus */ 1893 #if 1 1894 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1895 sc->sc_state = SPC_HASNEXUS; 1896 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1897 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1898 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1899 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1900 WAIT; 1901 if (SSR & SS_IREQUEST) 1902 continue; 1903 switch (sc->sc_phase) { 1904 default: 1905 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1906 case MESSAGE_IN_PHASE: 1907 /* $B2?$b$7$J$$(B */ 1908 continue; 1909 case STATUS_PHASE: 1910 sc->sc_phase = MESSAGE_IN_PHASE; 1911 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1912 continue; 1913 case DATA_IN_PHASE: 1914 sc->sc_prevphase = DATA_IN_PHASE; 1915 if (sc->sc_dleft == 0) { 1916 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1917 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1918 sc->sc_phase = STATUS_PHASE; 1919 CMR = CMD_RECEIVE_STS; /* receive sts */ 1920 continue; 1921 } 1922 n = mha_datain(sc, sc->sc_dp, 1923 sc->sc_dleft); 1924 sc->sc_dp += n; 1925 sc->sc_dleft -= n; 1926 continue; 1927 case DATA_OUT_PHASE: 1928 sc->sc_prevphase = DATA_OUT_PHASE; 1929 if (sc->sc_dleft == 0) { 1930 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1931 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1932 sc->sc_phase = STATUS_PHASE; 1933 CMR = CMD_RECEIVE_STS; /* receive sts */ 1934 continue; 1935 } 1936 /* data phase $B$NB3$-$r$d$m$&(B */ 1937 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1938 sc->sc_dp += n; 1939 sc->sc_dleft -= n; 1940 continue; 1941 case COMMAND_PHASE: 1942 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1943 if (acb->dleft) { 1944 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1945 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1946 sc->sc_phase = DATA_IN_PHASE; 1947 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1948 sc->sc_dp += n; 1949 sc->sc_dleft -= n; 1950 } 1951 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1952 sc->sc_phase = DATA_OUT_PHASE; 1953 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1954 sc->sc_dp += n; 1955 sc->sc_dleft -= n; 1956 } 1957 continue; 1958 } 1959 else { 1960 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1961 WAIT; 1962 sc->sc_phase = STATUS_PHASE; 1963 CMR = CMD_RECEIVE_STS; /* receive sts */ 1964 continue; 1965 } 1966 } 1967 #endif 1968 } 1969 continue; 1970 case 0x31: /* disconnected in xfer progress. */ 1971 SPC_MISC(("[0x31]")); 1972 case 0x70: /* disconnected. */ 1973 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1974 sc->sc_phase = BUSFREE_PHASE; 1975 sc->sc_state = SPC_IDLE; 1976 #if 1 1977 acb = sc->sc_nexus; 1978 SPC_ASSERT(sc->sc_nexus != NULL); 1979 acb->xs->error = XS_NOERROR; 1980 mha_done(sc, acb); 1981 #else 1982 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1983 mha_sched(sc); 1984 #endif 1985 continue; 1986 case 0x32: /* phase error in xfer progress. */ 1987 SPC_MISC(("[0x32]")); 1988 #if 0 1989 case 0x65: /* invalid command. 1990 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1991 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1992 #if 1 1993 SPC_MISC(("[0x%04x]", r)); 1994 #endif 1995 #endif 1996 case 0x54: /* initial-phase error. */ 1997 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1998 NSR, 1999 SCR, sc->sc_phase)); 2000 /* thru */ 2001 case 0x71: /* assert req */ 2002 WAIT; 2003 if (SSR & 0x40) { 2004 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 2005 SSR, r, NSR, SCR); 2006 WAIT; 2007 } 2008 ph = SCR; 2009 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 2010 sc->sc_state = SPC_HASNEXUS; 2011 } 2012 if (ph & 0x80) { 2013 switch (ph & PHASE_MASK) { 2014 default: 2015 printf("phase = %x\n", ph); 2016 panic("assert req: the phase I don't know!"); 2017 case DATA_IN_PHASE: 2018 sc->sc_prevphase = DATA_IN_PHASE; 2019 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 2020 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 2021 sc->sc_dp += n; 2022 sc->sc_dleft -= n; 2023 SPC_MISC(("done\n")); 2024 continue; 2025 case DATA_OUT_PHASE: 2026 sc->sc_prevphase = DATA_OUT_PHASE; 2027 SPC_MISC(("DATAOUT\n")); 2028 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 2029 sc->sc_dp += n; 2030 sc->sc_dleft -= n; 2031 continue; 2032 case STATUS_PHASE: 2033 sc->sc_phase = STATUS_PHASE; 2034 SPC_MISC(("[RECV_STS]")); 2035 WAIT; 2036 CMR = CMD_RECEIVE_STS; /* receive sts */ 2037 continue; 2038 case MESSAGE_IN_PHASE: 2039 sc->sc_phase = MESSAGE_IN_PHASE; 2040 WAIT; 2041 CMR = CMD_RECEIVE_MSG; 2042 continue; 2043 } 2044 } 2045 continue; 2046 } 2047 } 2048 } 2049 2050 void 2051 mha_abort(sc, acb) 2052 struct mha_softc *sc; 2053 struct acb *acb; 2054 { 2055 acb->flags |= ACB_ABORTED; 2056 2057 if (acb == sc->sc_nexus) { 2058 /* 2059 * If we're still selecting, the message will be scheduled 2060 * after selection is complete. 2061 */ 2062 if (sc->sc_state == SPC_HASNEXUS) { 2063 sc->sc_flags |= SPC_ABORTING; 2064 mha_sched_msgout(SEND_ABORT); 2065 } 2066 } else { 2067 if (sc->sc_state == SPC_IDLE) 2068 mha_sched(sc); 2069 } 2070 } 2071 2072 void 2073 mha_timeout(arg) 2074 void *arg; 2075 { 2076 int s = splbio(); 2077 struct acb *acb = (struct acb *)arg; 2078 struct scsipi_xfer *xs = acb->xs; 2079 struct scsipi_link *sc_link = xs->sc_link; 2080 struct mha_softc *sc = sc_link->adapter_softc; 2081 2082 scsi_print_addr(sc_link); 2083 again: 2084 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2085 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2086 sc->sc_dev.dv_xname, 2087 acb, acb->flags, acb->dleft, acb->stat, 2088 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2089 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2090 ); 2091 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2092 panic("timeout, ouch!"); 2093 2094 if (acb->flags & ACB_ABORTED) { 2095 /* abort timed out */ 2096 printf(" AGAIN\n"); 2097 #if 0 2098 mha_init(sc, 1); /* XXX 1?*/ 2099 #endif 2100 } else { 2101 /* abort the operation that has timed out */ 2102 printf("\n"); 2103 xs->error = XS_TIMEOUT; 2104 mha_abort(sc, acb); 2105 } 2106 2107 splx(s); 2108 } 2109 2110 #if SPC_DEBUG 2112 /* 2113 * The following functions are mostly used for debugging purposes, either 2114 * directly called from the driver or from the kernel debugger. 2115 */ 2116 2117 void 2118 mha_show_scsi_cmd(acb) 2119 struct acb *acb; 2120 { 2121 u_char *b = (u_char *)&acb->cmd; 2122 struct scsipi_link *sc_link = acb->xs->sc_link; 2123 int i; 2124 2125 scsi_print_addr(sc_link); 2126 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2127 for (i = 0; i < acb->clen; i++) { 2128 if (i) 2129 printf(","); 2130 printf("%x", b[i]); 2131 } 2132 printf("\n"); 2133 } else 2134 printf("RESET\n"); 2135 } 2136 2137 void 2138 mha_print_acb(acb) 2139 struct acb *acb; 2140 { 2141 2142 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2143 printf(" dp=%x dleft=%d stat=%x\n", 2144 (long)acb->daddr, acb->dleft, acb->stat); 2145 mha_show_scsi_cmd(acb); 2146 } 2147 2148 void 2149 mha_print_active_acb() 2150 { 2151 struct acb *acb; 2152 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2153 2154 printf("ready list:\n"); 2155 for (acb = sc->ready_list.tqh_first; acb != NULL; 2156 acb = acb->chain.tqe_next) 2157 mha_print_acb(acb); 2158 printf("nexus:\n"); 2159 if (sc->sc_nexus != NULL) 2160 mha_print_acb(sc->sc_nexus); 2161 printf("nexus list:\n"); 2162 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2163 acb = acb->chain.tqe_next) 2164 mha_print_acb(acb); 2165 } 2166 2167 void 2168 mha_dump_driver(sc) 2169 struct mha_softc *sc; 2170 { 2171 struct spc_tinfo *ti; 2172 int i; 2173 2174 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2175 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2176 sc->sc_state, sc->sc_imess[0], 2177 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2178 for (i = 0; i < 7; i++) { 2179 ti = &sc->sc_tinfo[i]; 2180 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2181 i, ti->cmds, ti->dconns, ti->touts); 2182 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2183 } 2184 } 2185 #endif 2186
Indexes created Sat Oct 18 17:09:52 GMT 2025