mha.c revision 1.19
1 /* $NetBSD: mha.c,v 1.19 2000/03/23 06:47:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 190 #define Debugger() panic("should call debugger here (mha.c)") 191 #endif /* ! DDB */ 192 193 194 #if SPC_DEBUG 195 #define SPC_SHOWACBS 0x01 196 #define SPC_SHOWINTS 0x02 197 #define SPC_SHOWCMDS 0x04 198 #define SPC_SHOWMISC 0x08 199 #define SPC_SHOWTRAC 0x10 200 #define SPC_SHOWSTART 0x20 201 #define SPC_SHOWPHASE 0x40 202 #define SPC_SHOWDMA 0x80 203 #define SPC_SHOWCCMDS 0x100 204 #define SPC_SHOWMSGS 0x200 205 #define SPC_DOBREAK 0x400 206 207 int mha_debug = 208 #if 0 209 0x7FF; 210 #else 211 SPC_SHOWSTART|SPC_SHOWTRAC; 212 #endif 213 214 215 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 216 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 217 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 218 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 219 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 220 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 221 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 222 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 223 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 224 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 225 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 226 #else 227 #define SPC_ACBS(str) 228 #define SPC_MISC(str) 229 #define SPC_INTS(str) 230 #define SPC_TRACE(str) 231 #define SPC_CMDS(str) 232 #define SPC_START(str) 233 #define SPC_PHASE(str) 234 #define SPC_DMA(str) 235 #define SPC_MSGS(str) 236 #define SPC_BREAK() 237 #define SPC_ASSERT(x) 238 #endif 239 240 int mhamatch __P((struct device *, struct cfdata *, void *)); 241 void mhaattach __P((struct device *, struct device *, void *)); 242 void mhaselect __P((struct mha_softc *, 243 u_char, u_char, u_char *, u_char)); 244 void mha_reset __P((struct mha_softc *)); 245 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 246 void mha_sense __P((struct mha_softc *, struct acb *)); 247 void mha_msgin __P((struct mha_softc *)); 248 void mha_msgout __P((struct mha_softc *)); 249 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 250 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_dataout __P((struct mha_softc *, u_char *, int)); 252 int mha_datain __P((struct mha_softc *, u_char *, int)); 253 void mha_abort __P((struct mha_softc *, struct acb *)); 254 void mha_init __P((struct mha_softc *)); 255 int mha_scsi_cmd __P((struct scsipi_xfer *)); 256 int mha_poll __P((struct mha_softc *, struct acb *)); 257 void mha_sched __P((struct mha_softc *)); 258 void mha_done __P((struct mha_softc *, struct acb *)); 259 int mhaintr __P((void*)); 260 void mha_timeout __P((void *)); 261 void mha_minphys __P((struct buf *)); 262 void mha_dequeue __P((struct mha_softc *, struct acb *)); 263 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 264 #if SPC_DEBUG 265 void mha_print_acb __P((struct acb *)); 266 void mha_show_scsi_cmd __P((struct acb *)); 267 void mha_print_active_acb __P((void)); 268 void mha_dump_driver __P((struct mha_softc *)); 269 #endif 270 271 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 272 273 struct cfattach mha_ca = { 274 sizeof(struct mha_softc), mhamatch, mhaattach 275 }; 276 277 extern struct cfdriver mha_cd; 278 279 struct scsipi_device mha_dev = { 280 NULL, /* Use default error handler */ 281 NULL, /* have a queue, served by this */ 282 NULL, /* have no async handler */ 283 NULL, /* Use default 'done' routine */ 284 }; 285 286 /* 288 * returns non-zero value if a controller is found. 289 */ 290 int 291 mhamatch(parent, cf, aux) 292 struct device *parent; 293 struct cfdata *cf; 294 void *aux; 295 { 296 struct intio_attach_args *ia = aux; 297 bus_space_tag_t iot = ia->ia_bst; 298 bus_space_handle_t ioh; 299 300 ia->ia_size=0x20; 301 if (ia->ia_addr != 0xea0000) 302 return 0; 303 304 if (intio_map_allocate_region(parent->dv_parent, ia, 305 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 306 return 0; 307 308 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 309 &ioh) < 0) 310 return 0; 311 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 312 return 0; 313 bus_space_unmap(iot, ioh, 0x20); 314 315 return 1; 316 } 317 318 /* 319 */ 320 321 struct mha_softc *tmpsc; 322 323 void 324 mhaattach(parent, self, aux) 325 struct device *parent, *self; 326 void *aux; 327 { 328 struct mha_softc *sc = (void *)self; 329 struct intio_attach_args *ia = aux; 330 331 tmpsc = sc; /* XXX */ 332 333 SPC_TRACE(("mhaattach ")); 334 sc->sc_state = SPC_INIT; 335 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 336 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 337 /* XXX: FAKE */ 338 sc->sc_dmat = ia->ia_dmat; 339 340 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 341 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 342 sc->sc_pcx = &sc->sc_pc[0x10]; 343 344 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 345 346 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 347 348 mha_init(sc); /* Init chip and driver */ 349 350 sc->sc_phase = BUSFREE_PHASE; 351 352 /* 353 * Fill in the adapter. 354 */ 355 sc->sc_adapter.scsipi_cmd = mha_scsi_cmd; 356 sc->sc_adapter.scsipi_minphys = mha_minphys; 357 358 /* 359 * Fill in the prototype scsi_link 360 */ 361 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 362 sc->sc_link.adapter_softc = sc; 363 sc->sc_link.scsipi_scsi.adapter_target = sc->sc_id; 364 sc->sc_link.adapter = &sc->sc_adapter; 365 sc->sc_link.device = &mha_dev; 366 sc->sc_link.openings = 2; 367 sc->sc_link.scsipi_scsi.max_target = 7; 368 sc->sc_link.scsipi_scsi.max_lun = 7; 369 sc->sc_link.type = BUS_SCSI; 370 371 sc->sc_spcinitialized = 0; 372 WAR = WA_INITWIN; 373 #if 1 374 CCR = 0x14; 375 OIR = sc->sc_id; 376 AMR = 0x00; 377 SMR = 0x00; 378 SRR = 0x00; 379 STR = 0x20; 380 RTR = 0x40; 381 ATR = 0x01; 382 PER = 0xc9; 383 #endif 384 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 385 #if 1 386 GLR = 0x00; 387 DMR = 0x30; 388 IMR = 0x00; 389 #endif 390 WAR = WA_MCSBUFWIN; 391 392 /* drop off */ 393 while (SSR & SS_IREQUEST) 394 { 395 unsigned a = ISCSR; 396 } 397 398 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 399 400 SPC_TRACE(("waiting for intr...")); 401 while (!(SSR & SS_IREQUEST)) 402 delay(10); 403 mhaintr (sc); 404 405 tmpsc = NULL; 406 407 config_found(self, &sc->sc_link, scsiprint); 408 } 409 410 #if 0 411 void 412 mha_reset(sc) 413 struct mha_softc *sc; 414 { 415 u_short dummy; 416 printf("reset..."); 417 CMR = CMD_SOFT_RESET; 418 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 419 dummy = sc->sc_ps[-1]; 420 dummy = sc->sc_ps[-1]; 421 dummy = sc->sc_ps[-1]; 422 dummy = sc->sc_ps[-1]; 423 asm volatile ("nop"); 424 CMR = CMD_SOFT_RESET; 425 sc->sc_spcinitialized = 0; 426 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 427 while(!sc->sc_spcinitialized); 428 429 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 430 printf("done.\n"); 431 } 432 #endif 433 434 /* 435 * Initialize mha SCSI driver. 436 */ 437 void 438 mha_init(sc) 439 struct mha_softc *sc; 440 { 441 struct acb *acb; 442 int r; 443 444 if (sc->sc_state == SPC_INIT) { 445 /* First time through; initialize. */ 446 TAILQ_INIT(&sc->ready_list); 447 TAILQ_INIT(&sc->nexus_list); 448 TAILQ_INIT(&sc->free_list); 449 sc->sc_nexus = NULL; 450 acb = sc->sc_acb; 451 bzero(acb, sizeof(sc->sc_acb)); 452 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 453 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 454 acb++; 455 } 456 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 457 458 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 459 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 460 BUS_DMA_NOWAIT); 461 if (r) 462 panic("mha_init: cannot allocate dma memory"); 463 if (sc->sc_ndmasegs != 1) 464 panic("mha_init: number of segment > 1??"); 465 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 466 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 467 if (r) 468 panic("mha_init: cannot map dma memory"); 469 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 470 MAXBSIZE, 0, BUS_DMA_NOWAIT, 471 &sc->sc_dmamap); 472 if (r) 473 panic("mha_init: cannot create dmamap structure"); 474 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 475 sc->sc_dmabuf, MAXBSIZE, NULL, 476 BUS_DMA_NOWAIT); 477 if (r) 478 panic("mha_init: cannot load dma buffer into dmamap"); 479 sc->sc_p = 0; 480 } else { 481 /* Cancel any active commands. */ 482 sc->sc_flags |= SPC_ABORTING; 483 sc->sc_state = SPC_IDLE; 484 if ((acb = sc->sc_nexus) != NULL) { 485 acb->xs->error = XS_DRIVER_STUFFUP; 486 mha_done(sc, acb); 487 } 488 while ((acb = sc->nexus_list.tqh_first) != NULL) { 489 acb->xs->error = XS_DRIVER_STUFFUP; 490 mha_done(sc, acb); 491 } 492 } 493 494 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 495 for (r = 0; r < 8; r++) { 496 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 497 498 ti->flags = 0; 499 #if SPC_USE_SYNCHRONOUS 500 ti->flags |= T_SYNCMODE; 501 ti->period = sc->sc_minsync; 502 ti->offset = SPC_SYNC_REQ_ACK_OFS; 503 #else 504 ti->period = ti->offset = 0; 505 #endif 506 ti->width = 0; 507 } 508 509 sc->sc_state = SPC_IDLE; 510 } 511 512 void 513 mha_free_acb(sc, acb, flags) 514 struct mha_softc *sc; 515 struct acb *acb; 516 int flags; 517 { 518 int s; 519 520 s = splbio(); 521 522 acb->flags = 0; 523 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 524 525 /* 526 * If there were none, wake anybody waiting for one to come free, 527 * starting with queued entries. 528 */ 529 if (acb->chain.tqe_next == 0) 530 wakeup(&sc->free_list); 531 532 splx(s); 533 } 534 535 536 /* 538 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 539 */ 540 541 /* 542 * Expected sequence: 543 * 1) Command inserted into ready list 544 * 2) Command selected for execution 545 * 3) Command won arbitration and has selected target device 546 * 4) Send message out (identify message, eventually also sync.negotiations) 547 * 5) Send command 548 * 5a) Receive disconnect message, disconnect. 549 * 5b) Reselected by target 550 * 5c) Receive identify message from target. 551 * 6) Send or receive data 552 * 7) Receive status 553 * 8) Receive message (command complete etc.) 554 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 555 * Repeat 2-8 (no disconnects please...) 556 */ 557 558 /* 559 * Start a selection. This is used by mha_sched() to select an idle target, 560 * and by mha_done() to immediately reselect a target to get sense information. 561 */ 562 void 563 mhaselect(sc, target, lun, cmd, clen) 564 struct mha_softc *sc; 565 u_char target, lun; 566 u_char *cmd; 567 u_char clen; 568 { 569 #if 0 570 struct scsi_link *sc_link = acb->xs->sc_link; 571 #endif 572 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 573 int i; 574 int s; 575 576 s = splbio(); /* XXX */ 577 578 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 579 580 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 581 /* Now the command into the FIFO */ 582 WAIT; 583 #if 1 584 SPC_MISC(("[cmd:")); 585 for (i = 0; i < clen; i++) 586 { 587 unsigned c = cmd[i]; 588 if (i == 1) 589 c |= lun << 5; 590 SPC_MISC((" %02x", c)); 591 sc->sc_pcx[i] = c; 592 } 593 SPC_MISC(("], target=%d\n", target)); 594 #else 595 bcopy(cmd, sc->sc_pcx, clen); 596 #endif 597 if (NSR & 0x80) 598 panic("scsistart: already selected..."); 599 sc->sc_phase = COMMAND_PHASE; 600 601 /* new state ASP_SELECTING */ 602 sc->sc_state = SPC_SELECTING; 603 604 SIR = target; 605 #if 0 606 CMR = CMD_SELECT; 607 #else 608 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 609 #endif 610 splx(s); 611 } 612 613 #if 0 614 int 615 mha_reselect(sc, message) 616 struct mha_softc *sc; 617 u_char message; 618 { 619 u_char selid, target, lun; 620 struct acb *acb; 621 struct scsipi_link *sc_link; 622 struct spc_tinfo *ti; 623 624 /* 625 * The SCSI chip made a snapshot of the data bus while the reselection 626 * was being negotiated. This enables us to determine which target did 627 * the reselect. 628 */ 629 selid = sc->sc_selid & ~(1 << sc->sc_id); 630 if (selid & (selid - 1)) { 631 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 632 sc->sc_dev.dv_xname, selid); 633 SPC_BREAK(); 634 goto reset; 635 } 636 637 /* 638 * Search wait queue for disconnected cmd 639 * The list should be short, so I haven't bothered with 640 * any more sophisticated structures than a simple 641 * singly linked list. 642 */ 643 target = ffs(selid) - 1; 644 lun = message & 0x07; 645 for (acb = sc->nexus_list.tqh_first; acb != NULL; 646 acb = acb->chain.tqe_next) { 647 sc_link = acb->xs->sc_link; 648 if (sc_link->scsipi_scsi.target == target && 649 sc_link->scsipi_scsi.lun == lun) 650 break; 651 } 652 if (acb == NULL) { 653 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 654 sc->sc_dev.dv_xname, target, lun); 655 SPC_BREAK(); 656 goto abort; 657 } 658 659 /* Make this nexus active again. */ 660 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 661 sc->sc_state = SPC_HASNEXUS; 662 sc->sc_nexus = acb; 663 ti = &sc->sc_tinfo[target]; 664 ti->lubusy |= (1 << lun); 665 mha_setsync(sc, ti); 666 667 if (acb->flags & ACB_RESET) 668 mha_sched_msgout(sc, SEND_DEV_RESET); 669 else if (acb->flags & ACB_ABORTED) 670 mha_sched_msgout(sc, SEND_ABORT); 671 672 /* Do an implicit RESTORE POINTERS. */ 673 sc->sc_dp = acb->daddr; 674 sc->sc_dleft = acb->dleft; 675 sc->sc_cp = (u_char *)&acb->cmd; 676 sc->sc_cleft = acb->clen; 677 678 return (0); 679 680 reset: 681 mha_sched_msgout(sc, SEND_DEV_RESET); 682 return (1); 683 684 abort: 685 mha_sched_msgout(sc, SEND_ABORT); 686 return (1); 687 } 688 #endif 689 /* 690 * Start a SCSI-command 691 * This function is called by the higher level SCSI-driver to queue/run 692 * SCSI-commands. 693 */ 694 int 695 mha_scsi_cmd(xs) 696 struct scsipi_xfer *xs; 697 { 698 struct scsipi_link *sc_link = xs->sc_link; 699 struct mha_softc *sc = sc_link->adapter_softc; 700 struct acb *acb; 701 int s, flags; 702 703 SPC_TRACE(("[mha_scsi_cmd] ")); 704 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 705 sc_link->scsipi_scsi.target)); 706 707 flags = xs->xs_control; 708 709 /* Get a mha command block */ 710 s = splbio(); 711 acb = sc->free_list.tqh_first; 712 if (acb) { 713 TAILQ_REMOVE(&sc->free_list, acb, chain); 714 ACB_SETQ(acb, ACB_QNONE); 715 } 716 splx(s); 717 718 if (acb == NULL) { 719 SPC_MISC(("TRY_AGAIN_LATER")); 720 return TRY_AGAIN_LATER; 721 } 722 723 /* Initialize acb */ 724 acb->xs = xs; 725 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 726 acb->clen = xs->cmdlen; 727 acb->daddr = xs->data; 728 acb->dleft = xs->datalen; 729 acb->stat = 0; 730 731 s = splbio(); 732 ACB_SETQ(acb, ACB_QREADY); 733 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 734 #if 1 735 callout_reset(&acb->xs->xs_callout, (xs->timeout*hz)/1000, 736 mha_timeout, acb); 737 #endif 738 739 /* 740 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 741 */ 742 if (sc->sc_state == SPC_IDLE) 743 mha_sched(sc); 744 745 splx(s); 746 747 if (flags & XS_CTL_POLL) { 748 /* Not allowed to use interrupts, use polling instead */ 749 return mha_poll(sc, acb); 750 } 751 752 SPC_MISC(("SUCCESSFULLY_QUEUED")); 753 return SUCCESSFULLY_QUEUED; 754 } 755 756 /* 757 * Adjust transfer size in buffer structure 758 */ 759 void 760 mha_minphys(bp) 761 struct buf *bp; 762 { 763 764 SPC_TRACE(("mha_minphys ")); 765 minphys(bp); 766 } 767 768 /* 769 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 770 */ 771 int 772 mha_poll(sc, acb) 773 struct mha_softc *sc; 774 struct acb *acb; 775 { 776 struct scsipi_xfer *xs = acb->xs; 777 int count = xs->timeout * 100; 778 int s = splbio(); 779 780 SPC_TRACE(("[mha_poll] ")); 781 782 while (count) { 783 /* 784 * If we had interrupts enabled, would we 785 * have got an interrupt? 786 */ 787 if (SSR & SS_IREQUEST) 788 mhaintr(sc); 789 if ((xs->xs_status & XS_STS_DONE) != 0) 790 break; 791 DELAY(10); 792 #if 1 793 if (sc->sc_state == SPC_IDLE) { 794 SPC_TRACE(("[mha_poll: rescheduling] ")); 795 mha_sched(sc); 796 } 797 #endif 798 count--; 799 } 800 801 if (count == 0) { 802 SPC_MISC(("mha_poll: timeout")); 803 mha_timeout((caddr_t)acb); 804 } 805 splx(s); 806 return COMPLETE; 807 } 808 809 /* 811 * LOW LEVEL SCSI UTILITIES 812 */ 813 814 /* 815 * Set synchronous transfer offset and period. 816 */ 817 inline void 818 mha_setsync(sc, ti) 819 struct mha_softc *sc; 820 struct spc_tinfo *ti; 821 { 822 } 823 824 825 /* 827 * Schedule a SCSI operation. This has now been pulled out of the interrupt 828 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 829 * save us an unecessary interrupt just to get things going. Should only be 830 * called when state == SPC_IDLE and at bio pl. 831 */ 832 void 833 mha_sched(sc) 834 register struct mha_softc *sc; 835 { 836 struct scsipi_link *sc_link; 837 struct acb *acb; 838 int t; 839 840 SPC_TRACE(("[mha_sched] ")); 841 if (sc->sc_state != SPC_IDLE) 842 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 843 844 if (sc->sc_flags & SPC_ABORTING) 845 return; 846 847 /* 848 * Find first acb in ready queue that is for a target/lunit 849 * combinations that is not busy. 850 */ 851 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 852 struct spc_tinfo *ti; 853 sc_link = acb->xs->sc_link; 854 t = sc_link->scsipi_scsi.target; 855 ti = &sc->sc_tinfo[t]; 856 if (!(ti->lubusy & (1 << sc_link->scsipi_scsi.lun))) { 857 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 858 panic("mha: busy entry on ready list"); 859 TAILQ_REMOVE(&sc->ready_list, acb, chain); 860 ACB_SETQ(acb, ACB_QNONE); 861 sc->sc_nexus = acb; 862 sc->sc_flags = 0; 863 sc->sc_prevphase = INVALID_PHASE; 864 sc->sc_dp = acb->daddr; 865 sc->sc_dleft = acb->dleft; 866 ti->lubusy |= (1<<sc_link->scsipi_scsi.lun); 867 mhaselect(sc, t, sc_link->scsipi_scsi.lun, 868 (u_char *)&acb->cmd, acb->clen); 869 break; 870 } else { 871 SPC_MISC(("%d:%d busy\n", 872 sc_link->scsipi_scsi.target, 873 sc_link->scsipi_scsi.lun)); 874 } 875 } 876 } 877 878 void 880 mha_sense(sc, acb) 881 struct mha_softc *sc; 882 struct acb *acb; 883 { 884 struct scsipi_xfer *xs = acb->xs; 885 struct scsipi_link *sc_link = xs->sc_link; 886 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 887 struct scsipi_sense *ss = (void *)&acb->cmd; 888 889 SPC_MISC(("requesting sense ")); 890 /* Next, setup a request sense command block */ 891 bzero(ss, sizeof(*ss)); 892 ss->opcode = REQUEST_SENSE; 893 ss->byte2 = sc_link->scsipi_scsi.lun << 5; 894 ss->length = sizeof(struct scsipi_sense_data); 895 acb->clen = sizeof(*ss); 896 acb->daddr = (char *)&xs->sense; 897 acb->dleft = sizeof(struct scsipi_sense_data); 898 acb->flags |= ACB_CHKSENSE; 899 ti->senses++; 900 if (acb->flags & ACB_QNEXUS) 901 ti->lubusy &= ~(1 << sc_link->scsipi_scsi.lun); 902 if (acb == sc->sc_nexus) { 903 mhaselect(sc, sc_link->scsipi_scsi.target, 904 sc_link->scsipi_scsi.lun, 905 (void *)&acb->cmd, acb->clen); 906 } else { 907 mha_dequeue(sc, acb); 908 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 909 if (sc->sc_state == SPC_IDLE) 910 mha_sched(sc); 911 } 912 } 913 914 /* 915 * POST PROCESSING OF SCSI_CMD (usually current) 916 */ 917 void 918 mha_done(sc, acb) 919 struct mha_softc *sc; 920 struct acb *acb; 921 { 922 struct scsipi_xfer *xs = acb->xs; 923 struct scsipi_link *sc_link = xs->sc_link; 924 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 925 926 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 927 928 #if 1 929 callout_stop(&acb->xs->xs_callout); 930 #endif 931 932 /* 933 * Now, if we've come here with no error code, i.e. we've kept the 934 * initial XS_NOERROR, and the status code signals that we should 935 * check sense, we'll need to set up a request sense cmd block and 936 * push the command back into the ready queue *before* any other 937 * commands for this target/lunit, else we lose the sense info. 938 * We don't support chk sense conditions for the request sense cmd. 939 */ 940 if (xs->error == XS_NOERROR) { 941 if ((acb->flags & ACB_ABORTED) != 0) { 942 xs->error = XS_TIMEOUT; 943 } else if (acb->flags & ACB_CHKSENSE) { 944 xs->error = XS_SENSE; 945 } else { 946 switch (acb->stat & ST_MASK) { 947 case SCSI_CHECK: 948 { 949 struct scsipi_sense *ss = (void *)&acb->cmd; 950 SPC_MISC(("requesting sense ")); 951 /* First, save the return values */ 952 xs->resid = acb->dleft; 953 xs->status = acb->stat; 954 /* Next, setup a request sense command block */ 955 bzero(ss, sizeof(*ss)); 956 ss->opcode = REQUEST_SENSE; 957 /*ss->byte2 = sc_link->lun << 5;*/ 958 ss->length = sizeof(struct scsipi_sense_data); 959 acb->clen = sizeof(*ss); 960 acb->daddr = (char *)&xs->sense; 961 acb->dleft = sizeof(struct scsipi_sense_data); 962 acb->flags |= ACB_CHKSENSE; 963 /*XXX - must take off queue here */ 964 if (acb != sc->sc_nexus) { 965 panic("%s: mha_sched: floating acb %p", 966 sc->sc_dev.dv_xname, acb); 967 } 968 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 969 ACB_SETQ(acb, ACB_QREADY); 970 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 971 ti->senses++; 972 callout_reset(&acb->xs->xs_callout, 973 (xs->timeout*hz)/1000, mha_timeout, acb); 974 if (sc->sc_nexus == acb) { 975 sc->sc_nexus = NULL; 976 sc->sc_state = SPC_IDLE; 977 mha_sched(sc); 978 } 979 #if 0 980 mha_sense(sc, acb); 981 #endif 982 return; 983 } 984 case SCSI_BUSY: 985 xs->error = XS_BUSY; 986 break; 987 case SCSI_OK: 988 xs->resid = acb->dleft; 989 break; 990 default: 991 xs->error = XS_DRIVER_STUFFUP; 992 #if SPC_DEBUG 993 printf("%s: mha_done: bad stat 0x%x\n", 994 sc->sc_dev.dv_xname, acb->stat); 995 #endif 996 break; 997 } 998 } 999 } 1000 1001 xs->xs_status |= XS_STS_DONE; 1002 1003 #if SPC_DEBUG 1004 if ((mha_debug & SPC_SHOWMISC) != 0) { 1005 if (xs->resid != 0) 1006 printf("resid=%d ", xs->resid); 1007 if (xs->error == XS_SENSE) 1008 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 1009 else 1010 printf("error=%d\n", xs->error); 1011 } 1012 #endif 1013 1014 /* 1015 * Remove the ACB from whatever queue it's on. 1016 */ 1017 switch (acb->flags & ACB_QBITS) { 1018 case ACB_QNONE: 1019 if (acb != sc->sc_nexus) { 1020 panic("%s: floating acb", sc->sc_dev.dv_xname); 1021 } 1022 sc->sc_nexus = NULL; 1023 sc->sc_state = SPC_IDLE; 1024 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1025 mha_sched(sc); 1026 break; 1027 case ACB_QREADY: 1028 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1029 break; 1030 case ACB_QNEXUS: 1031 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1032 ti->lubusy &= ~(1<<sc_link->scsipi_scsi.lun); 1033 break; 1034 case ACB_QFREE: 1035 panic("%s: dequeue: busy acb on free list", 1036 sc->sc_dev.dv_xname); 1037 break; 1038 default: 1039 panic("%s: dequeue: unknown queue %d", 1040 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1041 } 1042 1043 /* Put it on the free list, and clear flags. */ 1044 #if 0 1045 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1046 acb->flags = ACB_QFREE; 1047 #else 1048 mha_free_acb(sc, acb, xs->xs_control); 1049 #endif 1050 1051 ti->cmds++; 1052 scsipi_done(xs); 1053 } 1054 1055 void 1056 mha_dequeue(sc, acb) 1057 struct mha_softc *sc; 1058 struct acb *acb; 1059 { 1060 1061 if (acb->flags & ACB_QNEXUS) { 1062 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1063 } else { 1064 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1065 } 1066 } 1067 1068 /* 1070 * INTERRUPT/PROTOCOL ENGINE 1071 */ 1072 1073 /* 1074 * Schedule an outgoing message by prioritizing it, and asserting 1075 * attention on the bus. We can only do this when we are the initiator 1076 * else there will be an illegal command interrupt. 1077 */ 1078 #define mha_sched_msgout(m) \ 1079 do { \ 1080 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1081 CMR = CMD_SET_ATN; \ 1082 sc->sc_msgpriq |= (m); \ 1083 } while (0) 1084 1085 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1086 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1087 #define ISEXTMSG(m) ((m) == 0x01) 1088 1089 /* 1090 * Precondition: 1091 * The SCSI bus is already in the MSGI phase and there is a message byte 1092 * on the bus, along with an asserted REQ signal. 1093 */ 1094 void 1095 mha_msgin(sc) 1096 register struct mha_softc *sc; 1097 { 1098 register int v; 1099 int n; 1100 1101 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1102 1103 /* 1104 * Prepare for a new message. A message should (according 1105 * to the SCSI standard) be transmitted in one single 1106 * MESSAGE_IN_PHASE. If we have been in some other phase, 1107 * then this is a new message. 1108 */ 1109 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1110 sc->sc_flags &= ~SPC_DROP_MSGI; 1111 sc->sc_imlen = 0; 1112 } 1113 1114 WAIT; 1115 1116 v = MBR; /* modified byte */ 1117 v = sc->sc_pcx[0]; 1118 1119 sc->sc_imess[sc->sc_imlen] = v; 1120 1121 /* 1122 * If we're going to reject the message, don't bother storing 1123 * the incoming bytes. But still, we need to ACK them. 1124 */ 1125 1126 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1127 CMR = CMD_SET_ATN; 1128 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1129 printf("<dropping msg byte %x>", 1130 sc->sc_imess[sc->sc_imlen]); 1131 return; 1132 } 1133 1134 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1135 mha_sched_msgout(SEND_REJECT); 1136 sc->sc_flags |= SPC_DROP_MSGI; 1137 } else { 1138 sc->sc_imlen++; 1139 /* 1140 * This testing is suboptimal, but most 1141 * messages will be of the one byte variety, so 1142 * it should not effect performance 1143 * significantly. 1144 */ 1145 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1146 goto gotit; 1147 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1148 goto gotit; 1149 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1150 sc->sc_imlen == sc->sc_imess[1] + 2) 1151 goto gotit; 1152 } 1153 #if 0 1154 /* Ack what we have so far */ 1155 ESPCMD(sc, ESPCMD_MSGOK); 1156 #endif 1157 return; 1158 1159 gotit: 1160 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1161 /* 1162 * Now we should have a complete message (1 byte, 2 byte 1163 * and moderately long extended messages). We only handle 1164 * extended messages which total length is shorter than 1165 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1166 */ 1167 if (sc->sc_state == SPC_HASNEXUS) { 1168 struct acb *acb = sc->sc_nexus; 1169 struct spc_tinfo *ti = 1170 &sc->sc_tinfo[acb->xs->sc_link->scsipi_scsi.target]; 1171 1172 switch (sc->sc_imess[0]) { 1173 case MSG_CMDCOMPLETE: 1174 SPC_MSGS(("cmdcomplete ")); 1175 if (sc->sc_dleft < 0) { 1176 struct scsipi_link *sc_link = acb->xs->sc_link; 1177 printf("mha: %d extra bytes from %d:%d\n", 1178 -sc->sc_dleft, 1179 sc_link->scsipi_scsi.target, 1180 sc_link->scsipi_scsi.lun); 1181 sc->sc_dleft = 0; 1182 } 1183 acb->xs->resid = acb->dleft = sc->sc_dleft; 1184 sc->sc_flags |= SPC_BUSFREE_OK; 1185 break; 1186 1187 case MSG_MESSAGE_REJECT: 1188 #if SPC_DEBUG 1189 if (mha_debug & SPC_SHOWMSGS) 1190 printf("%s: our msg rejected by target\n", 1191 sc->sc_dev.dv_xname); 1192 #endif 1193 #if 1 /* XXX - must remember last message */ 1194 scsi_print_addr(acb->xs->sc_link); 1195 printf("MSG_MESSAGE_REJECT>>"); 1196 #endif 1197 if (sc->sc_flags & SPC_SYNCHNEGO) { 1198 ti->period = ti->offset = 0; 1199 sc->sc_flags &= ~SPC_SYNCHNEGO; 1200 ti->flags &= ~T_NEGOTIATE; 1201 } 1202 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1203 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1204 mha_sched_msgout(SEND_ABORT); 1205 break; 1206 case MSG_NOOP: 1207 SPC_MSGS(("noop ")); 1208 break; 1209 case MSG_DISCONNECT: 1210 SPC_MSGS(("disconnect ")); 1211 ti->dconns++; 1212 sc->sc_flags |= SPC_DISCON; 1213 sc->sc_flags |= SPC_BUSFREE_OK; 1214 if ((acb->xs->sc_link->quirks & SDEV_AUTOSAVE) == 0) 1215 break; 1216 /*FALLTHROUGH*/ 1217 case MSG_SAVEDATAPOINTER: 1218 SPC_MSGS(("save datapointer ")); 1219 acb->dleft = sc->sc_dleft; 1220 acb->daddr = sc->sc_dp; 1221 break; 1222 case MSG_RESTOREPOINTERS: 1223 SPC_MSGS(("restore datapointer ")); 1224 if (!acb) { 1225 mha_sched_msgout(SEND_ABORT); 1226 printf("%s: no DATAPOINTERs to restore\n", 1227 sc->sc_dev.dv_xname); 1228 break; 1229 } 1230 sc->sc_dp = acb->daddr; 1231 sc->sc_dleft = acb->dleft; 1232 break; 1233 case MSG_PARITY_ERROR: 1234 printf("%s:target%d: MSG_PARITY_ERROR\n", 1235 sc->sc_dev.dv_xname, 1236 acb->xs->sc_link->scsipi_scsi.target); 1237 break; 1238 case MSG_EXTENDED: 1239 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1240 switch (sc->sc_imess[2]) { 1241 case MSG_EXT_SDTR: 1242 SPC_MSGS(("SDTR period %d, offset %d ", 1243 sc->sc_imess[3], sc->sc_imess[4])); 1244 ti->period = sc->sc_imess[3]; 1245 ti->offset = sc->sc_imess[4]; 1246 if (sc->sc_minsync == 0) { 1247 /* We won't do synch */ 1248 ti->offset = 0; 1249 mha_sched_msgout(SEND_SDTR); 1250 } else if (ti->offset == 0) { 1251 printf("%s:%d: async\n", "mha", 1252 acb->xs->sc_link->scsipi_scsi.target); 1253 ti->offset = 0; 1254 sc->sc_flags &= ~SPC_SYNCHNEGO; 1255 } else if (ti->period > 124) { 1256 printf("%s:%d: async\n", "mha", 1257 acb->xs->sc_link->scsipi_scsi.target); 1258 ti->offset = 0; 1259 mha_sched_msgout(SEND_SDTR); 1260 } else { 1261 int r = 250/ti->period; 1262 int s = (100*250)/ti->period - 100*r; 1263 int p; 1264 #if 0 1265 p = mha_stp2cpb(sc, ti->period); 1266 ti->period = mha_cpb2stp(sc, p); 1267 #endif 1268 1269 #if SPC_DEBUG 1270 scsi_print_addr(acb->xs->sc_link); 1271 #endif 1272 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1273 /* Target initiated negotiation */ 1274 if (ti->flags & T_SYNCMODE) { 1275 ti->flags &= ~T_SYNCMODE; 1276 #if SPC_DEBUG 1277 printf("renegotiated "); 1278 #endif 1279 } 1280 TMR=TM_ASYNC; 1281 /* Clamp to our maxima */ 1282 if (ti->period < sc->sc_minsync) 1283 ti->period = sc->sc_minsync; 1284 if (ti->offset > 15) 1285 ti->offset = 15; 1286 mha_sched_msgout(SEND_SDTR); 1287 } else { 1288 /* we are sync */ 1289 sc->sc_flags &= ~SPC_SYNCHNEGO; 1290 TMR = TM_SYNC; 1291 ti->flags |= T_SYNCMODE; 1292 } 1293 #if SPC_DEBUG 1294 printf("max sync rate %d.%02dMb/s\n", 1295 r, s); 1296 #endif 1297 } 1298 ti->flags &= ~T_NEGOTIATE; 1299 break; 1300 default: /* Extended messages we don't handle */ 1301 CMR = CMD_SET_ATN; /* XXX? */ 1302 break; 1303 } 1304 break; 1305 default: 1306 SPC_MSGS(("ident ")); 1307 /* thanks for that ident... */ 1308 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1309 SPC_MISC(("unknown ")); 1310 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1311 CMR = CMD_SET_ATN; /* XXX? */ 1312 } 1313 break; 1314 } 1315 } else if (sc->sc_state == SPC_RESELECTED) { 1316 struct scsipi_link *sc_link = NULL; 1317 struct acb *acb; 1318 struct spc_tinfo *ti; 1319 u_char lunit; 1320 1321 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1322 SPC_MISC(("searching ")); 1323 /* 1324 * Search wait queue for disconnected cmd 1325 * The list should be short, so I haven't bothered with 1326 * any more sophisticated structures than a simple 1327 * singly linked list. 1328 */ 1329 lunit = sc->sc_imess[0] & 0x07; 1330 for (acb = sc->nexus_list.tqh_first; acb; 1331 acb = acb->chain.tqe_next) { 1332 sc_link = acb->xs->sc_link; 1333 if (sc_link->scsipi_scsi.lun == lunit && 1334 sc->sc_selid == (1<<sc_link->scsipi_scsi.target)) { 1335 TAILQ_REMOVE(&sc->nexus_list, acb, 1336 chain); 1337 ACB_SETQ(acb, ACB_QNONE); 1338 break; 1339 } 1340 } 1341 1342 if (!acb) { /* Invalid reselection! */ 1343 mha_sched_msgout(SEND_ABORT); 1344 printf("mha: invalid reselect (idbit=0x%2x)\n", 1345 sc->sc_selid); 1346 } else { /* Reestablish nexus */ 1347 /* 1348 * Setup driver data structures and 1349 * do an implicit RESTORE POINTERS 1350 */ 1351 ti = &sc->sc_tinfo[sc_link->scsipi_scsi.target]; 1352 sc->sc_nexus = acb; 1353 sc->sc_dp = acb->daddr; 1354 sc->sc_dleft = acb->dleft; 1355 sc->sc_tinfo[sc_link->scsipi_scsi.target].lubusy 1356 |= (1<<sc_link->scsipi_scsi.lun); 1357 if (ti->flags & T_SYNCMODE) { 1358 TMR = TM_SYNC; /* XXX */ 1359 } else { 1360 TMR = TM_ASYNC; 1361 } 1362 SPC_MISC(("... found acb")); 1363 sc->sc_state = SPC_HASNEXUS; 1364 } 1365 } else { 1366 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1367 sc->sc_dev.dv_xname, sc->sc_selid); 1368 mha_sched_msgout(SEND_DEV_RESET); 1369 } 1370 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1371 printf("%s: unexpected message in; will send DEV_RESET\n", 1372 sc->sc_dev.dv_xname); 1373 mha_sched_msgout(SEND_DEV_RESET); 1374 } 1375 1376 /* Ack last message byte */ 1377 #if 0 1378 ESPCMD(sc, ESPCMD_MSGOK); 1379 #endif 1380 1381 /* Done, reset message pointer. */ 1382 sc->sc_flags &= ~SPC_DROP_MSGI; 1383 sc->sc_imlen = 0; 1384 } 1385 1386 /* 1387 * Send the highest priority, scheduled message. 1388 */ 1389 void 1390 mha_msgout(sc) 1391 register struct mha_softc *sc; 1392 { 1393 struct spc_tinfo *ti; 1394 int n; 1395 1396 SPC_TRACE(("mha_msgout ")); 1397 1398 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1399 if (sc->sc_omp == sc->sc_omess) { 1400 /* 1401 * This is a retransmission. 1402 * 1403 * We get here if the target stayed in MESSAGE OUT 1404 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1405 * that all of the previously transmitted messages must 1406 * be sent again, in the same order. Therefore, we 1407 * requeue all the previously transmitted messages, and 1408 * start again from the top. Our simple priority 1409 * scheme keeps the messages in the right order. 1410 */ 1411 SPC_MISC(("retransmitting ")); 1412 sc->sc_msgpriq |= sc->sc_msgoutq; 1413 /* 1414 * Set ATN. If we're just sending a trivial 1-byte 1415 * message, we'll clear ATN later on anyway. 1416 */ 1417 CMR = CMD_SET_ATN; /* XXX? */ 1418 } else { 1419 /* This is a continuation of the previous message. */ 1420 n = sc->sc_omp - sc->sc_omess; 1421 goto nextbyte; 1422 } 1423 } 1424 1425 /* No messages transmitted so far. */ 1426 sc->sc_msgoutq = 0; 1427 sc->sc_lastmsg = 0; 1428 1429 nextmsg: 1430 /* Pick up highest priority message. */ 1431 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1432 sc->sc_msgpriq &= ~sc->sc_currmsg; 1433 sc->sc_msgoutq |= sc->sc_currmsg; 1434 1435 /* Build the outgoing message data. */ 1436 switch (sc->sc_currmsg) { 1437 case SEND_IDENTIFY: 1438 SPC_ASSERT(sc->sc_nexus != NULL); 1439 sc->sc_omess[0] = 1440 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->scsipi_scsi.lun, 1); 1441 n = 1; 1442 break; 1443 1444 #if SPC_USE_SYNCHRONOUS 1445 case SEND_SDTR: 1446 SPC_ASSERT(sc->sc_nexus != NULL); 1447 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1448 sc->sc_omess[4] = MSG_EXTENDED; 1449 sc->sc_omess[3] = 3; 1450 sc->sc_omess[2] = MSG_EXT_SDTR; 1451 sc->sc_omess[1] = ti->period >> 2; 1452 sc->sc_omess[0] = ti->offset; 1453 n = 5; 1454 break; 1455 #endif 1456 1457 #if SPC_USE_WIDE 1458 case SEND_WDTR: 1459 SPC_ASSERT(sc->sc_nexus != NULL); 1460 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 1461 sc->sc_omess[3] = MSG_EXTENDED; 1462 sc->sc_omess[2] = 2; 1463 sc->sc_omess[1] = MSG_EXT_WDTR; 1464 sc->sc_omess[0] = ti->width; 1465 n = 4; 1466 break; 1467 #endif 1468 1469 case SEND_DEV_RESET: 1470 sc->sc_flags |= SPC_ABORTING; 1471 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1472 n = 1; 1473 break; 1474 1475 case SEND_REJECT: 1476 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1477 n = 1; 1478 break; 1479 1480 case SEND_PARITY_ERROR: 1481 sc->sc_omess[0] = MSG_PARITY_ERROR; 1482 n = 1; 1483 break; 1484 1485 case SEND_INIT_DET_ERR: 1486 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1487 n = 1; 1488 break; 1489 1490 case SEND_ABORT: 1491 sc->sc_flags |= SPC_ABORTING; 1492 sc->sc_omess[0] = MSG_ABORT; 1493 n = 1; 1494 break; 1495 1496 default: 1497 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1498 sc->sc_dev.dv_xname); 1499 SPC_BREAK(); 1500 sc->sc_omess[0] = MSG_NOOP; 1501 n = 1; 1502 break; 1503 } 1504 sc->sc_omp = &sc->sc_omess[n]; 1505 1506 nextbyte: 1507 /* Send message bytes. */ 1508 /* send TRANSFER command. */ 1509 sc->sc_ps[3] = 1; 1510 sc->sc_ps[4] = n >> 8; 1511 sc->sc_pc[10] = n; 1512 sc->sc_ps[-1] = 0x000F; /* burst */ 1513 asm volatile ("nop"); 1514 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1515 for (;;) { 1516 if ((SSR & SS_BUSY) != 0) 1517 break; 1518 if (SSR & SS_IREQUEST) 1519 goto out; 1520 } 1521 for (;;) { 1522 #if 0 1523 for (;;) { 1524 if ((PSNS & PSNS_REQ) != 0) 1525 break; 1526 /* Wait for REQINIT. XXX Need timeout. */ 1527 } 1528 #endif 1529 if (SSR & SS_IREQUEST) { 1530 /* 1531 * Target left MESSAGE OUT, possibly to reject 1532 * our message. 1533 * 1534 * If this is the last message being sent, then we 1535 * deassert ATN, since either the target is going to 1536 * ignore this message, or it's going to ask for a 1537 * retransmission via MESSAGE PARITY ERROR (in which 1538 * case we reassert ATN anyway). 1539 */ 1540 #if 0 1541 if (sc->sc_msgpriq == 0) 1542 CMR = CMD_RESET_ATN; 1543 #endif 1544 goto out; 1545 } 1546 1547 #if 0 1548 /* Clear ATN before last byte if this is the last message. */ 1549 if (n == 1 && sc->sc_msgpriq == 0) 1550 CMR = CMD_RESET_ATN; 1551 #endif 1552 1553 while ((SSR & SS_DREG_FULL) != 0) 1554 ; 1555 /* Send message byte. */ 1556 sc->sc_pc[0] = *--sc->sc_omp; 1557 --n; 1558 /* Keep track of the last message we've sent any bytes of. */ 1559 sc->sc_lastmsg = sc->sc_currmsg; 1560 1561 if (n == 0) 1562 break; 1563 } 1564 1565 /* We get here only if the entire message has been transmitted. */ 1566 if (sc->sc_msgpriq != 0) { 1567 /* There are more outgoing messages. */ 1568 goto nextmsg; 1569 } 1570 1571 /* 1572 * The last message has been transmitted. We need to remember the last 1573 * message transmitted (in case the target switches to MESSAGE IN phase 1574 * and sends a MESSAGE REJECT), and the list of messages transmitted 1575 * this time around (in case the target stays in MESSAGE OUT phase to 1576 * request a retransmit). 1577 */ 1578 1579 out: 1580 /* Disable REQ/ACK protocol. */ 1581 } 1582 1583 1584 /*************************************************************** 1586 * 1587 * datain/dataout 1588 * 1589 */ 1590 1591 int 1592 mha_datain_pio(sc, p, n) 1593 register struct mha_softc *sc; 1594 u_char *p; 1595 int n; 1596 { 1597 u_short d; 1598 int a; 1599 int total_n = n; 1600 1601 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1602 1603 WAIT; 1604 sc->sc_ps[3] = 1; 1605 sc->sc_ps[4] = n >> 8; 1606 sc->sc_pc[10] = n; 1607 /* $BHa$7$-%=%U%HE>Aw(B */ 1608 CMR = CMD_RECEIVE_TO_MPU; 1609 for (;;) { 1610 a = SSR; 1611 if (a & 0x04) { 1612 d = sc->sc_ps[0]; 1613 *p++ = d >> 8; 1614 if (--n > 0) { 1615 *p++ = d; 1616 --n; 1617 } 1618 a = SSR; 1619 } 1620 if (a & 0x40) 1621 continue; 1622 if (a & 0x80) 1623 break; 1624 } 1625 SPC_TRACE(("...%d resd]", n)); 1626 return total_n - n; 1627 } 1628 1629 int 1630 mha_dataout_pio(sc, p, n) 1631 register struct mha_softc *sc; 1632 u_char *p; 1633 int n; 1634 { 1635 u_short d; 1636 int a; 1637 int total_n = n; 1638 1639 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1640 1641 WAIT; 1642 sc->sc_ps[3] = 1; 1643 sc->sc_ps[4] = n >> 8; 1644 sc->sc_pc[10] = n; 1645 /* $BHa$7$-%=%U%HE>Aw(B */ 1646 CMR = CMD_SEND_FROM_MPU; 1647 for (;;) { 1648 a = SSR; 1649 if (a & 0x04) { 1650 d = *p++ << 8; 1651 if (--n > 0) { 1652 d |= *p++; 1653 --n; 1654 } 1655 sc->sc_ps[0] = d; 1656 a = SSR; 1657 } 1658 if (a & 0x40) 1659 continue; 1660 if (a & 0x80) 1661 break; 1662 } 1663 SPC_TRACE(("...%d resd]", n)); 1664 return total_n - n; 1665 } 1666 1667 static int 1668 mha_dataio_dma(dw, cw, sc, p, n) 1669 int dw; /* DMA word */ 1670 int cw; /* CMR word */ 1671 register struct mha_softc *sc; 1672 u_char *p; 1673 int n; 1674 { 1675 char *paddr, *vaddr; 1676 1677 if (n > MAXBSIZE) 1678 panic("transfer size exceeds MAXBSIZE"); 1679 if (sc->sc_dmasize > 0) 1680 panic("DMA request while another DMA transfer is in pregress"); 1681 1682 if (cw == CMD_SEND_FROM_DMA) { 1683 memcpy(sc->sc_dmabuf, p, n); 1684 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1685 } else { 1686 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1687 } 1688 sc->sc_p = p; 1689 sc->sc_dmasize = n; 1690 1691 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1692 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1693 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1694 dw &= ~(1 << 3); 1695 #endif 1696 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1697 #if 0 1698 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1699 PCIA(); /* XXX */ 1700 #endif 1701 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1702 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1703 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1704 WAIT; 1705 sc->sc_ps[3] = 1; 1706 sc->sc_ps[4] = n >> 8; 1707 sc->sc_pc[10] = n; 1708 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1709 3 ... short bus cycle 1710 2 ... MAXIMUM XFER. 1711 1 ... BURST XFER. 1712 0 ... R/W */ 1713 sc->sc_ps[-1] = dw; /* burst */ 1714 asm volatile ("nop"); 1715 CMR = cw; /* receive to DMA */ 1716 return n; 1717 } 1718 int 1719 mha_dataout(sc, p, n) 1720 register struct mha_softc *sc; 1721 u_char *p; 1722 int n; 1723 { 1724 register struct acb *acb = sc->sc_nexus; 1725 1726 if (n == 0) 1727 return n; 1728 1729 if (n & 1) 1730 return mha_dataout_pio(sc, p, n); 1731 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1732 } 1733 1734 int 1736 mha_datain(sc, p, n) 1737 register struct mha_softc *sc; 1738 u_char *p; 1739 int n; 1740 { 1741 int ts; 1742 register struct acb *acb = sc->sc_nexus; 1743 char *paddr, *vaddr; 1744 1745 if (n == 0) 1746 return n; 1747 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1748 return mha_datain_pio(sc, p, n); 1749 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1750 } 1751 1752 1754 /* 1755 * Catch an interrupt from the adaptor 1756 */ 1757 /* 1758 * This is the workhorse routine of the driver. 1759 * Deficiencies (for now): 1760 * 1) always uses programmed I/O 1761 */ 1762 int 1763 mhaintr(arg) 1764 void *arg; 1765 { 1766 struct mha_softc *sc = arg; 1767 #if 0 1768 u_char ints; 1769 #endif 1770 struct acb *acb; 1771 struct scsipi_link *sc_link; 1772 struct spc_tinfo *ti; 1773 u_char ph; 1774 u_short r; 1775 int n; 1776 1777 #if 1 /* XXX called during attach? */ 1778 if (tmpsc != NULL) { 1779 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1780 sc = tmpsc; 1781 } else { 1782 #endif 1783 1784 #if 1 /* XXX */ 1785 } 1786 #endif 1787 1788 #if 0 1789 /* 1790 * $B3d$j9~$_6X;_$K$9$k(B 1791 */ 1792 SCTL &= ~SCTL_INTR_ENAB; 1793 #endif 1794 1795 SPC_TRACE(("[mhaintr]")); 1796 1797 loop: 1798 /* 1799 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1800 */ 1801 /* 1802 * First check for abnormal conditions, such as reset. 1803 */ 1804 #if 0 1805 #if 1 /* XXX? */ 1806 while (((ints = SSR) & SS_IREQUEST) == 0) 1807 delay(1); 1808 SPC_MISC(("ints = 0x%x ", ints)); 1809 #else /* usually? */ 1810 ints = SSR; 1811 #endif 1812 #endif 1813 while (SSR & SS_IREQUEST) { 1814 acb = sc->sc_nexus; 1815 r = ISCSR; 1816 SPC_MISC(("[r=0x%x]", r)); 1817 switch (r >> 8) { 1818 default: 1819 printf("[addr=%x\n" 1820 "result=0x%x\n" 1821 "cmd=0x%x\n" 1822 "ph=0x%x(ought to be %d)]\n", 1823 &ISCSR, 1824 r, 1825 acb->xs->cmd->opcode, 1826 SCR, sc->sc_phase); 1827 panic("unexpected result."); 1828 case 0x82: /* selection timeout */ 1829 SPC_MISC(("selection timeout ")); 1830 sc->sc_phase = BUSFREE_PHASE; 1831 SPC_ASSERT(sc->sc_nexus != NULL); 1832 acb = sc->sc_nexus; 1833 delay(250); 1834 acb->xs->error = XS_SELTIMEOUT; 1835 mha_done(sc, acb); 1836 continue; /* XXX ??? msaitoh */ 1837 case 0x60: /* command completed */ 1838 sc->sc_spcinitialized++; 1839 if (sc->sc_phase == BUSFREE_PHASE) 1840 continue; 1841 ph = SCR; 1842 if (ph & PSNS_ACK) { 1843 int s; 1844 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1845 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1846 ph & PHASE_MASK, sc->sc_phase)); 1847 #if 0 1848 /* switch (sc->sc_phase) {*/ 1849 #else 1850 switch (ph & PHASE_MASK) { 1851 #endif 1852 case STATUS_PHASE: 1853 if (sc->sc_state != SPC_HASNEXUS) 1854 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1855 sc->sc_state); 1856 SPC_ASSERT(sc->sc_nexus != NULL); 1857 acb = sc->sc_nexus; 1858 WAIT; 1859 s = MBR; 1860 SPC_ASSERT(s == 1); 1861 acb->stat = sc->sc_pcx[0]; /* XXX */ 1862 SPC_MISC(("stat=0x%02x ", acb->stat)); 1863 sc->sc_prevphase = STATUS_PHASE; 1864 break; 1865 case MESSAGE_IN_PHASE: 1866 mha_msgin(sc); 1867 sc->sc_prevphase = MESSAGE_IN_PHASE; 1868 /* thru */ 1869 case DATA_IN_PHASE: 1870 if (sc->sc_dmasize == 0) 1871 break; 1872 bus_dmamap_sync(sc->sc_dmat, 1873 sc->sc_dmamap, 1874 0, sc->sc_dmasize, 1875 BUS_DMASYNC_POSTREAD); 1876 memcpy(sc->sc_p, sc->sc_dmabuf, 1877 sc->sc_dmasize); 1878 sc->sc_dmasize = 0; 1879 break; 1880 case DATA_OUT_PHASE: 1881 if (sc->sc_dmasize == 0) 1882 break; 1883 bus_dmamap_sync(sc->sc_dmat, 1884 sc->sc_dmamap, 1885 0, sc->sc_dmasize, 1886 BUS_DMASYNC_POSTWRITE); 1887 sc->sc_dmasize = 0; 1888 break; 1889 } 1890 WAIT; 1891 CMR = CMD_RESET_ACK; /* reset ack */ 1892 /*mha_done(sc, acb); XXX */ 1893 continue; 1894 } else if (NSR & 0x80) { /* nexus */ 1895 #if 1 1896 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1897 sc->sc_state = SPC_HASNEXUS; 1898 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1899 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1900 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1901 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1902 WAIT; 1903 if (SSR & SS_IREQUEST) 1904 continue; 1905 switch (sc->sc_phase) { 1906 default: 1907 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1908 case MESSAGE_IN_PHASE: 1909 /* $B2?$b$7$J$$(B */ 1910 continue; 1911 case STATUS_PHASE: 1912 sc->sc_phase = MESSAGE_IN_PHASE; 1913 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1914 continue; 1915 case DATA_IN_PHASE: 1916 sc->sc_prevphase = DATA_IN_PHASE; 1917 if (sc->sc_dleft == 0) { 1918 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1919 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1920 sc->sc_phase = STATUS_PHASE; 1921 CMR = CMD_RECEIVE_STS; /* receive sts */ 1922 continue; 1923 } 1924 n = mha_datain(sc, sc->sc_dp, 1925 sc->sc_dleft); 1926 sc->sc_dp += n; 1927 sc->sc_dleft -= n; 1928 continue; 1929 case DATA_OUT_PHASE: 1930 sc->sc_prevphase = DATA_OUT_PHASE; 1931 if (sc->sc_dleft == 0) { 1932 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1933 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1934 sc->sc_phase = STATUS_PHASE; 1935 CMR = CMD_RECEIVE_STS; /* receive sts */ 1936 continue; 1937 } 1938 /* data phase $B$NB3$-$r$d$m$&(B */ 1939 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1940 sc->sc_dp += n; 1941 sc->sc_dleft -= n; 1942 continue; 1943 case COMMAND_PHASE: 1944 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1945 if (acb->dleft) { 1946 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1947 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1948 sc->sc_phase = DATA_IN_PHASE; 1949 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1950 sc->sc_dp += n; 1951 sc->sc_dleft -= n; 1952 } 1953 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1954 sc->sc_phase = DATA_OUT_PHASE; 1955 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1956 sc->sc_dp += n; 1957 sc->sc_dleft -= n; 1958 } 1959 continue; 1960 } 1961 else { 1962 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1963 WAIT; 1964 sc->sc_phase = STATUS_PHASE; 1965 CMR = CMD_RECEIVE_STS; /* receive sts */ 1966 continue; 1967 } 1968 } 1969 #endif 1970 } 1971 continue; 1972 case 0x31: /* disconnected in xfer progress. */ 1973 SPC_MISC(("[0x31]")); 1974 case 0x70: /* disconnected. */ 1975 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1976 sc->sc_phase = BUSFREE_PHASE; 1977 sc->sc_state = SPC_IDLE; 1978 #if 1 1979 acb = sc->sc_nexus; 1980 SPC_ASSERT(sc->sc_nexus != NULL); 1981 acb->xs->error = XS_NOERROR; 1982 mha_done(sc, acb); 1983 #else 1984 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1985 mha_sched(sc); 1986 #endif 1987 continue; 1988 case 0x32: /* phase error in xfer progress. */ 1989 SPC_MISC(("[0x32]")); 1990 #if 0 1991 case 0x65: /* invalid command. 1992 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1993 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1994 #if 1 1995 SPC_MISC(("[0x%04x]", r)); 1996 #endif 1997 #endif 1998 case 0x54: /* initial-phase error. */ 1999 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 2000 NSR, 2001 SCR, sc->sc_phase)); 2002 /* thru */ 2003 case 0x71: /* assert req */ 2004 WAIT; 2005 if (SSR & 0x40) { 2006 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 2007 SSR, r, NSR, SCR); 2008 WAIT; 2009 } 2010 ph = SCR; 2011 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 2012 sc->sc_state = SPC_HASNEXUS; 2013 } 2014 if (ph & 0x80) { 2015 switch (ph & PHASE_MASK) { 2016 default: 2017 printf("phase = %x\n", ph); 2018 panic("assert req: the phase I don't know!"); 2019 case DATA_IN_PHASE: 2020 sc->sc_prevphase = DATA_IN_PHASE; 2021 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 2022 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 2023 sc->sc_dp += n; 2024 sc->sc_dleft -= n; 2025 SPC_MISC(("done\n")); 2026 continue; 2027 case DATA_OUT_PHASE: 2028 sc->sc_prevphase = DATA_OUT_PHASE; 2029 SPC_MISC(("DATAOUT\n")); 2030 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 2031 sc->sc_dp += n; 2032 sc->sc_dleft -= n; 2033 continue; 2034 case STATUS_PHASE: 2035 sc->sc_phase = STATUS_PHASE; 2036 SPC_MISC(("[RECV_STS]")); 2037 WAIT; 2038 CMR = CMD_RECEIVE_STS; /* receive sts */ 2039 continue; 2040 case MESSAGE_IN_PHASE: 2041 sc->sc_phase = MESSAGE_IN_PHASE; 2042 WAIT; 2043 CMR = CMD_RECEIVE_MSG; 2044 continue; 2045 } 2046 } 2047 continue; 2048 } 2049 } 2050 } 2051 2052 void 2053 mha_abort(sc, acb) 2054 struct mha_softc *sc; 2055 struct acb *acb; 2056 { 2057 acb->flags |= ACB_ABORTED; 2058 2059 if (acb == sc->sc_nexus) { 2060 /* 2061 * If we're still selecting, the message will be scheduled 2062 * after selection is complete. 2063 */ 2064 if (sc->sc_state == SPC_HASNEXUS) { 2065 sc->sc_flags |= SPC_ABORTING; 2066 mha_sched_msgout(SEND_ABORT); 2067 } 2068 } else { 2069 if (sc->sc_state == SPC_IDLE) 2070 mha_sched(sc); 2071 } 2072 } 2073 2074 void 2075 mha_timeout(arg) 2076 void *arg; 2077 { 2078 int s = splbio(); 2079 struct acb *acb = (struct acb *)arg; 2080 struct scsipi_xfer *xs = acb->xs; 2081 struct scsipi_link *sc_link = xs->sc_link; 2082 struct mha_softc *sc = sc_link->adapter_softc; 2083 2084 scsi_print_addr(sc_link); 2085 again: 2086 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2087 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2088 sc->sc_dev.dv_xname, 2089 acb, acb->flags, acb->dleft, acb->stat, 2090 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2091 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2092 ); 2093 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2094 panic("timeout, ouch!"); 2095 2096 if (acb->flags & ACB_ABORTED) { 2097 /* abort timed out */ 2098 printf(" AGAIN\n"); 2099 #if 0 2100 mha_init(sc, 1); /* XXX 1?*/ 2101 #endif 2102 } else { 2103 /* abort the operation that has timed out */ 2104 printf("\n"); 2105 xs->error = XS_TIMEOUT; 2106 mha_abort(sc, acb); 2107 } 2108 2109 splx(s); 2110 } 2111 2112 #if SPC_DEBUG 2114 /* 2115 * The following functions are mostly used for debugging purposes, either 2116 * directly called from the driver or from the kernel debugger. 2117 */ 2118 2119 void 2120 mha_show_scsi_cmd(acb) 2121 struct acb *acb; 2122 { 2123 u_char *b = (u_char *)&acb->cmd; 2124 struct scsipi_link *sc_link = acb->xs->sc_link; 2125 int i; 2126 2127 scsi_print_addr(sc_link); 2128 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2129 for (i = 0; i < acb->clen; i++) { 2130 if (i) 2131 printf(","); 2132 printf("%x", b[i]); 2133 } 2134 printf("\n"); 2135 } else 2136 printf("RESET\n"); 2137 } 2138 2139 void 2140 mha_print_acb(acb) 2141 struct acb *acb; 2142 { 2143 2144 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2145 printf(" dp=%x dleft=%d stat=%x\n", 2146 (long)acb->daddr, acb->dleft, acb->stat); 2147 mha_show_scsi_cmd(acb); 2148 } 2149 2150 void 2151 mha_print_active_acb() 2152 { 2153 struct acb *acb; 2154 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2155 2156 printf("ready list:\n"); 2157 for (acb = sc->ready_list.tqh_first; acb != NULL; 2158 acb = acb->chain.tqe_next) 2159 mha_print_acb(acb); 2160 printf("nexus:\n"); 2161 if (sc->sc_nexus != NULL) 2162 mha_print_acb(sc->sc_nexus); 2163 printf("nexus list:\n"); 2164 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2165 acb = acb->chain.tqe_next) 2166 mha_print_acb(acb); 2167 } 2168 2169 void 2170 mha_dump_driver(sc) 2171 struct mha_softc *sc; 2172 { 2173 struct spc_tinfo *ti; 2174 int i; 2175 2176 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2177 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2178 sc->sc_state, sc->sc_imess[0], 2179 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2180 for (i = 0; i < 7; i++) { 2181 ti = &sc->sc_tinfo[i]; 2182 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2183 i, ti->cmds, ti->dconns, ti->touts); 2184 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2185 } 2186 } 2187 #endif 2188
Indexes created Sat Oct 18 17:09:52 GMT 2025