mha.c revision 1.22.6.1
1 /* $NetBSD: mha.c,v 1.22.6.1 2001/11/12 21:17:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 190 #define Debugger() panic("should call debugger here (mha.c)") 191 #endif /* ! DDB */ 192 193 194 #if SPC_DEBUG 195 #define SPC_SHOWACBS 0x01 196 #define SPC_SHOWINTS 0x02 197 #define SPC_SHOWCMDS 0x04 198 #define SPC_SHOWMISC 0x08 199 #define SPC_SHOWTRAC 0x10 200 #define SPC_SHOWSTART 0x20 201 #define SPC_SHOWPHASE 0x40 202 #define SPC_SHOWDMA 0x80 203 #define SPC_SHOWCCMDS 0x100 204 #define SPC_SHOWMSGS 0x200 205 #define SPC_DOBREAK 0x400 206 207 int mha_debug = 208 #if 0 209 0x7FF; 210 #else 211 SPC_SHOWSTART|SPC_SHOWTRAC; 212 #endif 213 214 215 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 216 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 217 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 218 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 219 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 220 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 221 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 222 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 223 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 224 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 225 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 226 #else 227 #define SPC_ACBS(str) 228 #define SPC_MISC(str) 229 #define SPC_INTS(str) 230 #define SPC_TRACE(str) 231 #define SPC_CMDS(str) 232 #define SPC_START(str) 233 #define SPC_PHASE(str) 234 #define SPC_DMA(str) 235 #define SPC_MSGS(str) 236 #define SPC_BREAK() 237 #define SPC_ASSERT(x) 238 #endif 239 240 int mhamatch __P((struct device *, struct cfdata *, void *)); 241 void mhaattach __P((struct device *, struct device *, void *)); 242 void mhaselect __P((struct mha_softc *, 243 u_char, u_char, u_char *, u_char)); 244 void mha_scsi_reset __P((struct mha_softc *)); 245 void mha_reset __P((struct mha_softc *)); 246 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 247 void mha_sense __P((struct mha_softc *, struct acb *)); 248 void mha_msgin __P((struct mha_softc *)); 249 void mha_msgout __P((struct mha_softc *)); 250 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 252 int mha_dataout __P((struct mha_softc *, u_char *, int)); 253 int mha_datain __P((struct mha_softc *, u_char *, int)); 254 void mha_abort __P((struct mha_softc *, struct acb *)); 255 void mha_init __P((struct mha_softc *)); 256 void mha_scsi_request __P((struct scsipi_channel *, 257 scsipi_adapter_req_t, void *)); 258 void mha_poll __P((struct mha_softc *, struct acb *)); 259 void mha_sched __P((struct mha_softc *)); 260 void mha_done __P((struct mha_softc *, struct acb *)); 261 int mhaintr __P((void*)); 262 void mha_timeout __P((void *)); 263 void mha_minphys __P((struct buf *)); 264 void mha_dequeue __P((struct mha_softc *, struct acb *)); 265 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 266 #if SPC_DEBUG 267 void mha_print_acb __P((struct acb *)); 268 void mha_show_scsi_cmd __P((struct acb *)); 269 void mha_print_active_acb __P((void)); 270 void mha_dump_driver __P((struct mha_softc *)); 271 #endif 272 273 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 274 275 struct cfattach mha_ca = { 276 sizeof(struct mha_softc), mhamatch, mhaattach 277 }; 278 279 extern struct cfdriver mha_cd; 280 281 282 /* 284 * returns non-zero value if a controller is found. 285 */ 286 int 287 mhamatch(parent, cf, aux) 288 struct device *parent; 289 struct cfdata *cf; 290 void *aux; 291 { 292 struct intio_attach_args *ia = aux; 293 bus_space_tag_t iot = ia->ia_bst; 294 bus_space_handle_t ioh; 295 296 ia->ia_size=0x20; 297 if (ia->ia_addr != 0xea0000) 298 return 0; 299 300 if (intio_map_allocate_region(parent->dv_parent, ia, 301 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 302 return 0; 303 304 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 305 &ioh) < 0) 306 return 0; 307 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 308 return 0; 309 bus_space_unmap(iot, ioh, 0x20); 310 311 return 1; 312 } 313 314 /* 315 */ 316 317 struct mha_softc *tmpsc; 318 319 void 320 mhaattach(parent, self, aux) 321 struct device *parent, *self; 322 void *aux; 323 { 324 struct mha_softc *sc = (void *)self; 325 struct intio_attach_args *ia = aux; 326 327 tmpsc = sc; /* XXX */ 328 329 printf (": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 330 331 SPC_TRACE(("mhaattach ")); 332 sc->sc_state = SPC_INIT; 333 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 334 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 335 /* XXX: FAKE */ 336 sc->sc_dmat = ia->ia_dmat; 337 338 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 339 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 340 sc->sc_pcx = &sc->sc_pc[0x10]; 341 342 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 343 344 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 345 346 mha_init(sc); /* Init chip and driver */ 347 348 mha_scsi_reset(sc); /* XXX: some devices need this. */ 349 350 sc->sc_phase = BUSFREE_PHASE; 351 352 /* 353 * Fill in the adapter. 354 */ 355 sc->sc_adapter.adapt_dev = &sc->sc_dev; 356 sc->sc_adapter.adapt_nchannels = 1; 357 sc->sc_adapter.adapt_openings = 7; 358 sc->sc_adapter.adapt_max_periph = 1; 359 sc->sc_adapter.adapt_ioctl = NULL; 360 sc->sc_adapter.adapt_minphys = mha_minphys; 361 sc->sc_adapter.adapt_request = mha_scsi_request; 362 363 sc->sc_channel.chan_adapter = &sc->sc_adapter; 364 sc->sc_channel.chan_bustype = &scsi_bustype; 365 sc->sc_channel.chan_channel = 0; 366 sc->sc_channel.chan_ntargets = 8; 367 sc->sc_channel.chan_nluns = 8; 368 sc->sc_channel.chan_id = sc->sc_id; 369 370 sc->sc_spcinitialized = 0; 371 WAR = WA_INITWIN; 372 #if 1 373 CCR = 0x14; 374 OIR = sc->sc_id; 375 AMR = 0x00; 376 SMR = 0x00; 377 SRR = 0x00; 378 STR = 0x20; 379 RTR = 0x40; 380 ATR = 0x01; 381 PER = 0xc9; 382 #endif 383 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 384 #if 1 385 GLR = 0x00; 386 DMR = 0x30; 387 IMR = 0x00; 388 #endif 389 WAR = WA_MCSBUFWIN; 390 391 /* drop off */ 392 while (SSR & SS_IREQUEST) 393 { 394 unsigned a = ISCSR; 395 } 396 397 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 398 399 SPC_TRACE(("waiting for intr...")); 400 while (!(SSR & SS_IREQUEST)) 401 delay(10); 402 mhaintr (sc); 403 404 tmpsc = NULL; 405 406 config_found(self, &sc->sc_channel, scsiprint); 407 } 408 409 #if 0 410 void 411 mha_reset(sc) 412 struct mha_softc *sc; 413 { 414 u_short dummy; 415 printf("reset..."); 416 CMR = CMD_SOFT_RESET; 417 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 418 dummy = sc->sc_ps[-1]; 419 dummy = sc->sc_ps[-1]; 420 dummy = sc->sc_ps[-1]; 421 dummy = sc->sc_ps[-1]; 422 asm volatile ("nop"); 423 CMR = CMD_SOFT_RESET; 424 sc->sc_spcinitialized = 0; 425 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 426 while(!sc->sc_spcinitialized); 427 428 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 429 printf("done.\n"); 430 } 431 #endif 432 433 /* 434 * Pull the SCSI RST line for 500us. 435 */ 436 void 437 mha_scsi_reset(sc) /* FINISH? */ 438 struct mha_softc *sc; 439 { 440 441 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 442 while (!(SSR&SS_IREQUEST)) 443 delay(10); 444 } 445 446 /* 447 * Initialize mha SCSI driver. 448 */ 449 void 450 mha_init(sc) 451 struct mha_softc *sc; 452 { 453 struct acb *acb; 454 int r; 455 456 if (sc->sc_state == SPC_INIT) { 457 /* First time through; initialize. */ 458 TAILQ_INIT(&sc->ready_list); 459 TAILQ_INIT(&sc->nexus_list); 460 TAILQ_INIT(&sc->free_list); 461 sc->sc_nexus = NULL; 462 acb = sc->sc_acb; 463 bzero(acb, sizeof(sc->sc_acb)); 464 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 465 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 466 acb++; 467 } 468 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 469 470 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 471 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 472 BUS_DMA_NOWAIT); 473 if (r) 474 panic("mha_init: cannot allocate dma memory"); 475 if (sc->sc_ndmasegs != 1) 476 panic("mha_init: number of segment > 1??"); 477 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 478 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 479 if (r) 480 panic("mha_init: cannot map dma memory"); 481 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 482 MAXBSIZE, 0, BUS_DMA_NOWAIT, 483 &sc->sc_dmamap); 484 if (r) 485 panic("mha_init: cannot create dmamap structure"); 486 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 487 sc->sc_dmabuf, MAXBSIZE, NULL, 488 BUS_DMA_NOWAIT); 489 if (r) 490 panic("mha_init: cannot load dma buffer into dmamap"); 491 sc->sc_p = 0; 492 } else { 493 /* Cancel any active commands. */ 494 sc->sc_flags |= SPC_ABORTING; 495 sc->sc_state = SPC_IDLE; 496 if ((acb = sc->sc_nexus) != NULL) { 497 acb->xs->error = XS_DRIVER_STUFFUP; 498 mha_done(sc, acb); 499 } 500 while ((acb = sc->nexus_list.tqh_first) != NULL) { 501 acb->xs->error = XS_DRIVER_STUFFUP; 502 mha_done(sc, acb); 503 } 504 } 505 506 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 507 for (r = 0; r < 8; r++) { 508 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 509 510 ti->flags = 0; 511 #if SPC_USE_SYNCHRONOUS 512 ti->flags |= T_SYNCMODE; 513 ti->period = sc->sc_minsync; 514 ti->offset = SPC_SYNC_REQ_ACK_OFS; 515 #else 516 ti->period = ti->offset = 0; 517 #endif 518 ti->width = 0; 519 } 520 521 sc->sc_state = SPC_IDLE; 522 } 523 524 void 525 mha_free_acb(sc, acb, flags) 526 struct mha_softc *sc; 527 struct acb *acb; 528 int flags; 529 { 530 int s; 531 532 s = splbio(); 533 534 acb->flags = 0; 535 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 536 537 /* 538 * If there were none, wake anybody waiting for one to come free, 539 * starting with queued entries. 540 */ 541 if (acb->chain.tqe_next == 0) 542 wakeup(&sc->free_list); 543 544 splx(s); 545 } 546 547 548 /* 550 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 551 */ 552 553 /* 554 * Expected sequence: 555 * 1) Command inserted into ready list 556 * 2) Command selected for execution 557 * 3) Command won arbitration and has selected target device 558 * 4) Send message out (identify message, eventually also sync.negotiations) 559 * 5) Send command 560 * 5a) Receive disconnect message, disconnect. 561 * 5b) Reselected by target 562 * 5c) Receive identify message from target. 563 * 6) Send or receive data 564 * 7) Receive status 565 * 8) Receive message (command complete etc.) 566 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 567 * Repeat 2-8 (no disconnects please...) 568 */ 569 570 /* 571 * Start a selection. This is used by mha_sched() to select an idle target, 572 * and by mha_done() to immediately reselect a target to get sense information. 573 */ 574 void 575 mhaselect(sc, target, lun, cmd, clen) 576 struct mha_softc *sc; 577 u_char target, lun; 578 u_char *cmd; 579 u_char clen; 580 { 581 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 582 int i; 583 int s; 584 585 s = splbio(); /* XXX */ 586 587 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 588 589 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 590 /* Now the command into the FIFO */ 591 WAIT; 592 #if 1 593 SPC_MISC(("[cmd:")); 594 for (i = 0; i < clen; i++) 595 { 596 unsigned c = cmd[i]; 597 if (i == 1) 598 c |= lun << 5; 599 SPC_MISC((" %02x", c)); 600 sc->sc_pcx[i] = c; 601 } 602 SPC_MISC(("], target=%d\n", target)); 603 #else 604 bcopy(cmd, sc->sc_pcx, clen); 605 #endif 606 if (NSR & 0x80) 607 panic("scsistart: already selected..."); 608 sc->sc_phase = COMMAND_PHASE; 609 610 /* new state ASP_SELECTING */ 611 sc->sc_state = SPC_SELECTING; 612 613 SIR = target; 614 #if 0 615 CMR = CMD_SELECT; 616 #else 617 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 618 #endif 619 splx(s); 620 } 621 622 #if 0 623 int 624 mha_reselect(sc, message) 625 struct mha_softc *sc; 626 u_char message; 627 { 628 u_char selid, target, lun; 629 struct acb *acb; 630 struct scsipi_periph *periph; 631 struct spc_tinfo *ti; 632 633 /* 634 * The SCSI chip made a snapshot of the data bus while the reselection 635 * was being negotiated. This enables us to determine which target did 636 * the reselect. 637 */ 638 selid = sc->sc_selid & ~(1 << sc->sc_id); 639 if (selid & (selid - 1)) { 640 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 641 sc->sc_dev.dv_xname, selid); 642 SPC_BREAK(); 643 goto reset; 644 } 645 646 /* 647 * Search wait queue for disconnected cmd 648 * The list should be short, so I haven't bothered with 649 * any more sophisticated structures than a simple 650 * singly linked list. 651 */ 652 target = ffs(selid) - 1; 653 lun = message & 0x07; 654 for (acb = sc->nexus_list.tqh_first; acb != NULL; 655 acb = acb->chain.tqe_next) { 656 periph = acb->xs->xs_periph; 657 if (periph->periph_target == target && 658 periph->periph_lun == lun) 659 break; 660 } 661 if (acb == NULL) { 662 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 663 sc->sc_dev.dv_xname, target, lun); 664 SPC_BREAK(); 665 goto abort; 666 } 667 668 /* Make this nexus active again. */ 669 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 670 sc->sc_state = SPC_HASNEXUS; 671 sc->sc_nexus = acb; 672 ti = &sc->sc_tinfo[target]; 673 ti->lubusy |= (1 << lun); 674 mha_setsync(sc, ti); 675 676 if (acb->flags & ACB_RESET) 677 mha_sched_msgout(sc, SEND_DEV_RESET); 678 else if (acb->flags & ACB_ABORTED) 679 mha_sched_msgout(sc, SEND_ABORT); 680 681 /* Do an implicit RESTORE POINTERS. */ 682 sc->sc_dp = acb->daddr; 683 sc->sc_dleft = acb->dleft; 684 sc->sc_cp = (u_char *)&acb->cmd; 685 sc->sc_cleft = acb->clen; 686 687 return (0); 688 689 reset: 690 mha_sched_msgout(sc, SEND_DEV_RESET); 691 return (1); 692 693 abort: 694 mha_sched_msgout(sc, SEND_ABORT); 695 return (1); 696 } 697 #endif 698 /* 699 * Start a SCSI-command 700 * This function is called by the higher level SCSI-driver to queue/run 701 * SCSI-commands. 702 */ 703 void 704 mha_scsi_request(chan, req, arg) 705 struct scsipi_channel *chan; 706 scsipi_adapter_req_t req; 707 void *arg; 708 { 709 struct scsipi_xfer *xs; 710 struct scsipi_periph *periph; 711 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 712 struct acb *acb; 713 int s, flags; 714 715 switch (req) { 716 case ADAPTER_REQ_RUN_XFER: 717 xs = arg; 718 periph = xs->xs_periph; 719 720 SPC_TRACE(("[mha_scsi_cmd] ")); 721 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 722 periph->periph_target)); 723 724 flags = xs->xs_control; 725 726 /* Get a mha command block */ 727 s = splbio(); 728 acb = sc->free_list.tqh_first; 729 if (acb) { 730 TAILQ_REMOVE(&sc->free_list, acb, chain); 731 ACB_SETQ(acb, ACB_QNONE); 732 } 733 734 if (acb == NULL) { 735 xs->error = XS_RESOURCE_SHORTAGE; 736 scsipi_done(xs); 737 splx(s); 738 return; 739 } 740 splx(s); 741 742 /* Initialize acb */ 743 acb->xs = xs; 744 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 745 acb->clen = xs->cmdlen; 746 acb->daddr = xs->data; 747 acb->dleft = xs->datalen; 748 acb->stat = 0; 749 750 s = splbio(); 751 ACB_SETQ(acb, ACB_QREADY); 752 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 753 #if 1 754 callout_reset(&acb->xs->xs_callout, 755 ((u_int64_t)xs->timeout * (u_int64_t)hz) / 1000, 756 mha_timeout, acb); 757 #endif 758 759 /* 760 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 761 */ 762 if (sc->sc_state == SPC_IDLE) 763 mha_sched(sc); 764 765 splx(s); 766 767 if (flags & XS_CTL_POLL) { 768 /* Not allowed to use interrupts, use polling instead */ 769 mha_poll(sc, acb); 770 } 771 772 SPC_MISC(("SUCCESSFULLY_QUEUED")); 773 return; 774 775 case ADAPTER_REQ_GROW_RESOURCES: 776 /* XXX Not supported. */ 777 return; 778 779 case ADAPTER_REQ_SET_XFER_MODE: 780 /* XXX Not supported. */ 781 return; 782 } 783 } 784 785 /* 786 * Adjust transfer size in buffer structure 787 */ 788 void 789 mha_minphys(bp) 790 struct buf *bp; 791 { 792 793 SPC_TRACE(("mha_minphys ")); 794 minphys(bp); 795 } 796 797 /* 798 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 799 */ 800 void 801 mha_poll(sc, acb) 802 struct mha_softc *sc; 803 struct acb *acb; 804 { 805 struct scsipi_xfer *xs = acb->xs; 806 int count = xs->timeout * 100; 807 int s = splbio(); 808 809 SPC_TRACE(("[mha_poll] ")); 810 811 while (count) { 812 /* 813 * If we had interrupts enabled, would we 814 * have got an interrupt? 815 */ 816 if (SSR & SS_IREQUEST) 817 mhaintr(sc); 818 if ((xs->xs_status & XS_STS_DONE) != 0) 819 break; 820 DELAY(10); 821 #if 1 822 if (sc->sc_state == SPC_IDLE) { 823 SPC_TRACE(("[mha_poll: rescheduling] ")); 824 mha_sched(sc); 825 } 826 #endif 827 count--; 828 } 829 830 if (count == 0) { 831 SPC_MISC(("mha_poll: timeout")); 832 mha_timeout((caddr_t)acb); 833 } 834 splx(s); 835 scsipi_done(xs); 836 } 837 838 /* 840 * LOW LEVEL SCSI UTILITIES 841 */ 842 843 /* 844 * Set synchronous transfer offset and period. 845 */ 846 inline void 847 mha_setsync(sc, ti) 848 struct mha_softc *sc; 849 struct spc_tinfo *ti; 850 { 851 } 852 853 854 /* 856 * Schedule a SCSI operation. This has now been pulled out of the interrupt 857 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 858 * save us an unecessary interrupt just to get things going. Should only be 859 * called when state == SPC_IDLE and at bio pl. 860 */ 861 void 862 mha_sched(sc) 863 register struct mha_softc *sc; 864 { 865 struct scsipi_periph *periph; 866 struct acb *acb; 867 int t; 868 869 SPC_TRACE(("[mha_sched] ")); 870 if (sc->sc_state != SPC_IDLE) 871 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 872 873 if (sc->sc_flags & SPC_ABORTING) 874 return; 875 876 /* 877 * Find first acb in ready queue that is for a target/lunit 878 * combinations that is not busy. 879 */ 880 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 881 struct spc_tinfo *ti; 882 periph = acb->xs->xs_periph; 883 t = periph->periph_target; 884 ti = &sc->sc_tinfo[t]; 885 if (!(ti->lubusy & (1 << periph->periph_lun))) { 886 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 887 panic("mha: busy entry on ready list"); 888 TAILQ_REMOVE(&sc->ready_list, acb, chain); 889 ACB_SETQ(acb, ACB_QNONE); 890 sc->sc_nexus = acb; 891 sc->sc_flags = 0; 892 sc->sc_prevphase = INVALID_PHASE; 893 sc->sc_dp = acb->daddr; 894 sc->sc_dleft = acb->dleft; 895 ti->lubusy |= (1<<periph->periph_lun); 896 mhaselect(sc, t, periph->periph_lun, 897 (u_char *)&acb->cmd, acb->clen); 898 break; 899 } else { 900 SPC_MISC(("%d:%d busy\n", 901 periph->periph_target, 902 periph->periph_lun)); 903 } 904 } 905 } 906 907 /* 909 * POST PROCESSING OF SCSI_CMD (usually current) 910 */ 911 void 912 mha_done(sc, acb) 913 struct mha_softc *sc; 914 struct acb *acb; 915 { 916 struct scsipi_xfer *xs = acb->xs; 917 struct scsipi_periph *periph = xs->xs_periph; 918 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 919 920 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 921 922 #if 1 923 callout_stop(&acb->xs->xs_callout); 924 #endif 925 926 /* 927 * Now, if we've come here with no error code, i.e. we've kept the 928 * initial XS_NOERROR, and the status code signals that we should 929 * check sense, we'll need to set up a request sense cmd block and 930 * push the command back into the ready queue *before* any other 931 * commands for this target/lunit, else we lose the sense info. 932 * We don't support chk sense conditions for the request sense cmd. 933 */ 934 if (xs->error == XS_NOERROR) { 935 if ((acb->flags & ACB_ABORTED) != 0) { 936 xs->error = XS_TIMEOUT; 937 } else if (acb->flags & ACB_CHKSENSE) { 938 xs->error = XS_SENSE; 939 } else { 940 xs->status = acb->stat & ST_MASK; 941 switch (xs->status) { 942 case SCSI_CHECK: 943 xs->resid = acb->dleft; 944 /* FALLTHOUGH */ 945 case SCSI_BUSY: 946 xs->error = XS_BUSY; 947 break; 948 case SCSI_OK: 949 xs->resid = acb->dleft; 950 break; 951 default: 952 xs->error = XS_DRIVER_STUFFUP; 953 #if SPC_DEBUG 954 printf("%s: mha_done: bad stat 0x%x\n", 955 sc->sc_dev.dv_xname, acb->stat); 956 #endif 957 break; 958 } 959 } 960 } 961 962 #if SPC_DEBUG 963 if ((mha_debug & SPC_SHOWMISC) != 0) { 964 if (xs->resid != 0) 965 printf("resid=%d ", xs->resid); 966 if (xs->error == XS_SENSE) 967 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 968 else 969 printf("error=%d\n", xs->error); 970 } 971 #endif 972 973 /* 974 * Remove the ACB from whatever queue it's on. 975 */ 976 switch (acb->flags & ACB_QBITS) { 977 case ACB_QNONE: 978 if (acb != sc->sc_nexus) { 979 panic("%s: floating acb", sc->sc_dev.dv_xname); 980 } 981 sc->sc_nexus = NULL; 982 sc->sc_state = SPC_IDLE; 983 ti->lubusy &= ~(1<<periph->periph_lun); 984 mha_sched(sc); 985 break; 986 case ACB_QREADY: 987 TAILQ_REMOVE(&sc->ready_list, acb, chain); 988 break; 989 case ACB_QNEXUS: 990 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 991 ti->lubusy &= ~(1<<periph->periph_lun); 992 break; 993 case ACB_QFREE: 994 panic("%s: dequeue: busy acb on free list", 995 sc->sc_dev.dv_xname); 996 break; 997 default: 998 panic("%s: dequeue: unknown queue %d", 999 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1000 } 1001 1002 /* Put it on the free list, and clear flags. */ 1003 #if 0 1004 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1005 acb->flags = ACB_QFREE; 1006 #else 1007 mha_free_acb(sc, acb, xs->xs_control); 1008 #endif 1009 1010 ti->cmds++; 1011 scsipi_done(xs); 1012 } 1013 1014 void 1015 mha_dequeue(sc, acb) 1016 struct mha_softc *sc; 1017 struct acb *acb; 1018 { 1019 1020 if (acb->flags & ACB_QNEXUS) { 1021 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1022 } else { 1023 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1024 } 1025 } 1026 1027 /* 1029 * INTERRUPT/PROTOCOL ENGINE 1030 */ 1031 1032 /* 1033 * Schedule an outgoing message by prioritizing it, and asserting 1034 * attention on the bus. We can only do this when we are the initiator 1035 * else there will be an illegal command interrupt. 1036 */ 1037 #define mha_sched_msgout(m) \ 1038 do { \ 1039 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1040 CMR = CMD_SET_ATN; \ 1041 sc->sc_msgpriq |= (m); \ 1042 } while (0) 1043 1044 /* 1045 * Precondition: 1046 * The SCSI bus is already in the MSGI phase and there is a message byte 1047 * on the bus, along with an asserted REQ signal. 1048 */ 1049 void 1050 mha_msgin(sc) 1051 register struct mha_softc *sc; 1052 { 1053 register int v; 1054 int n; 1055 1056 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1057 1058 /* 1059 * Prepare for a new message. A message should (according 1060 * to the SCSI standard) be transmitted in one single 1061 * MESSAGE_IN_PHASE. If we have been in some other phase, 1062 * then this is a new message. 1063 */ 1064 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1065 sc->sc_flags &= ~SPC_DROP_MSGI; 1066 sc->sc_imlen = 0; 1067 } 1068 1069 WAIT; 1070 1071 v = MBR; /* modified byte */ 1072 v = sc->sc_pcx[0]; 1073 1074 sc->sc_imess[sc->sc_imlen] = v; 1075 1076 /* 1077 * If we're going to reject the message, don't bother storing 1078 * the incoming bytes. But still, we need to ACK them. 1079 */ 1080 1081 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1082 CMR = CMD_SET_ATN; 1083 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1084 printf("<dropping msg byte %x>", 1085 sc->sc_imess[sc->sc_imlen]); 1086 return; 1087 } 1088 1089 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1090 mha_sched_msgout(SEND_REJECT); 1091 sc->sc_flags |= SPC_DROP_MSGI; 1092 } else { 1093 sc->sc_imlen++; 1094 /* 1095 * This testing is suboptimal, but most 1096 * messages will be of the one byte variety, so 1097 * it should not effect performance 1098 * significantly. 1099 */ 1100 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1101 goto gotit; 1102 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1103 goto gotit; 1104 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1105 sc->sc_imlen == sc->sc_imess[1] + 2) 1106 goto gotit; 1107 } 1108 #if 0 1109 /* Ack what we have so far */ 1110 ESPCMD(sc, ESPCMD_MSGOK); 1111 #endif 1112 return; 1113 1114 gotit: 1115 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1116 /* 1117 * Now we should have a complete message (1 byte, 2 byte 1118 * and moderately long extended messages). We only handle 1119 * extended messages which total length is shorter than 1120 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1121 */ 1122 if (sc->sc_state == SPC_HASNEXUS) { 1123 struct acb *acb = sc->sc_nexus; 1124 struct spc_tinfo *ti = 1125 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1126 1127 switch (sc->sc_imess[0]) { 1128 case MSG_CMDCOMPLETE: 1129 SPC_MSGS(("cmdcomplete ")); 1130 if (sc->sc_dleft < 0) { 1131 struct scsipi_periph *periph = acb->xs->xs_periph; 1132 printf("mha: %d extra bytes from %d:%d\n", 1133 -sc->sc_dleft, 1134 periph->periph_target, 1135 periph->periph_lun); 1136 sc->sc_dleft = 0; 1137 } 1138 acb->xs->resid = acb->dleft = sc->sc_dleft; 1139 sc->sc_flags |= SPC_BUSFREE_OK; 1140 break; 1141 1142 case MSG_MESSAGE_REJECT: 1143 #if SPC_DEBUG 1144 if (mha_debug & SPC_SHOWMSGS) 1145 printf("%s: our msg rejected by target\n", 1146 sc->sc_dev.dv_xname); 1147 #endif 1148 #if 1 /* XXX - must remember last message */ 1149 scsipi_printaddr(acb->xs->xs_periph); 1150 printf("MSG_MESSAGE_REJECT>>"); 1151 #endif 1152 if (sc->sc_flags & SPC_SYNCHNEGO) { 1153 ti->period = ti->offset = 0; 1154 sc->sc_flags &= ~SPC_SYNCHNEGO; 1155 ti->flags &= ~T_NEGOTIATE; 1156 } 1157 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1158 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1159 mha_sched_msgout(SEND_ABORT); 1160 break; 1161 case MSG_NOOP: 1162 SPC_MSGS(("noop ")); 1163 break; 1164 case MSG_DISCONNECT: 1165 SPC_MSGS(("disconnect ")); 1166 ti->dconns++; 1167 sc->sc_flags |= SPC_DISCON; 1168 sc->sc_flags |= SPC_BUSFREE_OK; 1169 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1170 break; 1171 /*FALLTHROUGH*/ 1172 case MSG_SAVEDATAPOINTER: 1173 SPC_MSGS(("save datapointer ")); 1174 acb->dleft = sc->sc_dleft; 1175 acb->daddr = sc->sc_dp; 1176 break; 1177 case MSG_RESTOREPOINTERS: 1178 SPC_MSGS(("restore datapointer ")); 1179 if (!acb) { 1180 mha_sched_msgout(SEND_ABORT); 1181 printf("%s: no DATAPOINTERs to restore\n", 1182 sc->sc_dev.dv_xname); 1183 break; 1184 } 1185 sc->sc_dp = acb->daddr; 1186 sc->sc_dleft = acb->dleft; 1187 break; 1188 case MSG_PARITY_ERROR: 1189 printf("%s:target%d: MSG_PARITY_ERROR\n", 1190 sc->sc_dev.dv_xname, 1191 acb->xs->xs_periph->periph_target); 1192 break; 1193 case MSG_EXTENDED: 1194 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1195 switch (sc->sc_imess[2]) { 1196 case MSG_EXT_SDTR: 1197 SPC_MSGS(("SDTR period %d, offset %d ", 1198 sc->sc_imess[3], sc->sc_imess[4])); 1199 ti->period = sc->sc_imess[3]; 1200 ti->offset = sc->sc_imess[4]; 1201 if (sc->sc_minsync == 0) { 1202 /* We won't do synch */ 1203 ti->offset = 0; 1204 mha_sched_msgout(SEND_SDTR); 1205 } else if (ti->offset == 0) { 1206 printf("%s:%d: async\n", "mha", 1207 acb->xs->xs_periph->periph_target); 1208 ti->offset = 0; 1209 sc->sc_flags &= ~SPC_SYNCHNEGO; 1210 } else if (ti->period > 124) { 1211 printf("%s:%d: async\n", "mha", 1212 acb->xs->xs_periph->periph_target); 1213 ti->offset = 0; 1214 mha_sched_msgout(SEND_SDTR); 1215 } else { 1216 int r = 250/ti->period; 1217 int s = (100*250)/ti->period - 100*r; 1218 int p; 1219 #if 0 1220 p = mha_stp2cpb(sc, ti->period); 1221 ti->period = mha_cpb2stp(sc, p); 1222 #endif 1223 1224 #if SPC_DEBUG 1225 scsipi_printaddr(acb->xs->xs_periph); 1226 #endif 1227 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1228 /* Target initiated negotiation */ 1229 if (ti->flags & T_SYNCMODE) { 1230 ti->flags &= ~T_SYNCMODE; 1231 #if SPC_DEBUG 1232 printf("renegotiated "); 1233 #endif 1234 } 1235 TMR=TM_ASYNC; 1236 /* Clamp to our maxima */ 1237 if (ti->period < sc->sc_minsync) 1238 ti->period = sc->sc_minsync; 1239 if (ti->offset > 15) 1240 ti->offset = 15; 1241 mha_sched_msgout(SEND_SDTR); 1242 } else { 1243 /* we are sync */ 1244 sc->sc_flags &= ~SPC_SYNCHNEGO; 1245 TMR = TM_SYNC; 1246 ti->flags |= T_SYNCMODE; 1247 } 1248 #if SPC_DEBUG 1249 printf("max sync rate %d.%02dMb/s\n", 1250 r, s); 1251 #endif 1252 } 1253 ti->flags &= ~T_NEGOTIATE; 1254 break; 1255 default: /* Extended messages we don't handle */ 1256 CMR = CMD_SET_ATN; /* XXX? */ 1257 break; 1258 } 1259 break; 1260 default: 1261 SPC_MSGS(("ident ")); 1262 /* thanks for that ident... */ 1263 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1264 SPC_MISC(("unknown ")); 1265 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1266 CMR = CMD_SET_ATN; /* XXX? */ 1267 } 1268 break; 1269 } 1270 } else if (sc->sc_state == SPC_RESELECTED) { 1271 struct scsipi_periph *periph = NULL; 1272 struct acb *acb; 1273 struct spc_tinfo *ti; 1274 u_char lunit; 1275 1276 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1277 SPC_MISC(("searching ")); 1278 /* 1279 * Search wait queue for disconnected cmd 1280 * The list should be short, so I haven't bothered with 1281 * any more sophisticated structures than a simple 1282 * singly linked list. 1283 */ 1284 lunit = sc->sc_imess[0] & 0x07; 1285 for (acb = sc->nexus_list.tqh_first; acb; 1286 acb = acb->chain.tqe_next) { 1287 periph = acb->xs->xs_periph; 1288 if (periph->periph_lun == lunit && 1289 sc->sc_selid == (1<<periph->periph_target)) { 1290 TAILQ_REMOVE(&sc->nexus_list, acb, 1291 chain); 1292 ACB_SETQ(acb, ACB_QNONE); 1293 break; 1294 } 1295 } 1296 1297 if (!acb) { /* Invalid reselection! */ 1298 mha_sched_msgout(SEND_ABORT); 1299 printf("mha: invalid reselect (idbit=0x%2x)\n", 1300 sc->sc_selid); 1301 } else { /* Reestablish nexus */ 1302 /* 1303 * Setup driver data structures and 1304 * do an implicit RESTORE POINTERS 1305 */ 1306 ti = &sc->sc_tinfo[periph->periph_target]; 1307 sc->sc_nexus = acb; 1308 sc->sc_dp = acb->daddr; 1309 sc->sc_dleft = acb->dleft; 1310 sc->sc_tinfo[periph->periph_target].lubusy 1311 |= (1<<periph->periph_lun); 1312 if (ti->flags & T_SYNCMODE) { 1313 TMR = TM_SYNC; /* XXX */ 1314 } else { 1315 TMR = TM_ASYNC; 1316 } 1317 SPC_MISC(("... found acb")); 1318 sc->sc_state = SPC_HASNEXUS; 1319 } 1320 } else { 1321 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1322 sc->sc_dev.dv_xname, sc->sc_selid); 1323 mha_sched_msgout(SEND_DEV_RESET); 1324 } 1325 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1326 printf("%s: unexpected message in; will send DEV_RESET\n", 1327 sc->sc_dev.dv_xname); 1328 mha_sched_msgout(SEND_DEV_RESET); 1329 } 1330 1331 /* Ack last message byte */ 1332 #if 0 1333 ESPCMD(sc, ESPCMD_MSGOK); 1334 #endif 1335 1336 /* Done, reset message pointer. */ 1337 sc->sc_flags &= ~SPC_DROP_MSGI; 1338 sc->sc_imlen = 0; 1339 } 1340 1341 /* 1342 * Send the highest priority, scheduled message. 1343 */ 1344 void 1345 mha_msgout(sc) 1346 register struct mha_softc *sc; 1347 { 1348 struct spc_tinfo *ti; 1349 int n; 1350 1351 SPC_TRACE(("mha_msgout ")); 1352 1353 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1354 if (sc->sc_omp == sc->sc_omess) { 1355 /* 1356 * This is a retransmission. 1357 * 1358 * We get here if the target stayed in MESSAGE OUT 1359 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1360 * that all of the previously transmitted messages must 1361 * be sent again, in the same order. Therefore, we 1362 * requeue all the previously transmitted messages, and 1363 * start again from the top. Our simple priority 1364 * scheme keeps the messages in the right order. 1365 */ 1366 SPC_MISC(("retransmitting ")); 1367 sc->sc_msgpriq |= sc->sc_msgoutq; 1368 /* 1369 * Set ATN. If we're just sending a trivial 1-byte 1370 * message, we'll clear ATN later on anyway. 1371 */ 1372 CMR = CMD_SET_ATN; /* XXX? */ 1373 } else { 1374 /* This is a continuation of the previous message. */ 1375 n = sc->sc_omp - sc->sc_omess; 1376 goto nextbyte; 1377 } 1378 } 1379 1380 /* No messages transmitted so far. */ 1381 sc->sc_msgoutq = 0; 1382 sc->sc_lastmsg = 0; 1383 1384 nextmsg: 1385 /* Pick up highest priority message. */ 1386 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1387 sc->sc_msgpriq &= ~sc->sc_currmsg; 1388 sc->sc_msgoutq |= sc->sc_currmsg; 1389 1390 /* Build the outgoing message data. */ 1391 switch (sc->sc_currmsg) { 1392 case SEND_IDENTIFY: 1393 SPC_ASSERT(sc->sc_nexus != NULL); 1394 sc->sc_omess[0] = 1395 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1396 n = 1; 1397 break; 1398 1399 #if SPC_USE_SYNCHRONOUS 1400 case SEND_SDTR: 1401 SPC_ASSERT(sc->sc_nexus != NULL); 1402 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1403 sc->sc_omess[4] = MSG_EXTENDED; 1404 sc->sc_omess[3] = 3; 1405 sc->sc_omess[2] = MSG_EXT_SDTR; 1406 sc->sc_omess[1] = ti->period >> 2; 1407 sc->sc_omess[0] = ti->offset; 1408 n = 5; 1409 break; 1410 #endif 1411 1412 #if SPC_USE_WIDE 1413 case SEND_WDTR: 1414 SPC_ASSERT(sc->sc_nexus != NULL); 1415 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1416 sc->sc_omess[3] = MSG_EXTENDED; 1417 sc->sc_omess[2] = 2; 1418 sc->sc_omess[1] = MSG_EXT_WDTR; 1419 sc->sc_omess[0] = ti->width; 1420 n = 4; 1421 break; 1422 #endif 1423 1424 case SEND_DEV_RESET: 1425 sc->sc_flags |= SPC_ABORTING; 1426 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1427 n = 1; 1428 break; 1429 1430 case SEND_REJECT: 1431 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1432 n = 1; 1433 break; 1434 1435 case SEND_PARITY_ERROR: 1436 sc->sc_omess[0] = MSG_PARITY_ERROR; 1437 n = 1; 1438 break; 1439 1440 case SEND_INIT_DET_ERR: 1441 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1442 n = 1; 1443 break; 1444 1445 case SEND_ABORT: 1446 sc->sc_flags |= SPC_ABORTING; 1447 sc->sc_omess[0] = MSG_ABORT; 1448 n = 1; 1449 break; 1450 1451 default: 1452 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1453 sc->sc_dev.dv_xname); 1454 SPC_BREAK(); 1455 sc->sc_omess[0] = MSG_NOOP; 1456 n = 1; 1457 break; 1458 } 1459 sc->sc_omp = &sc->sc_omess[n]; 1460 1461 nextbyte: 1462 /* Send message bytes. */ 1463 /* send TRANSFER command. */ 1464 sc->sc_ps[3] = 1; 1465 sc->sc_ps[4] = n >> 8; 1466 sc->sc_pc[10] = n; 1467 sc->sc_ps[-1] = 0x000F; /* burst */ 1468 asm volatile ("nop"); 1469 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1470 for (;;) { 1471 if ((SSR & SS_BUSY) != 0) 1472 break; 1473 if (SSR & SS_IREQUEST) 1474 goto out; 1475 } 1476 for (;;) { 1477 #if 0 1478 for (;;) { 1479 if ((PSNS & PSNS_REQ) != 0) 1480 break; 1481 /* Wait for REQINIT. XXX Need timeout. */ 1482 } 1483 #endif 1484 if (SSR & SS_IREQUEST) { 1485 /* 1486 * Target left MESSAGE OUT, possibly to reject 1487 * our message. 1488 * 1489 * If this is the last message being sent, then we 1490 * deassert ATN, since either the target is going to 1491 * ignore this message, or it's going to ask for a 1492 * retransmission via MESSAGE PARITY ERROR (in which 1493 * case we reassert ATN anyway). 1494 */ 1495 #if 0 1496 if (sc->sc_msgpriq == 0) 1497 CMR = CMD_RESET_ATN; 1498 #endif 1499 goto out; 1500 } 1501 1502 #if 0 1503 /* Clear ATN before last byte if this is the last message. */ 1504 if (n == 1 && sc->sc_msgpriq == 0) 1505 CMR = CMD_RESET_ATN; 1506 #endif 1507 1508 while ((SSR & SS_DREG_FULL) != 0) 1509 ; 1510 /* Send message byte. */ 1511 sc->sc_pc[0] = *--sc->sc_omp; 1512 --n; 1513 /* Keep track of the last message we've sent any bytes of. */ 1514 sc->sc_lastmsg = sc->sc_currmsg; 1515 1516 if (n == 0) 1517 break; 1518 } 1519 1520 /* We get here only if the entire message has been transmitted. */ 1521 if (sc->sc_msgpriq != 0) { 1522 /* There are more outgoing messages. */ 1523 goto nextmsg; 1524 } 1525 1526 /* 1527 * The last message has been transmitted. We need to remember the last 1528 * message transmitted (in case the target switches to MESSAGE IN phase 1529 * and sends a MESSAGE REJECT), and the list of messages transmitted 1530 * this time around (in case the target stays in MESSAGE OUT phase to 1531 * request a retransmit). 1532 */ 1533 1534 out: 1535 /* Disable REQ/ACK protocol. */ 1536 } 1537 1538 1539 /*************************************************************** 1541 * 1542 * datain/dataout 1543 * 1544 */ 1545 1546 int 1547 mha_datain_pio(sc, p, n) 1548 register struct mha_softc *sc; 1549 u_char *p; 1550 int n; 1551 { 1552 u_short d; 1553 int a; 1554 int total_n = n; 1555 1556 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1557 1558 WAIT; 1559 sc->sc_ps[3] = 1; 1560 sc->sc_ps[4] = n >> 8; 1561 sc->sc_pc[10] = n; 1562 /* $BHa$7$-%=%U%HE>Aw(B */ 1563 CMR = CMD_RECEIVE_TO_MPU; 1564 for (;;) { 1565 a = SSR; 1566 if (a & 0x04) { 1567 d = sc->sc_ps[0]; 1568 *p++ = d >> 8; 1569 if (--n > 0) { 1570 *p++ = d; 1571 --n; 1572 } 1573 a = SSR; 1574 } 1575 if (a & 0x40) 1576 continue; 1577 if (a & 0x80) 1578 break; 1579 } 1580 SPC_TRACE(("...%d resd]", n)); 1581 return total_n - n; 1582 } 1583 1584 int 1585 mha_dataout_pio(sc, p, n) 1586 register struct mha_softc *sc; 1587 u_char *p; 1588 int n; 1589 { 1590 u_short d; 1591 int a; 1592 int total_n = n; 1593 1594 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1595 1596 WAIT; 1597 sc->sc_ps[3] = 1; 1598 sc->sc_ps[4] = n >> 8; 1599 sc->sc_pc[10] = n; 1600 /* $BHa$7$-%=%U%HE>Aw(B */ 1601 CMR = CMD_SEND_FROM_MPU; 1602 for (;;) { 1603 a = SSR; 1604 if (a & 0x04) { 1605 d = *p++ << 8; 1606 if (--n > 0) { 1607 d |= *p++; 1608 --n; 1609 } 1610 sc->sc_ps[0] = d; 1611 a = SSR; 1612 } 1613 if (a & 0x40) 1614 continue; 1615 if (a & 0x80) 1616 break; 1617 } 1618 SPC_TRACE(("...%d resd]", n)); 1619 return total_n - n; 1620 } 1621 1622 static int 1623 mha_dataio_dma(dw, cw, sc, p, n) 1624 int dw; /* DMA word */ 1625 int cw; /* CMR word */ 1626 register struct mha_softc *sc; 1627 u_char *p; 1628 int n; 1629 { 1630 char *paddr, *vaddr; 1631 1632 if (n > MAXBSIZE) 1633 panic("transfer size exceeds MAXBSIZE"); 1634 if (sc->sc_dmasize > 0) 1635 panic("DMA request while another DMA transfer is in pregress"); 1636 1637 if (cw == CMD_SEND_FROM_DMA) { 1638 memcpy(sc->sc_dmabuf, p, n); 1639 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1640 } else { 1641 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1642 } 1643 sc->sc_p = p; 1644 sc->sc_dmasize = n; 1645 1646 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1647 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1648 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1649 dw &= ~(1 << 3); 1650 #endif 1651 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1652 #if 0 1653 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1654 PCIA(); /* XXX */ 1655 #endif 1656 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1657 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1658 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1659 WAIT; 1660 sc->sc_ps[3] = 1; 1661 sc->sc_ps[4] = n >> 8; 1662 sc->sc_pc[10] = n; 1663 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1664 3 ... short bus cycle 1665 2 ... MAXIMUM XFER. 1666 1 ... BURST XFER. 1667 0 ... R/W */ 1668 sc->sc_ps[-1] = dw; /* burst */ 1669 asm volatile ("nop"); 1670 CMR = cw; /* receive to DMA */ 1671 return n; 1672 } 1673 int 1674 mha_dataout(sc, p, n) 1675 register struct mha_softc *sc; 1676 u_char *p; 1677 int n; 1678 { 1679 register struct acb *acb = sc->sc_nexus; 1680 1681 if (n == 0) 1682 return n; 1683 1684 if (n & 1) 1685 return mha_dataout_pio(sc, p, n); 1686 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1687 } 1688 1689 int 1691 mha_datain(sc, p, n) 1692 register struct mha_softc *sc; 1693 u_char *p; 1694 int n; 1695 { 1696 int ts; 1697 register struct acb *acb = sc->sc_nexus; 1698 char *paddr, *vaddr; 1699 1700 if (n == 0) 1701 return n; 1702 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1703 return mha_datain_pio(sc, p, n); 1704 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1705 } 1706 1707 1709 /* 1710 * Catch an interrupt from the adaptor 1711 */ 1712 /* 1713 * This is the workhorse routine of the driver. 1714 * Deficiencies (for now): 1715 * 1) always uses programmed I/O 1716 */ 1717 int 1718 mhaintr(arg) 1719 void *arg; 1720 { 1721 struct mha_softc *sc = arg; 1722 #if 0 1723 u_char ints; 1724 #endif 1725 struct acb *acb; 1726 struct scsipi_periph *periph; 1727 struct spc_tinfo *ti; 1728 u_char ph; 1729 u_short r; 1730 int n; 1731 1732 #if 1 /* XXX called during attach? */ 1733 if (tmpsc != NULL) { 1734 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1735 sc = tmpsc; 1736 } else { 1737 #endif 1738 1739 #if 1 /* XXX */ 1740 } 1741 #endif 1742 1743 #if 0 1744 /* 1745 * $B3d$j9~$_6X;_$K$9$k(B 1746 */ 1747 SCTL &= ~SCTL_INTR_ENAB; 1748 #endif 1749 1750 SPC_TRACE(("[mhaintr]")); 1751 1752 loop: 1753 /* 1754 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1755 */ 1756 /* 1757 * First check for abnormal conditions, such as reset. 1758 */ 1759 #if 0 1760 #if 1 /* XXX? */ 1761 while (((ints = SSR) & SS_IREQUEST) == 0) 1762 delay(1); 1763 SPC_MISC(("ints = 0x%x ", ints)); 1764 #else /* usually? */ 1765 ints = SSR; 1766 #endif 1767 #endif 1768 while (SSR & SS_IREQUEST) { 1769 acb = sc->sc_nexus; 1770 r = ISCSR; 1771 SPC_MISC(("[r=0x%x]", r)); 1772 switch (r >> 8) { 1773 default: 1774 printf("[addr=%x\n" 1775 "result=0x%x\n" 1776 "cmd=0x%x\n" 1777 "ph=0x%x(ought to be %d)]\n", 1778 &ISCSR, 1779 r, 1780 acb->xs->cmd->opcode, 1781 SCR, sc->sc_phase); 1782 panic("unexpected result."); 1783 case 0x82: /* selection timeout */ 1784 SPC_MISC(("selection timeout ")); 1785 sc->sc_phase = BUSFREE_PHASE; 1786 SPC_ASSERT(sc->sc_nexus != NULL); 1787 acb = sc->sc_nexus; 1788 delay(250); 1789 acb->xs->error = XS_SELTIMEOUT; 1790 mha_done(sc, acb); 1791 continue; /* XXX ??? msaitoh */ 1792 case 0x60: /* command completed */ 1793 sc->sc_spcinitialized++; 1794 if (sc->sc_phase == BUSFREE_PHASE) 1795 continue; 1796 ph = SCR; 1797 if (ph & PSNS_ACK) { 1798 int s; 1799 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1800 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1801 ph & PHASE_MASK, sc->sc_phase)); 1802 #if 0 1803 /* switch (sc->sc_phase) {*/ 1804 #else 1805 switch (ph & PHASE_MASK) { 1806 #endif 1807 case STATUS_PHASE: 1808 if (sc->sc_state != SPC_HASNEXUS) 1809 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1810 sc->sc_state); 1811 SPC_ASSERT(sc->sc_nexus != NULL); 1812 acb = sc->sc_nexus; 1813 WAIT; 1814 s = MBR; 1815 SPC_ASSERT(s == 1); 1816 acb->stat = sc->sc_pcx[0]; /* XXX */ 1817 SPC_MISC(("stat=0x%02x ", acb->stat)); 1818 sc->sc_prevphase = STATUS_PHASE; 1819 break; 1820 case MESSAGE_IN_PHASE: 1821 mha_msgin(sc); 1822 sc->sc_prevphase = MESSAGE_IN_PHASE; 1823 /* thru */ 1824 case DATA_IN_PHASE: 1825 if (sc->sc_dmasize == 0) 1826 break; 1827 bus_dmamap_sync(sc->sc_dmat, 1828 sc->sc_dmamap, 1829 0, sc->sc_dmasize, 1830 BUS_DMASYNC_POSTREAD); 1831 memcpy(sc->sc_p, sc->sc_dmabuf, 1832 sc->sc_dmasize); 1833 sc->sc_dmasize = 0; 1834 break; 1835 case DATA_OUT_PHASE: 1836 if (sc->sc_dmasize == 0) 1837 break; 1838 bus_dmamap_sync(sc->sc_dmat, 1839 sc->sc_dmamap, 1840 0, sc->sc_dmasize, 1841 BUS_DMASYNC_POSTWRITE); 1842 sc->sc_dmasize = 0; 1843 break; 1844 } 1845 WAIT; 1846 CMR = CMD_RESET_ACK; /* reset ack */ 1847 /*mha_done(sc, acb); XXX */ 1848 continue; 1849 } else if (NSR & 0x80) { /* nexus */ 1850 #if 1 1851 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1852 sc->sc_state = SPC_HASNEXUS; 1853 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1854 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1855 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1856 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1857 WAIT; 1858 if (SSR & SS_IREQUEST) 1859 continue; 1860 switch (sc->sc_phase) { 1861 default: 1862 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1863 case MESSAGE_IN_PHASE: 1864 /* $B2?$b$7$J$$(B */ 1865 continue; 1866 case STATUS_PHASE: 1867 sc->sc_phase = MESSAGE_IN_PHASE; 1868 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1869 continue; 1870 case DATA_IN_PHASE: 1871 sc->sc_prevphase = DATA_IN_PHASE; 1872 if (sc->sc_dleft == 0) { 1873 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1874 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1875 sc->sc_phase = STATUS_PHASE; 1876 CMR = CMD_RECEIVE_STS; /* receive sts */ 1877 continue; 1878 } 1879 n = mha_datain(sc, sc->sc_dp, 1880 sc->sc_dleft); 1881 sc->sc_dp += n; 1882 sc->sc_dleft -= n; 1883 continue; 1884 case DATA_OUT_PHASE: 1885 sc->sc_prevphase = DATA_OUT_PHASE; 1886 if (sc->sc_dleft == 0) { 1887 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1888 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1889 sc->sc_phase = STATUS_PHASE; 1890 CMR = CMD_RECEIVE_STS; /* receive sts */ 1891 continue; 1892 } 1893 /* data phase $B$NB3$-$r$d$m$&(B */ 1894 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1895 sc->sc_dp += n; 1896 sc->sc_dleft -= n; 1897 continue; 1898 case COMMAND_PHASE: 1899 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1900 if (acb->dleft) { 1901 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1902 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1903 sc->sc_phase = DATA_IN_PHASE; 1904 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1905 sc->sc_dp += n; 1906 sc->sc_dleft -= n; 1907 } 1908 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1909 sc->sc_phase = DATA_OUT_PHASE; 1910 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1911 sc->sc_dp += n; 1912 sc->sc_dleft -= n; 1913 } 1914 continue; 1915 } 1916 else { 1917 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1918 WAIT; 1919 sc->sc_phase = STATUS_PHASE; 1920 CMR = CMD_RECEIVE_STS; /* receive sts */ 1921 continue; 1922 } 1923 } 1924 #endif 1925 } 1926 continue; 1927 case 0x31: /* disconnected in xfer progress. */ 1928 SPC_MISC(("[0x31]")); 1929 case 0x70: /* disconnected. */ 1930 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1931 sc->sc_phase = BUSFREE_PHASE; 1932 sc->sc_state = SPC_IDLE; 1933 #if 1 1934 acb = sc->sc_nexus; 1935 SPC_ASSERT(sc->sc_nexus != NULL); 1936 acb->xs->error = XS_NOERROR; 1937 mha_done(sc, acb); 1938 #else 1939 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1940 mha_sched(sc); 1941 #endif 1942 continue; 1943 case 0x32: /* phase error in xfer progress. */ 1944 SPC_MISC(("[0x32]")); 1945 #if 0 1946 case 0x65: /* invalid command. 1947 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1948 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1949 #if 1 1950 SPC_MISC(("[0x%04x]", r)); 1951 #endif 1952 #endif 1953 case 0x54: /* initial-phase error. */ 1954 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1955 NSR, 1956 SCR, sc->sc_phase)); 1957 /* thru */ 1958 case 0x71: /* assert req */ 1959 WAIT; 1960 if (SSR & 0x40) { 1961 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1962 SSR, r, NSR, SCR); 1963 WAIT; 1964 } 1965 ph = SCR; 1966 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1967 sc->sc_state = SPC_HASNEXUS; 1968 } 1969 if (ph & 0x80) { 1970 switch (ph & PHASE_MASK) { 1971 default: 1972 printf("phase = %x\n", ph); 1973 panic("assert req: the phase I don't know!"); 1974 case DATA_IN_PHASE: 1975 sc->sc_prevphase = DATA_IN_PHASE; 1976 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1977 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1978 sc->sc_dp += n; 1979 sc->sc_dleft -= n; 1980 SPC_MISC(("done\n")); 1981 continue; 1982 case DATA_OUT_PHASE: 1983 sc->sc_prevphase = DATA_OUT_PHASE; 1984 SPC_MISC(("DATAOUT\n")); 1985 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1986 sc->sc_dp += n; 1987 sc->sc_dleft -= n; 1988 continue; 1989 case STATUS_PHASE: 1990 sc->sc_phase = STATUS_PHASE; 1991 SPC_MISC(("[RECV_STS]")); 1992 WAIT; 1993 CMR = CMD_RECEIVE_STS; /* receive sts */ 1994 continue; 1995 case MESSAGE_IN_PHASE: 1996 sc->sc_phase = MESSAGE_IN_PHASE; 1997 WAIT; 1998 CMR = CMD_RECEIVE_MSG; 1999 continue; 2000 } 2001 } 2002 continue; 2003 } 2004 } 2005 } 2006 2007 void 2008 mha_abort(sc, acb) 2009 struct mha_softc *sc; 2010 struct acb *acb; 2011 { 2012 acb->flags |= ACB_ABORTED; 2013 2014 if (acb == sc->sc_nexus) { 2015 /* 2016 * If we're still selecting, the message will be scheduled 2017 * after selection is complete. 2018 */ 2019 if (sc->sc_state == SPC_HASNEXUS) { 2020 sc->sc_flags |= SPC_ABORTING; 2021 mha_sched_msgout(SEND_ABORT); 2022 } 2023 } else { 2024 if (sc->sc_state == SPC_IDLE) 2025 mha_sched(sc); 2026 } 2027 } 2028 2029 void 2030 mha_timeout(arg) 2031 void *arg; 2032 { 2033 int s = splbio(); 2034 struct acb *acb = (struct acb *)arg; 2035 struct scsipi_xfer *xs = acb->xs; 2036 struct scsipi_periph *periph = xs->xs_periph; 2037 struct mha_softc *sc = 2038 (void*)periph->periph_channel->chan_adapter->adapt_dev; 2039 2040 scsipi_printaddr(periph); 2041 again: 2042 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2043 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2044 sc->sc_dev.dv_xname, 2045 acb, acb->flags, acb->dleft, acb->stat, 2046 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2047 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2048 ); 2049 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2050 panic("timeout, ouch!"); 2051 2052 if (acb->flags & ACB_ABORTED) { 2053 /* abort timed out */ 2054 printf(" AGAIN\n"); 2055 #if 0 2056 mha_init(sc, 1); /* XXX 1?*/ 2057 #endif 2058 } else { 2059 /* abort the operation that has timed out */ 2060 printf("\n"); 2061 xs->error = XS_TIMEOUT; 2062 mha_abort(sc, acb); 2063 } 2064 2065 splx(s); 2066 } 2067 2068 #if SPC_DEBUG 2070 /* 2071 * The following functions are mostly used for debugging purposes, either 2072 * directly called from the driver or from the kernel debugger. 2073 */ 2074 2075 void 2076 mha_show_scsi_cmd(acb) 2077 struct acb *acb; 2078 { 2079 u_char *b = (u_char *)&acb->cmd; 2080 struct scsipi_periph *periph = acb->xs->xs_periph; 2081 int i; 2082 2083 scsipi_printaddr(periph); 2084 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2085 for (i = 0; i < acb->clen; i++) { 2086 if (i) 2087 printf(","); 2088 printf("%x", b[i]); 2089 } 2090 printf("\n"); 2091 } else 2092 printf("RESET\n"); 2093 } 2094 2095 void 2096 mha_print_acb(acb) 2097 struct acb *acb; 2098 { 2099 2100 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2101 printf(" dp=%x dleft=%d stat=%x\n", 2102 (long)acb->daddr, acb->dleft, acb->stat); 2103 mha_show_scsi_cmd(acb); 2104 } 2105 2106 void 2107 mha_print_active_acb() 2108 { 2109 struct acb *acb; 2110 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2111 2112 printf("ready list:\n"); 2113 for (acb = sc->ready_list.tqh_first; acb != NULL; 2114 acb = acb->chain.tqe_next) 2115 mha_print_acb(acb); 2116 printf("nexus:\n"); 2117 if (sc->sc_nexus != NULL) 2118 mha_print_acb(sc->sc_nexus); 2119 printf("nexus list:\n"); 2120 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2121 acb = acb->chain.tqe_next) 2122 mha_print_acb(acb); 2123 } 2124 2125 void 2126 mha_dump_driver(sc) 2127 struct mha_softc *sc; 2128 { 2129 struct spc_tinfo *ti; 2130 int i; 2131 2132 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2133 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2134 sc->sc_state, sc->sc_imess[0], 2135 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2136 for (i = 0; i < 7; i++) { 2137 ti = &sc->sc_tinfo[i]; 2138 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2139 i, ti->cmds, ti->dconns, ti->touts); 2140 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2141 } 2142 } 2143 #endif 2144
Indexes created Sat Oct 18 17:09:52 GMT 2025