mha.c revision 1.33
1 /* $NetBSD: mha.c,v 1.33 2003/05/03 18:11:07 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 190 #define Debugger() panic("should call debugger here (mha.c)") 191 #endif /* ! DDB */ 192 193 194 #if SPC_DEBUG 195 #define SPC_SHOWACBS 0x01 196 #define SPC_SHOWINTS 0x02 197 #define SPC_SHOWCMDS 0x04 198 #define SPC_SHOWMISC 0x08 199 #define SPC_SHOWTRAC 0x10 200 #define SPC_SHOWSTART 0x20 201 #define SPC_SHOWPHASE 0x40 202 #define SPC_SHOWDMA 0x80 203 #define SPC_SHOWCCMDS 0x100 204 #define SPC_SHOWMSGS 0x200 205 #define SPC_DOBREAK 0x400 206 207 int mha_debug = 208 #if 0 209 0x7FF; 210 #else 211 SPC_SHOWSTART|SPC_SHOWTRAC; 212 #endif 213 214 215 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 216 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 217 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 218 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 219 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 220 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 221 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 222 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 223 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 224 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 225 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 226 #else 227 #define SPC_ACBS(str) 228 #define SPC_MISC(str) 229 #define SPC_INTS(str) 230 #define SPC_TRACE(str) 231 #define SPC_CMDS(str) 232 #define SPC_START(str) 233 #define SPC_PHASE(str) 234 #define SPC_DMA(str) 235 #define SPC_MSGS(str) 236 #define SPC_BREAK() 237 #define SPC_ASSERT(x) 238 #endif 239 240 int mhamatch __P((struct device *, struct cfdata *, void *)); 241 void mhaattach __P((struct device *, struct device *, void *)); 242 void mhaselect __P((struct mha_softc *, 243 u_char, u_char, u_char *, u_char)); 244 void mha_scsi_reset __P((struct mha_softc *)); 245 void mha_reset __P((struct mha_softc *)); 246 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 247 void mha_sense __P((struct mha_softc *, struct acb *)); 248 void mha_msgin __P((struct mha_softc *)); 249 void mha_msgout __P((struct mha_softc *)); 250 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 252 int mha_dataout __P((struct mha_softc *, u_char *, int)); 253 int mha_datain __P((struct mha_softc *, u_char *, int)); 254 void mha_abort __P((struct mha_softc *, struct acb *)); 255 void mha_init __P((struct mha_softc *)); 256 void mha_scsi_request __P((struct scsipi_channel *, 257 scsipi_adapter_req_t, void *)); 258 void mha_poll __P((struct mha_softc *, struct acb *)); 259 void mha_sched __P((struct mha_softc *)); 260 void mha_done __P((struct mha_softc *, struct acb *)); 261 int mhaintr __P((void*)); 262 void mha_timeout __P((void *)); 263 void mha_minphys __P((struct buf *)); 264 void mha_dequeue __P((struct mha_softc *, struct acb *)); 265 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 266 #if SPC_DEBUG 267 void mha_print_acb __P((struct acb *)); 268 void mha_show_scsi_cmd __P((struct acb *)); 269 void mha_print_active_acb __P((void)); 270 void mha_dump_driver __P((struct mha_softc *)); 271 #endif 272 273 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 274 275 CFATTACH_DECL(mha, sizeof(struct mha_softc), 276 mhamatch, mhaattach, NULL, NULL); 277 278 extern struct cfdriver mha_cd; 279 280 281 /* 283 * returns non-zero value if a controller is found. 284 */ 285 int 286 mhamatch(parent, cf, aux) 287 struct device *parent; 288 struct cfdata *cf; 289 void *aux; 290 { 291 struct intio_attach_args *ia = aux; 292 bus_space_tag_t iot = ia->ia_bst; 293 bus_space_handle_t ioh; 294 295 ia->ia_size=0x20; 296 if (ia->ia_addr != 0xea0000) 297 return 0; 298 299 if (intio_map_allocate_region(parent->dv_parent, ia, 300 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 301 return 0; 302 303 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 304 &ioh) < 0) 305 return 0; 306 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 307 return 0; 308 bus_space_unmap(iot, ioh, 0x20); 309 310 return 1; 311 } 312 313 /* 314 */ 315 316 struct mha_softc *tmpsc; 317 318 void 319 mhaattach(parent, self, aux) 320 struct device *parent, *self; 321 void *aux; 322 { 323 struct mha_softc *sc = (void *)self; 324 struct intio_attach_args *ia = aux; 325 326 tmpsc = sc; /* XXX */ 327 328 printf (": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 329 330 SPC_TRACE(("mhaattach ")); 331 sc->sc_state = SPC_INIT; 332 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 333 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 334 /* XXX: FAKE */ 335 sc->sc_dmat = ia->ia_dmat; 336 337 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 338 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 339 sc->sc_pcx = &sc->sc_pc[0x10]; 340 341 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 342 343 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 344 345 mha_init(sc); /* Init chip and driver */ 346 347 mha_scsi_reset(sc); /* XXX: some devices need this. */ 348 349 sc->sc_phase = BUSFREE_PHASE; 350 351 /* 352 * Fill in the adapter. 353 */ 354 sc->sc_adapter.adapt_dev = &sc->sc_dev; 355 sc->sc_adapter.adapt_nchannels = 1; 356 sc->sc_adapter.adapt_openings = 7; 357 sc->sc_adapter.adapt_max_periph = 1; 358 sc->sc_adapter.adapt_ioctl = NULL; 359 sc->sc_adapter.adapt_minphys = mha_minphys; 360 sc->sc_adapter.adapt_request = mha_scsi_request; 361 362 sc->sc_channel.chan_adapter = &sc->sc_adapter; 363 sc->sc_channel.chan_bustype = &scsi_bustype; 364 sc->sc_channel.chan_channel = 0; 365 sc->sc_channel.chan_ntargets = 8; 366 sc->sc_channel.chan_nluns = 8; 367 sc->sc_channel.chan_id = sc->sc_id; 368 369 sc->sc_spcinitialized = 0; 370 WAR = WA_INITWIN; 371 #if 1 372 CCR = 0x14; 373 OIR = sc->sc_id; 374 AMR = 0x00; 375 SMR = 0x00; 376 SRR = 0x00; 377 STR = 0x20; 378 RTR = 0x40; 379 ATR = 0x01; 380 PER = 0xc9; 381 #endif 382 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 383 #if 1 384 GLR = 0x00; 385 DMR = 0x30; 386 IMR = 0x00; 387 #endif 388 WAR = WA_MCSBUFWIN; 389 390 /* drop off */ 391 while (SSR & SS_IREQUEST) 392 { 393 (void) ISCSR; 394 } 395 396 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 397 398 SPC_TRACE(("waiting for intr...")); 399 while (!(SSR & SS_IREQUEST)) 400 delay(10); 401 mhaintr (sc); 402 403 tmpsc = NULL; 404 405 config_found(self, &sc->sc_channel, scsiprint); 406 } 407 408 #if 0 409 void 410 mha_reset(sc) 411 struct mha_softc *sc; 412 { 413 u_short dummy; 414 printf("reset..."); 415 CMR = CMD_SOFT_RESET; 416 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 417 dummy = sc->sc_ps[-1]; 418 dummy = sc->sc_ps[-1]; 419 dummy = sc->sc_ps[-1]; 420 dummy = sc->sc_ps[-1]; 421 asm volatile ("nop"); 422 CMR = CMD_SOFT_RESET; 423 sc->sc_spcinitialized = 0; 424 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 425 while(!sc->sc_spcinitialized); 426 427 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 428 printf("done.\n"); 429 } 430 #endif 431 432 /* 433 * Pull the SCSI RST line for 500us. 434 */ 435 void 436 mha_scsi_reset(sc) /* FINISH? */ 437 struct mha_softc *sc; 438 { 439 440 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 441 while (!(SSR&SS_IREQUEST)) 442 delay(10); 443 } 444 445 /* 446 * Initialize mha SCSI driver. 447 */ 448 void 449 mha_init(sc) 450 struct mha_softc *sc; 451 { 452 struct acb *acb; 453 int r; 454 455 if (sc->sc_state == SPC_INIT) { 456 /* First time through; initialize. */ 457 TAILQ_INIT(&sc->ready_list); 458 TAILQ_INIT(&sc->nexus_list); 459 TAILQ_INIT(&sc->free_list); 460 sc->sc_nexus = NULL; 461 acb = sc->sc_acb; 462 memset(acb, 0, sizeof(sc->sc_acb)); 463 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 464 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 465 acb++; 466 } 467 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 468 469 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 470 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 471 BUS_DMA_NOWAIT); 472 if (r) 473 panic("mha_init: cannot allocate DMA memory"); 474 if (sc->sc_ndmasegs != 1) 475 panic("mha_init: number of segment > 1??"); 476 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 477 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 478 if (r) 479 panic("mha_init: cannot map DMA memory"); 480 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 481 MAXBSIZE, 0, BUS_DMA_NOWAIT, 482 &sc->sc_dmamap); 483 if (r) 484 panic("mha_init: cannot create dmamap structure"); 485 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 486 sc->sc_dmabuf, MAXBSIZE, NULL, 487 BUS_DMA_NOWAIT); 488 if (r) 489 panic("mha_init: cannot load DMA buffer into dmamap"); 490 sc->sc_p = 0; 491 } else { 492 /* Cancel any active commands. */ 493 sc->sc_flags |= SPC_ABORTING; 494 sc->sc_state = SPC_IDLE; 495 if ((acb = sc->sc_nexus) != NULL) { 496 acb->xs->error = XS_DRIVER_STUFFUP; 497 mha_done(sc, acb); 498 } 499 while ((acb = sc->nexus_list.tqh_first) != NULL) { 500 acb->xs->error = XS_DRIVER_STUFFUP; 501 mha_done(sc, acb); 502 } 503 } 504 505 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 506 for (r = 0; r < 8; r++) { 507 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 508 509 ti->flags = 0; 510 #if SPC_USE_SYNCHRONOUS 511 ti->flags |= T_SYNCMODE; 512 ti->period = sc->sc_minsync; 513 ti->offset = SPC_SYNC_REQ_ACK_OFS; 514 #else 515 ti->period = ti->offset = 0; 516 #endif 517 ti->width = 0; 518 } 519 520 sc->sc_state = SPC_IDLE; 521 } 522 523 void 524 mha_free_acb(sc, acb, flags) 525 struct mha_softc *sc; 526 struct acb *acb; 527 int flags; 528 { 529 int s; 530 531 s = splbio(); 532 533 acb->flags = 0; 534 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 535 536 /* 537 * If there were none, wake anybody waiting for one to come free, 538 * starting with queued entries. 539 */ 540 if (acb->chain.tqe_next == 0) 541 wakeup(&sc->free_list); 542 543 splx(s); 544 } 545 546 547 /* 549 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 550 */ 551 552 /* 553 * Expected sequence: 554 * 1) Command inserted into ready list 555 * 2) Command selected for execution 556 * 3) Command won arbitration and has selected target device 557 * 4) Send message out (identify message, eventually also sync.negotiations) 558 * 5) Send command 559 * 5a) Receive disconnect message, disconnect. 560 * 5b) Reselected by target 561 * 5c) Receive identify message from target. 562 * 6) Send or receive data 563 * 7) Receive status 564 * 8) Receive message (command complete etc.) 565 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 566 * Repeat 2-8 (no disconnects please...) 567 */ 568 569 /* 570 * Start a selection. This is used by mha_sched() to select an idle target, 571 * and by mha_done() to immediately reselect a target to get sense information. 572 */ 573 void 574 mhaselect(sc, target, lun, cmd, clen) 575 struct mha_softc *sc; 576 u_char target, lun; 577 u_char *cmd; 578 u_char clen; 579 { 580 int i; 581 int s; 582 583 s = splbio(); /* XXX */ 584 585 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 586 587 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 588 /* Now the command into the FIFO */ 589 WAIT; 590 #if 1 591 SPC_MISC(("[cmd:")); 592 for (i = 0; i < clen; i++) 593 { 594 unsigned c = cmd[i]; 595 if (i == 1) 596 c |= lun << 5; 597 SPC_MISC((" %02x", c)); 598 sc->sc_pcx[i] = c; 599 } 600 SPC_MISC(("], target=%d\n", target)); 601 #else 602 memcpy(sc->sc_pcx, cmd, clen); 603 #endif 604 if (NSR & 0x80) 605 panic("scsistart: already selected..."); 606 sc->sc_phase = COMMAND_PHASE; 607 608 /* new state ASP_SELECTING */ 609 sc->sc_state = SPC_SELECTING; 610 611 SIR = target; 612 #if 0 613 CMR = CMD_SELECT; 614 #else 615 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 616 #endif 617 splx(s); 618 } 619 620 #if 0 621 int 622 mha_reselect(sc, message) 623 struct mha_softc *sc; 624 u_char message; 625 { 626 u_char selid, target, lun; 627 struct acb *acb; 628 struct scsipi_periph *periph; 629 struct spc_tinfo *ti; 630 631 /* 632 * The SCSI chip made a snapshot of the data bus while the reselection 633 * was being negotiated. This enables us to determine which target did 634 * the reselect. 635 */ 636 selid = sc->sc_selid & ~(1 << sc->sc_id); 637 if (selid & (selid - 1)) { 638 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 639 sc->sc_dev.dv_xname, selid); 640 SPC_BREAK(); 641 goto reset; 642 } 643 644 /* 645 * Search wait queue for disconnected cmd 646 * The list should be short, so I haven't bothered with 647 * any more sophisticated structures than a simple 648 * singly linked list. 649 */ 650 target = ffs(selid) - 1; 651 lun = message & 0x07; 652 for (acb = sc->nexus_list.tqh_first; acb != NULL; 653 acb = acb->chain.tqe_next) { 654 periph = acb->xs->xs_periph; 655 if (periph->periph_target == target && 656 periph->periph_lun == lun) 657 break; 658 } 659 if (acb == NULL) { 660 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 661 sc->sc_dev.dv_xname, target, lun); 662 SPC_BREAK(); 663 goto abort; 664 } 665 666 /* Make this nexus active again. */ 667 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 668 sc->sc_state = SPC_HASNEXUS; 669 sc->sc_nexus = acb; 670 ti = &sc->sc_tinfo[target]; 671 ti->lubusy |= (1 << lun); 672 mha_setsync(sc, ti); 673 674 if (acb->flags & ACB_RESET) 675 mha_sched_msgout(sc, SEND_DEV_RESET); 676 else if (acb->flags & ACB_ABORTED) 677 mha_sched_msgout(sc, SEND_ABORT); 678 679 /* Do an implicit RESTORE POINTERS. */ 680 sc->sc_dp = acb->daddr; 681 sc->sc_dleft = acb->dleft; 682 sc->sc_cp = (u_char *)&acb->cmd; 683 sc->sc_cleft = acb->clen; 684 685 return (0); 686 687 reset: 688 mha_sched_msgout(sc, SEND_DEV_RESET); 689 return (1); 690 691 abort: 692 mha_sched_msgout(sc, SEND_ABORT); 693 return (1); 694 } 695 #endif 696 /* 697 * Start a SCSI-command 698 * This function is called by the higher level SCSI-driver to queue/run 699 * SCSI-commands. 700 */ 701 void 702 mha_scsi_request(chan, req, arg) 703 struct scsipi_channel *chan; 704 scsipi_adapter_req_t req; 705 void *arg; 706 { 707 struct scsipi_xfer *xs; 708 struct scsipi_periph *periph; 709 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 710 struct acb *acb; 711 int s, flags; 712 713 switch (req) { 714 case ADAPTER_REQ_RUN_XFER: 715 xs = arg; 716 periph = xs->xs_periph; 717 718 SPC_TRACE(("[mha_scsi_cmd] ")); 719 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 720 periph->periph_target)); 721 722 flags = xs->xs_control; 723 724 /* Get a mha command block */ 725 s = splbio(); 726 acb = sc->free_list.tqh_first; 727 if (acb) { 728 TAILQ_REMOVE(&sc->free_list, acb, chain); 729 ACB_SETQ(acb, ACB_QNONE); 730 } 731 732 if (acb == NULL) { 733 xs->error = XS_RESOURCE_SHORTAGE; 734 scsipi_done(xs); 735 splx(s); 736 return; 737 } 738 splx(s); 739 740 /* Initialize acb */ 741 acb->xs = xs; 742 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 743 acb->clen = xs->cmdlen; 744 acb->daddr = xs->data; 745 acb->dleft = xs->datalen; 746 acb->stat = 0; 747 748 s = splbio(); 749 ACB_SETQ(acb, ACB_QREADY); 750 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 751 #if 1 752 callout_reset(&acb->xs->xs_callout, 753 mstohz(xs->timeout), mha_timeout, acb); 754 #endif 755 756 /* 757 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 758 */ 759 if (sc->sc_state == SPC_IDLE) 760 mha_sched(sc); 761 762 splx(s); 763 764 if (flags & XS_CTL_POLL) { 765 /* Not allowed to use interrupts, use polling instead */ 766 mha_poll(sc, acb); 767 } 768 769 SPC_MISC(("SUCCESSFULLY_QUEUED")); 770 return; 771 772 case ADAPTER_REQ_GROW_RESOURCES: 773 /* XXX Not supported. */ 774 return; 775 776 case ADAPTER_REQ_SET_XFER_MODE: 777 /* XXX Not supported. */ 778 return; 779 } 780 } 781 782 /* 783 * Adjust transfer size in buffer structure 784 */ 785 void 786 mha_minphys(bp) 787 struct buf *bp; 788 { 789 790 SPC_TRACE(("mha_minphys ")); 791 minphys(bp); 792 } 793 794 /* 795 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 796 */ 797 void 798 mha_poll(sc, acb) 799 struct mha_softc *sc; 800 struct acb *acb; 801 { 802 struct scsipi_xfer *xs = acb->xs; 803 int count = xs->timeout * 100; 804 int s = splbio(); 805 806 SPC_TRACE(("[mha_poll] ")); 807 808 while (count) { 809 /* 810 * If we had interrupts enabled, would we 811 * have got an interrupt? 812 */ 813 if (SSR & SS_IREQUEST) 814 mhaintr(sc); 815 if ((xs->xs_status & XS_STS_DONE) != 0) 816 break; 817 DELAY(10); 818 #if 1 819 if (sc->sc_state == SPC_IDLE) { 820 SPC_TRACE(("[mha_poll: rescheduling] ")); 821 mha_sched(sc); 822 } 823 #endif 824 count--; 825 } 826 827 if (count == 0) { 828 SPC_MISC(("mha_poll: timeout")); 829 mha_timeout((caddr_t)acb); 830 } 831 splx(s); 832 scsipi_done(xs); 833 } 834 835 /* 837 * LOW LEVEL SCSI UTILITIES 838 */ 839 840 /* 841 * Set synchronous transfer offset and period. 842 */ 843 inline void 844 mha_setsync(sc, ti) 845 struct mha_softc *sc; 846 struct spc_tinfo *ti; 847 { 848 } 849 850 851 /* 853 * Schedule a SCSI operation. This has now been pulled out of the interrupt 854 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 855 * save us an unecessary interrupt just to get things going. Should only be 856 * called when state == SPC_IDLE and at bio pl. 857 */ 858 void 859 mha_sched(sc) 860 register struct mha_softc *sc; 861 { 862 struct scsipi_periph *periph; 863 struct acb *acb; 864 int t; 865 866 SPC_TRACE(("[mha_sched] ")); 867 if (sc->sc_state != SPC_IDLE) 868 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 869 870 if (sc->sc_flags & SPC_ABORTING) 871 return; 872 873 /* 874 * Find first acb in ready queue that is for a target/lunit 875 * combinations that is not busy. 876 */ 877 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 878 struct spc_tinfo *ti; 879 periph = acb->xs->xs_periph; 880 t = periph->periph_target; 881 ti = &sc->sc_tinfo[t]; 882 if (!(ti->lubusy & (1 << periph->periph_lun))) { 883 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 884 panic("mha: busy entry on ready list"); 885 TAILQ_REMOVE(&sc->ready_list, acb, chain); 886 ACB_SETQ(acb, ACB_QNONE); 887 sc->sc_nexus = acb; 888 sc->sc_flags = 0; 889 sc->sc_prevphase = INVALID_PHASE; 890 sc->sc_dp = acb->daddr; 891 sc->sc_dleft = acb->dleft; 892 ti->lubusy |= (1<<periph->periph_lun); 893 mhaselect(sc, t, periph->periph_lun, 894 (u_char *)&acb->cmd, acb->clen); 895 break; 896 } else { 897 SPC_MISC(("%d:%d busy\n", 898 periph->periph_target, 899 periph->periph_lun)); 900 } 901 } 902 } 903 904 /* 906 * POST PROCESSING OF SCSI_CMD (usually current) 907 */ 908 void 909 mha_done(sc, acb) 910 struct mha_softc *sc; 911 struct acb *acb; 912 { 913 struct scsipi_xfer *xs = acb->xs; 914 struct scsipi_periph *periph = xs->xs_periph; 915 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 916 917 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 918 919 #if 1 920 callout_stop(&acb->xs->xs_callout); 921 #endif 922 923 /* 924 * Now, if we've come here with no error code, i.e. we've kept the 925 * initial XS_NOERROR, and the status code signals that we should 926 * check sense, we'll need to set up a request sense cmd block and 927 * push the command back into the ready queue *before* any other 928 * commands for this target/lunit, else we lose the sense info. 929 * We don't support chk sense conditions for the request sense cmd. 930 */ 931 if (xs->error == XS_NOERROR) { 932 if ((acb->flags & ACB_ABORTED) != 0) { 933 xs->error = XS_TIMEOUT; 934 } else if (acb->flags & ACB_CHKSENSE) { 935 xs->error = XS_SENSE; 936 } else { 937 xs->status = acb->stat & ST_MASK; 938 switch (xs->status) { 939 case SCSI_CHECK: 940 xs->resid = acb->dleft; 941 /* FALLTHOUGH */ 942 case SCSI_BUSY: 943 xs->error = XS_BUSY; 944 break; 945 case SCSI_OK: 946 xs->resid = acb->dleft; 947 break; 948 default: 949 xs->error = XS_DRIVER_STUFFUP; 950 #if SPC_DEBUG 951 printf("%s: mha_done: bad stat 0x%x\n", 952 sc->sc_dev.dv_xname, acb->stat); 953 #endif 954 break; 955 } 956 } 957 } 958 959 #if SPC_DEBUG 960 if ((mha_debug & SPC_SHOWMISC) != 0) { 961 if (xs->resid != 0) 962 printf("resid=%d ", xs->resid); 963 if (xs->error == XS_SENSE) 964 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 965 else 966 printf("error=%d\n", xs->error); 967 } 968 #endif 969 970 /* 971 * Remove the ACB from whatever queue it's on. 972 */ 973 switch (acb->flags & ACB_QBITS) { 974 case ACB_QNONE: 975 if (acb != sc->sc_nexus) { 976 panic("%s: floating acb", sc->sc_dev.dv_xname); 977 } 978 sc->sc_nexus = NULL; 979 sc->sc_state = SPC_IDLE; 980 ti->lubusy &= ~(1<<periph->periph_lun); 981 mha_sched(sc); 982 break; 983 case ACB_QREADY: 984 TAILQ_REMOVE(&sc->ready_list, acb, chain); 985 break; 986 case ACB_QNEXUS: 987 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 988 ti->lubusy &= ~(1<<periph->periph_lun); 989 break; 990 case ACB_QFREE: 991 panic("%s: dequeue: busy acb on free list", 992 sc->sc_dev.dv_xname); 993 break; 994 default: 995 panic("%s: dequeue: unknown queue %d", 996 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 997 } 998 999 /* Put it on the free list, and clear flags. */ 1000 #if 0 1001 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1002 acb->flags = ACB_QFREE; 1003 #else 1004 mha_free_acb(sc, acb, xs->xs_control); 1005 #endif 1006 1007 ti->cmds++; 1008 scsipi_done(xs); 1009 } 1010 1011 void 1012 mha_dequeue(sc, acb) 1013 struct mha_softc *sc; 1014 struct acb *acb; 1015 { 1016 1017 if (acb->flags & ACB_QNEXUS) { 1018 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1019 } else { 1020 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1021 } 1022 } 1023 1024 /* 1026 * INTERRUPT/PROTOCOL ENGINE 1027 */ 1028 1029 /* 1030 * Schedule an outgoing message by prioritizing it, and asserting 1031 * attention on the bus. We can only do this when we are the initiator 1032 * else there will be an illegal command interrupt. 1033 */ 1034 #define mha_sched_msgout(m) \ 1035 do { \ 1036 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1037 CMR = CMD_SET_ATN; \ 1038 sc->sc_msgpriq |= (m); \ 1039 } while (0) 1040 1041 /* 1042 * Precondition: 1043 * The SCSI bus is already in the MSGI phase and there is a message byte 1044 * on the bus, along with an asserted REQ signal. 1045 */ 1046 void 1047 mha_msgin(sc) 1048 register struct mha_softc *sc; 1049 { 1050 register int v; 1051 1052 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1053 1054 /* 1055 * Prepare for a new message. A message should (according 1056 * to the SCSI standard) be transmitted in one single 1057 * MESSAGE_IN_PHASE. If we have been in some other phase, 1058 * then this is a new message. 1059 */ 1060 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1061 sc->sc_flags &= ~SPC_DROP_MSGI; 1062 sc->sc_imlen = 0; 1063 } 1064 1065 WAIT; 1066 1067 v = MBR; /* modified byte */ 1068 v = sc->sc_pcx[0]; 1069 1070 sc->sc_imess[sc->sc_imlen] = v; 1071 1072 /* 1073 * If we're going to reject the message, don't bother storing 1074 * the incoming bytes. But still, we need to ACK them. 1075 */ 1076 1077 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1078 CMR = CMD_SET_ATN; 1079 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1080 printf("<dropping msg byte %x>", 1081 sc->sc_imess[sc->sc_imlen]); 1082 return; 1083 } 1084 1085 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1086 mha_sched_msgout(SEND_REJECT); 1087 sc->sc_flags |= SPC_DROP_MSGI; 1088 } else { 1089 sc->sc_imlen++; 1090 /* 1091 * This testing is suboptimal, but most 1092 * messages will be of the one byte variety, so 1093 * it should not effect performance 1094 * significantly. 1095 */ 1096 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1097 goto gotit; 1098 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1099 goto gotit; 1100 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1101 sc->sc_imlen == sc->sc_imess[1] + 2) 1102 goto gotit; 1103 } 1104 #if 0 1105 /* Ack what we have so far */ 1106 ESPCMD(sc, ESPCMD_MSGOK); 1107 #endif 1108 return; 1109 1110 gotit: 1111 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1112 /* 1113 * Now we should have a complete message (1 byte, 2 byte 1114 * and moderately long extended messages). We only handle 1115 * extended messages which total length is shorter than 1116 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1117 */ 1118 if (sc->sc_state == SPC_HASNEXUS) { 1119 struct acb *acb = sc->sc_nexus; 1120 struct spc_tinfo *ti = 1121 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1122 1123 switch (sc->sc_imess[0]) { 1124 case MSG_CMDCOMPLETE: 1125 SPC_MSGS(("cmdcomplete ")); 1126 if (sc->sc_dleft < 0) { 1127 struct scsipi_periph *periph = acb->xs->xs_periph; 1128 printf("mha: %d extra bytes from %d:%d\n", 1129 -sc->sc_dleft, 1130 periph->periph_target, 1131 periph->periph_lun); 1132 sc->sc_dleft = 0; 1133 } 1134 acb->xs->resid = acb->dleft = sc->sc_dleft; 1135 sc->sc_flags |= SPC_BUSFREE_OK; 1136 break; 1137 1138 case MSG_MESSAGE_REJECT: 1139 #if SPC_DEBUG 1140 if (mha_debug & SPC_SHOWMSGS) 1141 printf("%s: our msg rejected by target\n", 1142 sc->sc_dev.dv_xname); 1143 #endif 1144 #if 1 /* XXX - must remember last message */ 1145 scsipi_printaddr(acb->xs->xs_periph); 1146 printf("MSG_MESSAGE_REJECT>>"); 1147 #endif 1148 if (sc->sc_flags & SPC_SYNCHNEGO) { 1149 ti->period = ti->offset = 0; 1150 sc->sc_flags &= ~SPC_SYNCHNEGO; 1151 ti->flags &= ~T_NEGOTIATE; 1152 } 1153 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1154 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1155 mha_sched_msgout(SEND_ABORT); 1156 break; 1157 case MSG_NOOP: 1158 SPC_MSGS(("noop ")); 1159 break; 1160 case MSG_DISCONNECT: 1161 SPC_MSGS(("disconnect ")); 1162 ti->dconns++; 1163 sc->sc_flags |= SPC_DISCON; 1164 sc->sc_flags |= SPC_BUSFREE_OK; 1165 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1166 break; 1167 /*FALLTHROUGH*/ 1168 case MSG_SAVEDATAPOINTER: 1169 SPC_MSGS(("save datapointer ")); 1170 acb->dleft = sc->sc_dleft; 1171 acb->daddr = sc->sc_dp; 1172 break; 1173 case MSG_RESTOREPOINTERS: 1174 SPC_MSGS(("restore datapointer ")); 1175 if (!acb) { 1176 mha_sched_msgout(SEND_ABORT); 1177 printf("%s: no DATAPOINTERs to restore\n", 1178 sc->sc_dev.dv_xname); 1179 break; 1180 } 1181 sc->sc_dp = acb->daddr; 1182 sc->sc_dleft = acb->dleft; 1183 break; 1184 case MSG_PARITY_ERROR: 1185 printf("%s:target%d: MSG_PARITY_ERROR\n", 1186 sc->sc_dev.dv_xname, 1187 acb->xs->xs_periph->periph_target); 1188 break; 1189 case MSG_EXTENDED: 1190 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1191 switch (sc->sc_imess[2]) { 1192 case MSG_EXT_SDTR: 1193 SPC_MSGS(("SDTR period %d, offset %d ", 1194 sc->sc_imess[3], sc->sc_imess[4])); 1195 ti->period = sc->sc_imess[3]; 1196 ti->offset = sc->sc_imess[4]; 1197 if (sc->sc_minsync == 0) { 1198 /* We won't do synch */ 1199 ti->offset = 0; 1200 mha_sched_msgout(SEND_SDTR); 1201 } else if (ti->offset == 0) { 1202 printf("%s:%d: async\n", "mha", 1203 acb->xs->xs_periph->periph_target); 1204 ti->offset = 0; 1205 sc->sc_flags &= ~SPC_SYNCHNEGO; 1206 } else if (ti->period > 124) { 1207 printf("%s:%d: async\n", "mha", 1208 acb->xs->xs_periph->periph_target); 1209 ti->offset = 0; 1210 mha_sched_msgout(SEND_SDTR); 1211 } else { 1212 #if 0 1213 int p; 1214 p = mha_stp2cpb(sc, ti->period); 1215 ti->period = mha_cpb2stp(sc, p); 1216 #endif 1217 1218 #if SPC_DEBUG 1219 scsipi_printaddr(acb->xs->xs_periph); 1220 #endif 1221 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1222 /* Target initiated negotiation */ 1223 if (ti->flags & T_SYNCMODE) { 1224 ti->flags &= ~T_SYNCMODE; 1225 #if SPC_DEBUG 1226 printf("renegotiated "); 1227 #endif 1228 } 1229 TMR=TM_ASYNC; 1230 /* Clamp to our maxima */ 1231 if (ti->period < sc->sc_minsync) 1232 ti->period = sc->sc_minsync; 1233 if (ti->offset > 15) 1234 ti->offset = 15; 1235 mha_sched_msgout(SEND_SDTR); 1236 } else { 1237 /* we are sync */ 1238 sc->sc_flags &= ~SPC_SYNCHNEGO; 1239 TMR = TM_SYNC; 1240 ti->flags |= T_SYNCMODE; 1241 } 1242 } 1243 ti->flags &= ~T_NEGOTIATE; 1244 break; 1245 default: /* Extended messages we don't handle */ 1246 CMR = CMD_SET_ATN; /* XXX? */ 1247 break; 1248 } 1249 break; 1250 default: 1251 SPC_MSGS(("ident ")); 1252 /* thanks for that ident... */ 1253 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1254 SPC_MISC(("unknown ")); 1255 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1256 CMR = CMD_SET_ATN; /* XXX? */ 1257 } 1258 break; 1259 } 1260 } else if (sc->sc_state == SPC_RESELECTED) { 1261 struct scsipi_periph *periph = NULL; 1262 struct acb *acb; 1263 struct spc_tinfo *ti; 1264 u_char lunit; 1265 1266 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1267 SPC_MISC(("searching ")); 1268 /* 1269 * Search wait queue for disconnected cmd 1270 * The list should be short, so I haven't bothered with 1271 * any more sophisticated structures than a simple 1272 * singly linked list. 1273 */ 1274 lunit = sc->sc_imess[0] & 0x07; 1275 for (acb = sc->nexus_list.tqh_first; acb; 1276 acb = acb->chain.tqe_next) { 1277 periph = acb->xs->xs_periph; 1278 if (periph->periph_lun == lunit && 1279 sc->sc_selid == (1<<periph->periph_target)) { 1280 TAILQ_REMOVE(&sc->nexus_list, acb, 1281 chain); 1282 ACB_SETQ(acb, ACB_QNONE); 1283 break; 1284 } 1285 } 1286 1287 if (!acb) { /* Invalid reselection! */ 1288 mha_sched_msgout(SEND_ABORT); 1289 printf("mha: invalid reselect (idbit=0x%2x)\n", 1290 sc->sc_selid); 1291 } else { /* Reestablish nexus */ 1292 /* 1293 * Setup driver data structures and 1294 * do an implicit RESTORE POINTERS 1295 */ 1296 ti = &sc->sc_tinfo[periph->periph_target]; 1297 sc->sc_nexus = acb; 1298 sc->sc_dp = acb->daddr; 1299 sc->sc_dleft = acb->dleft; 1300 sc->sc_tinfo[periph->periph_target].lubusy 1301 |= (1<<periph->periph_lun); 1302 if (ti->flags & T_SYNCMODE) { 1303 TMR = TM_SYNC; /* XXX */ 1304 } else { 1305 TMR = TM_ASYNC; 1306 } 1307 SPC_MISC(("... found acb")); 1308 sc->sc_state = SPC_HASNEXUS; 1309 } 1310 } else { 1311 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1312 sc->sc_dev.dv_xname, sc->sc_selid); 1313 mha_sched_msgout(SEND_DEV_RESET); 1314 } 1315 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1316 printf("%s: unexpected message in; will send DEV_RESET\n", 1317 sc->sc_dev.dv_xname); 1318 mha_sched_msgout(SEND_DEV_RESET); 1319 } 1320 1321 /* Ack last message byte */ 1322 #if 0 1323 ESPCMD(sc, ESPCMD_MSGOK); 1324 #endif 1325 1326 /* Done, reset message pointer. */ 1327 sc->sc_flags &= ~SPC_DROP_MSGI; 1328 sc->sc_imlen = 0; 1329 } 1330 1331 /* 1332 * Send the highest priority, scheduled message. 1333 */ 1334 void 1335 mha_msgout(sc) 1336 register struct mha_softc *sc; 1337 { 1338 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE) 1339 struct spc_tinfo *ti; 1340 #endif 1341 int n; 1342 1343 SPC_TRACE(("mha_msgout ")); 1344 1345 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1346 if (sc->sc_omp == sc->sc_omess) { 1347 /* 1348 * This is a retransmission. 1349 * 1350 * We get here if the target stayed in MESSAGE OUT 1351 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1352 * that all of the previously transmitted messages must 1353 * be sent again, in the same order. Therefore, we 1354 * requeue all the previously transmitted messages, and 1355 * start again from the top. Our simple priority 1356 * scheme keeps the messages in the right order. 1357 */ 1358 SPC_MISC(("retransmitting ")); 1359 sc->sc_msgpriq |= sc->sc_msgoutq; 1360 /* 1361 * Set ATN. If we're just sending a trivial 1-byte 1362 * message, we'll clear ATN later on anyway. 1363 */ 1364 CMR = CMD_SET_ATN; /* XXX? */ 1365 } else { 1366 /* This is a continuation of the previous message. */ 1367 n = sc->sc_omp - sc->sc_omess; 1368 goto nextbyte; 1369 } 1370 } 1371 1372 /* No messages transmitted so far. */ 1373 sc->sc_msgoutq = 0; 1374 sc->sc_lastmsg = 0; 1375 1376 nextmsg: 1377 /* Pick up highest priority message. */ 1378 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1379 sc->sc_msgpriq &= ~sc->sc_currmsg; 1380 sc->sc_msgoutq |= sc->sc_currmsg; 1381 1382 /* Build the outgoing message data. */ 1383 switch (sc->sc_currmsg) { 1384 case SEND_IDENTIFY: 1385 SPC_ASSERT(sc->sc_nexus != NULL); 1386 sc->sc_omess[0] = 1387 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1388 n = 1; 1389 break; 1390 1391 #if SPC_USE_SYNCHRONOUS 1392 case SEND_SDTR: 1393 SPC_ASSERT(sc->sc_nexus != NULL); 1394 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1395 sc->sc_omess[4] = MSG_EXTENDED; 1396 sc->sc_omess[3] = 3; 1397 sc->sc_omess[2] = MSG_EXT_SDTR; 1398 sc->sc_omess[1] = ti->period >> 2; 1399 sc->sc_omess[0] = ti->offset; 1400 n = 5; 1401 break; 1402 #endif 1403 1404 #if SPC_USE_WIDE 1405 case SEND_WDTR: 1406 SPC_ASSERT(sc->sc_nexus != NULL); 1407 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1408 sc->sc_omess[3] = MSG_EXTENDED; 1409 sc->sc_omess[2] = 2; 1410 sc->sc_omess[1] = MSG_EXT_WDTR; 1411 sc->sc_omess[0] = ti->width; 1412 n = 4; 1413 break; 1414 #endif 1415 1416 case SEND_DEV_RESET: 1417 sc->sc_flags |= SPC_ABORTING; 1418 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1419 n = 1; 1420 break; 1421 1422 case SEND_REJECT: 1423 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1424 n = 1; 1425 break; 1426 1427 case SEND_PARITY_ERROR: 1428 sc->sc_omess[0] = MSG_PARITY_ERROR; 1429 n = 1; 1430 break; 1431 1432 case SEND_INIT_DET_ERR: 1433 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1434 n = 1; 1435 break; 1436 1437 case SEND_ABORT: 1438 sc->sc_flags |= SPC_ABORTING; 1439 sc->sc_omess[0] = MSG_ABORT; 1440 n = 1; 1441 break; 1442 1443 default: 1444 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1445 sc->sc_dev.dv_xname); 1446 SPC_BREAK(); 1447 sc->sc_omess[0] = MSG_NOOP; 1448 n = 1; 1449 break; 1450 } 1451 sc->sc_omp = &sc->sc_omess[n]; 1452 1453 nextbyte: 1454 /* Send message bytes. */ 1455 /* send TRANSFER command. */ 1456 sc->sc_ps[3] = 1; 1457 sc->sc_ps[4] = n >> 8; 1458 sc->sc_pc[10] = n; 1459 sc->sc_ps[-1] = 0x000F; /* burst */ 1460 asm volatile ("nop"); 1461 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1462 for (;;) { 1463 if ((SSR & SS_BUSY) != 0) 1464 break; 1465 if (SSR & SS_IREQUEST) 1466 goto out; 1467 } 1468 for (;;) { 1469 #if 0 1470 for (;;) { 1471 if ((PSNS & PSNS_REQ) != 0) 1472 break; 1473 /* Wait for REQINIT. XXX Need timeout. */ 1474 } 1475 #endif 1476 if (SSR & SS_IREQUEST) { 1477 /* 1478 * Target left MESSAGE OUT, possibly to reject 1479 * our message. 1480 * 1481 * If this is the last message being sent, then we 1482 * deassert ATN, since either the target is going to 1483 * ignore this message, or it's going to ask for a 1484 * retransmission via MESSAGE PARITY ERROR (in which 1485 * case we reassert ATN anyway). 1486 */ 1487 #if 0 1488 if (sc->sc_msgpriq == 0) 1489 CMR = CMD_RESET_ATN; 1490 #endif 1491 goto out; 1492 } 1493 1494 #if 0 1495 /* Clear ATN before last byte if this is the last message. */ 1496 if (n == 1 && sc->sc_msgpriq == 0) 1497 CMR = CMD_RESET_ATN; 1498 #endif 1499 1500 while ((SSR & SS_DREG_FULL) != 0) 1501 ; 1502 /* Send message byte. */ 1503 sc->sc_pc[0] = *--sc->sc_omp; 1504 --n; 1505 /* Keep track of the last message we've sent any bytes of. */ 1506 sc->sc_lastmsg = sc->sc_currmsg; 1507 1508 if (n == 0) 1509 break; 1510 } 1511 1512 /* We get here only if the entire message has been transmitted. */ 1513 if (sc->sc_msgpriq != 0) { 1514 /* There are more outgoing messages. */ 1515 goto nextmsg; 1516 } 1517 1518 /* 1519 * The last message has been transmitted. We need to remember the last 1520 * message transmitted (in case the target switches to MESSAGE IN phase 1521 * and sends a MESSAGE REJECT), and the list of messages transmitted 1522 * this time around (in case the target stays in MESSAGE OUT phase to 1523 * request a retransmit). 1524 */ 1525 1526 out: 1527 /* Disable REQ/ACK protocol. */ 1528 return; 1529 } 1530 1531 1532 /*************************************************************** 1534 * 1535 * datain/dataout 1536 * 1537 */ 1538 1539 int 1540 mha_datain_pio(sc, p, n) 1541 register struct mha_softc *sc; 1542 u_char *p; 1543 int n; 1544 { 1545 u_short d; 1546 int a; 1547 int total_n = n; 1548 1549 SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n)); 1550 1551 WAIT; 1552 sc->sc_ps[3] = 1; 1553 sc->sc_ps[4] = n >> 8; 1554 sc->sc_pc[10] = n; 1555 /* $BHa$7$-%=%U%HE>Aw(B */ 1556 CMR = CMD_RECEIVE_TO_MPU; 1557 for (;;) { 1558 a = SSR; 1559 if (a & 0x04) { 1560 d = sc->sc_ps[0]; 1561 *p++ = d >> 8; 1562 if (--n > 0) { 1563 *p++ = d; 1564 --n; 1565 } 1566 a = SSR; 1567 } 1568 if (a & 0x40) 1569 continue; 1570 if (a & 0x80) 1571 break; 1572 } 1573 SPC_TRACE(("...%d resd]", n)); 1574 return total_n - n; 1575 } 1576 1577 int 1578 mha_dataout_pio(sc, p, n) 1579 register struct mha_softc *sc; 1580 u_char *p; 1581 int n; 1582 { 1583 u_short d; 1584 int a; 1585 int total_n = n; 1586 1587 SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n)); 1588 1589 WAIT; 1590 sc->sc_ps[3] = 1; 1591 sc->sc_ps[4] = n >> 8; 1592 sc->sc_pc[10] = n; 1593 /* $BHa$7$-%=%U%HE>Aw(B */ 1594 CMR = CMD_SEND_FROM_MPU; 1595 for (;;) { 1596 a = SSR; 1597 if (a & 0x04) { 1598 d = *p++ << 8; 1599 if (--n > 0) { 1600 d |= *p++; 1601 --n; 1602 } 1603 sc->sc_ps[0] = d; 1604 a = SSR; 1605 } 1606 if (a & 0x40) 1607 continue; 1608 if (a & 0x80) 1609 break; 1610 } 1611 SPC_TRACE(("...%d resd]", n)); 1612 return total_n - n; 1613 } 1614 1615 static int 1616 mha_dataio_dma(dw, cw, sc, p, n) 1617 int dw; /* DMA word */ 1618 int cw; /* CMR word */ 1619 register struct mha_softc *sc; 1620 u_char *p; 1621 int n; 1622 { 1623 char *paddr; 1624 1625 if (n > MAXBSIZE) 1626 panic("transfer size exceeds MAXBSIZE"); 1627 if (sc->sc_dmasize > 0) 1628 panic("DMA request while another DMA transfer is in pregress"); 1629 1630 if (cw == CMD_SEND_FROM_DMA) { 1631 memcpy(sc->sc_dmabuf, p, n); 1632 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1633 } else { 1634 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1635 } 1636 sc->sc_p = p; 1637 sc->sc_dmasize = n; 1638 1639 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1640 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1641 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1642 dw &= ~(1 << 3); 1643 #endif 1644 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1645 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1646 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1647 WAIT; 1648 sc->sc_ps[3] = 1; 1649 sc->sc_ps[4] = n >> 8; 1650 sc->sc_pc[10] = n; 1651 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1652 3 ... short bus cycle 1653 2 ... MAXIMUM XFER. 1654 1 ... BURST XFER. 1655 0 ... R/W */ 1656 sc->sc_ps[-1] = dw; /* burst */ 1657 asm volatile ("nop"); 1658 CMR = cw; /* receive to DMA */ 1659 return n; 1660 } 1661 int 1662 mha_dataout(sc, p, n) 1663 register struct mha_softc *sc; 1664 u_char *p; 1665 int n; 1666 { 1667 if (n == 0) 1668 return n; 1669 1670 if (n & 1) 1671 return mha_dataout_pio(sc, p, n); 1672 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1673 } 1674 1675 int 1677 mha_datain(sc, p, n) 1678 register struct mha_softc *sc; 1679 u_char *p; 1680 int n; 1681 { 1682 register struct acb *acb = sc->sc_nexus; 1683 1684 if (n == 0) 1685 return n; 1686 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1687 return mha_datain_pio(sc, p, n); 1688 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1689 } 1690 1691 1693 /* 1694 * Catch an interrupt from the adaptor 1695 */ 1696 /* 1697 * This is the workhorse routine of the driver. 1698 * Deficiencies (for now): 1699 * 1) always uses programmed I/O 1700 */ 1701 int 1702 mhaintr(arg) 1703 void *arg; 1704 { 1705 struct mha_softc *sc = arg; 1706 #if 0 1707 u_char ints; 1708 #endif 1709 struct acb *acb; 1710 u_char ph; 1711 u_short r; 1712 int n; 1713 1714 #if 1 /* XXX called during attach? */ 1715 if (tmpsc != NULL) { 1716 SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc)); 1717 sc = tmpsc; 1718 } else { 1719 #endif 1720 1721 #if 1 /* XXX */ 1722 } 1723 #endif 1724 1725 #if 0 1726 /* 1727 * $B3d$j9~$_6X;_$K$9$k(B 1728 */ 1729 SCTL &= ~SCTL_INTR_ENAB; 1730 #endif 1731 1732 SPC_TRACE(("[mhaintr]")); 1733 1734 /* 1735 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1736 */ 1737 /* 1738 * First check for abnormal conditions, such as reset. 1739 */ 1740 #if 0 1741 #if 1 /* XXX? */ 1742 while (((ints = SSR) & SS_IREQUEST) == 0) 1743 delay(1); 1744 SPC_MISC(("ints = 0x%x ", ints)); 1745 #else /* usually? */ 1746 ints = SSR; 1747 #endif 1748 #endif 1749 while (SSR & SS_IREQUEST) { 1750 acb = sc->sc_nexus; 1751 r = ISCSR; 1752 SPC_MISC(("[r=0x%x]", r)); 1753 switch (r >> 8) { 1754 default: 1755 printf("[addr=%p\n" 1756 "result=0x%x\n" 1757 "cmd=0x%x\n" 1758 "ph=0x%x(ought to be %d)]\n", 1759 &ISCSR, 1760 r, 1761 acb->xs->cmd->opcode, 1762 SCR, sc->sc_phase); 1763 panic("unexpected result."); 1764 case 0x82: /* selection timeout */ 1765 SPC_MISC(("selection timeout ")); 1766 sc->sc_phase = BUSFREE_PHASE; 1767 SPC_ASSERT(sc->sc_nexus != NULL); 1768 acb = sc->sc_nexus; 1769 delay(250); 1770 acb->xs->error = XS_SELTIMEOUT; 1771 mha_done(sc, acb); 1772 continue; /* XXX ??? msaitoh */ 1773 case 0x60: /* command completed */ 1774 sc->sc_spcinitialized++; 1775 if (sc->sc_phase == BUSFREE_PHASE) 1776 continue; 1777 ph = SCR; 1778 if (ph & PSNS_ACK) { 1779 int s; 1780 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1781 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1782 ph & PHASE_MASK, sc->sc_phase)); 1783 #if 0 1784 /* switch (sc->sc_phase) {*/ 1785 #else 1786 switch (ph & PHASE_MASK) { 1787 #endif 1788 case STATUS_PHASE: 1789 if (sc->sc_state != SPC_HASNEXUS) 1790 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1791 sc->sc_state); 1792 SPC_ASSERT(sc->sc_nexus != NULL); 1793 acb = sc->sc_nexus; 1794 WAIT; 1795 s = MBR; 1796 SPC_ASSERT(s == 1); 1797 acb->stat = sc->sc_pcx[0]; /* XXX */ 1798 SPC_MISC(("stat=0x%02x ", acb->stat)); 1799 sc->sc_prevphase = STATUS_PHASE; 1800 break; 1801 case MESSAGE_IN_PHASE: 1802 mha_msgin(sc); 1803 sc->sc_prevphase = MESSAGE_IN_PHASE; 1804 /* thru */ 1805 case DATA_IN_PHASE: 1806 if (sc->sc_dmasize == 0) 1807 break; 1808 bus_dmamap_sync(sc->sc_dmat, 1809 sc->sc_dmamap, 1810 0, sc->sc_dmasize, 1811 BUS_DMASYNC_POSTREAD); 1812 memcpy(sc->sc_p, sc->sc_dmabuf, 1813 sc->sc_dmasize); 1814 sc->sc_dmasize = 0; 1815 break; 1816 case DATA_OUT_PHASE: 1817 if (sc->sc_dmasize == 0) 1818 break; 1819 bus_dmamap_sync(sc->sc_dmat, 1820 sc->sc_dmamap, 1821 0, sc->sc_dmasize, 1822 BUS_DMASYNC_POSTWRITE); 1823 sc->sc_dmasize = 0; 1824 break; 1825 } 1826 WAIT; 1827 CMR = CMD_RESET_ACK; /* reset ack */ 1828 /*mha_done(sc, acb); XXX */ 1829 continue; 1830 } else if (NSR & 0x80) { /* nexus */ 1831 #if 1 1832 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1833 sc->sc_state = SPC_HASNEXUS; 1834 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1835 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1836 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1837 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1838 WAIT; 1839 if (SSR & SS_IREQUEST) 1840 continue; 1841 switch (sc->sc_phase) { 1842 default: 1843 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1844 case MESSAGE_IN_PHASE: 1845 /* $B2?$b$7$J$$(B */ 1846 continue; 1847 case STATUS_PHASE: 1848 sc->sc_phase = MESSAGE_IN_PHASE; 1849 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1850 continue; 1851 case DATA_IN_PHASE: 1852 sc->sc_prevphase = DATA_IN_PHASE; 1853 if (sc->sc_dleft == 0) { 1854 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1855 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1856 sc->sc_phase = STATUS_PHASE; 1857 CMR = CMD_RECEIVE_STS; /* receive sts */ 1858 continue; 1859 } 1860 n = mha_datain(sc, sc->sc_dp, 1861 sc->sc_dleft); 1862 sc->sc_dp += n; 1863 sc->sc_dleft -= n; 1864 continue; 1865 case DATA_OUT_PHASE: 1866 sc->sc_prevphase = DATA_OUT_PHASE; 1867 if (sc->sc_dleft == 0) { 1868 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1869 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1870 sc->sc_phase = STATUS_PHASE; 1871 CMR = CMD_RECEIVE_STS; /* receive sts */ 1872 continue; 1873 } 1874 /* data phase $B$NB3$-$r$d$m$&(B */ 1875 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1876 sc->sc_dp += n; 1877 sc->sc_dleft -= n; 1878 continue; 1879 case COMMAND_PHASE: 1880 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1881 if (acb->dleft) { 1882 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1883 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1884 sc->sc_phase = DATA_IN_PHASE; 1885 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1886 sc->sc_dp += n; 1887 sc->sc_dleft -= n; 1888 } 1889 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1890 sc->sc_phase = DATA_OUT_PHASE; 1891 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1892 sc->sc_dp += n; 1893 sc->sc_dleft -= n; 1894 } 1895 continue; 1896 } 1897 else { 1898 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1899 WAIT; 1900 sc->sc_phase = STATUS_PHASE; 1901 CMR = CMD_RECEIVE_STS; /* receive sts */ 1902 continue; 1903 } 1904 } 1905 #endif 1906 } 1907 continue; 1908 case 0x31: /* disconnected in xfer progress. */ 1909 SPC_MISC(("[0x31]")); 1910 case 0x70: /* disconnected. */ 1911 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1912 sc->sc_phase = BUSFREE_PHASE; 1913 sc->sc_state = SPC_IDLE; 1914 #if 1 1915 acb = sc->sc_nexus; 1916 SPC_ASSERT(sc->sc_nexus != NULL); 1917 acb->xs->error = XS_NOERROR; 1918 mha_done(sc, acb); 1919 #else 1920 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1921 mha_sched(sc); 1922 #endif 1923 continue; 1924 case 0x32: /* phase error in xfer progress. */ 1925 SPC_MISC(("[0x32]")); 1926 #if 0 1927 case 0x65: /* invalid command. 1928 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1929 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1930 #if 1 1931 SPC_MISC(("[0x%04x]", r)); 1932 #endif 1933 #endif 1934 case 0x54: /* initial-phase error. */ 1935 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1936 NSR, 1937 SCR, sc->sc_phase)); 1938 /* thru */ 1939 case 0x71: /* assert req */ 1940 WAIT; 1941 if (SSR & 0x40) { 1942 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1943 SSR, r, NSR, SCR); 1944 WAIT; 1945 } 1946 ph = SCR; 1947 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1948 sc->sc_state = SPC_HASNEXUS; 1949 } 1950 if (ph & 0x80) { 1951 switch (ph & PHASE_MASK) { 1952 default: 1953 printf("phase = %x\n", ph); 1954 panic("assert req: the phase I don't know!"); 1955 case DATA_IN_PHASE: 1956 sc->sc_prevphase = DATA_IN_PHASE; 1957 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1958 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1959 sc->sc_dp += n; 1960 sc->sc_dleft -= n; 1961 SPC_MISC(("done\n")); 1962 continue; 1963 case DATA_OUT_PHASE: 1964 sc->sc_prevphase = DATA_OUT_PHASE; 1965 SPC_MISC(("DATAOUT\n")); 1966 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1967 sc->sc_dp += n; 1968 sc->sc_dleft -= n; 1969 continue; 1970 case STATUS_PHASE: 1971 sc->sc_phase = STATUS_PHASE; 1972 SPC_MISC(("[RECV_STS]")); 1973 WAIT; 1974 CMR = CMD_RECEIVE_STS; /* receive sts */ 1975 continue; 1976 case MESSAGE_IN_PHASE: 1977 sc->sc_phase = MESSAGE_IN_PHASE; 1978 WAIT; 1979 CMR = CMD_RECEIVE_MSG; 1980 continue; 1981 } 1982 } 1983 continue; 1984 } 1985 } 1986 1987 return 1; 1988 } 1989 1990 void 1991 mha_abort(sc, acb) 1992 struct mha_softc *sc; 1993 struct acb *acb; 1994 { 1995 acb->flags |= ACB_ABORTED; 1996 1997 if (acb == sc->sc_nexus) { 1998 /* 1999 * If we're still selecting, the message will be scheduled 2000 * after selection is complete. 2001 */ 2002 if (sc->sc_state == SPC_HASNEXUS) { 2003 sc->sc_flags |= SPC_ABORTING; 2004 mha_sched_msgout(SEND_ABORT); 2005 } 2006 } else { 2007 if (sc->sc_state == SPC_IDLE) 2008 mha_sched(sc); 2009 } 2010 } 2011 2012 void 2013 mha_timeout(arg) 2014 void *arg; 2015 { 2016 int s = splbio(); 2017 struct acb *acb = (struct acb *)arg; 2018 struct scsipi_xfer *xs = acb->xs; 2019 struct scsipi_periph *periph = xs->xs_periph; 2020 struct mha_softc *sc = 2021 (void*)periph->periph_channel->chan_adapter->adapt_dev; 2022 2023 scsipi_printaddr(periph); 2024 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2025 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2026 sc->sc_dev.dv_xname, 2027 acb, acb->flags, acb->dleft, acb->stat, 2028 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2029 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2030 ); 2031 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2032 panic("timeout, ouch!"); 2033 2034 if (acb->flags & ACB_ABORTED) { 2035 /* abort timed out */ 2036 printf(" AGAIN\n"); 2037 #if 0 2038 mha_init(sc, 1); /* XXX 1?*/ 2039 #endif 2040 } else { 2041 /* abort the operation that has timed out */ 2042 printf("\n"); 2043 xs->error = XS_TIMEOUT; 2044 mha_abort(sc, acb); 2045 } 2046 2047 splx(s); 2048 } 2049 2050 #if SPC_DEBUG 2052 /* 2053 * The following functions are mostly used for debugging purposes, either 2054 * directly called from the driver or from the kernel debugger. 2055 */ 2056 2057 void 2058 mha_show_scsi_cmd(acb) 2059 struct acb *acb; 2060 { 2061 u_char *b = (u_char *)&acb->cmd; 2062 struct scsipi_periph *periph = acb->xs->xs_periph; 2063 int i; 2064 2065 scsipi_printaddr(periph); 2066 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2067 for (i = 0; i < acb->clen; i++) { 2068 if (i) 2069 printf(","); 2070 printf("%x", b[i]); 2071 } 2072 printf("\n"); 2073 } else 2074 printf("RESET\n"); 2075 } 2076 2077 void 2078 mha_print_acb(acb) 2079 struct acb *acb; 2080 { 2081 2082 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2083 printf(" dp=%p dleft=%d stat=%x\n", 2084 acb->daddr, acb->dleft, acb->stat); 2085 mha_show_scsi_cmd(acb); 2086 } 2087 2088 void 2089 mha_print_active_acb() 2090 { 2091 struct acb *acb; 2092 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2093 2094 printf("ready list:\n"); 2095 for (acb = sc->ready_list.tqh_first; acb != NULL; 2096 acb = acb->chain.tqe_next) 2097 mha_print_acb(acb); 2098 printf("nexus:\n"); 2099 if (sc->sc_nexus != NULL) 2100 mha_print_acb(sc->sc_nexus); 2101 printf("nexus list:\n"); 2102 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2103 acb = acb->chain.tqe_next) 2104 mha_print_acb(acb); 2105 } 2106 2107 void 2108 mha_dump_driver(sc) 2109 struct mha_softc *sc; 2110 { 2111 struct spc_tinfo *ti; 2112 int i; 2113 2114 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2115 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2116 sc->sc_state, sc->sc_imess[0], 2117 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2118 for (i = 0; i < 7; i++) { 2119 ti = &sc->sc_tinfo[i]; 2120 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2121 i, ti->cmds, ti->dconns, ti->touts); 2122 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2123 } 2124 } 2125 #endif 2126
Indexes created Sun Oct 19 02:09:48 GMT 2025