mha.c revision 1.34
1 /* $NetBSD: mha.c,v 1.34 2003/07/15 01:44:52 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: mha.c,v 1.34 2003/07/15 01:44:52 lukem Exp $"); 70 71 #include "opt_ddb.h" 72 73 /* Synchronous data transfers? */ 74 #define SPC_USE_SYNCHRONOUS 0 75 #define SPC_SYNC_REQ_ACK_OFS 8 76 77 /* Default DMA mode? */ 78 #define MHA_DMA_LIMIT_XFER 1 79 #define MHA_DMA_BURST_XFER 1 80 #define MHA_DMA_SHORT_BUS_CYCLE 1 81 82 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 86 | (MHA_DMA_BURST_XFER << 2) \ 87 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 88 89 /* Include debug functions? At the end of this file there are a bunch of 90 * functions that will print out various information regarding queued SCSI 91 * commands, driver state and chip contents. You can call them from the 92 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 93 * kernel uses less memory) but you lose the debugging facilities. 94 */ 95 #define SPC_DEBUG 0 96 97 /* End of customizable parameters */ 98 99 /* 100 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 101 */ 102 103 #include <sys/types.h> 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/kernel.h> 107 #include <sys/errno.h> 108 #include <sys/ioctl.h> 109 #include <sys/device.h> 110 #include <sys/buf.h> 111 #include <sys/proc.h> 112 #include <sys/user.h> 113 #include <sys/queue.h> 114 115 #include <machine/bus.h> 116 117 #include <dev/scsipi/scsi_all.h> 118 #include <dev/scsipi/scsipi_all.h> 119 #include <dev/scsipi/scsi_message.h> 120 #include <dev/scsipi/scsiconf.h> 121 122 #include <x68k/x68k/iodevice.h> 123 #include <x68k/dev/mb86601reg.h> 124 #include <x68k/dev/mhavar.h> 125 #include <x68k/dev/intiovar.h> 126 #include <x68k/dev/scsiromvar.h> 127 128 #if 0 129 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 130 #else 131 #define WAIT {while (sc->sc_pc[2] & 0x40);} 132 #endif 133 134 #define SSR (sc->sc_pc[2]) 135 #define SS_IREQUEST 0x80 136 #define SS_BUSY 0x40 137 #define SS_DREG_FULL 0x02 138 139 #define NSR (sc->sc_pc[3]) 140 141 #define SIR (sc->sc_pc[4]) 142 143 #define CMR (sc->sc_pc[5]) 144 #define CMD_SEL_AND_CMD 0x00 145 #define CMD_SELECT 0x09 146 #define CMD_SET_ATN 0x0a 147 #define CMD_RESET_ATN 0x0b 148 #define CMD_RESET_ACK 0x0d 149 #define CMD_SEND_FROM_MPU 0x10 150 #define CMD_SEND_FROM_DMA 0x11 151 #define CMD_RECEIVE_TO_MPU 0x12 152 #define CMD_RECEIVE_TO_DMA 0x13 153 #define CMD_RECEIVE_MSG 0x1a 154 #define CMD_RECEIVE_STS 0x1c 155 #define CMD_SOFT_RESET 0x40 156 #define CMD_SCSI_RESET 0x42 157 #define CMD_SET_UP_REG 0x43 158 159 #define SCR (sc->sc_pc[11]) 160 161 #define TMR (sc->sc_pc[12]) 162 #define TM_SYNC 0x80 163 #define TM_ASYNC 0x00 164 165 #define WAR (sc->sc_pc[15]) 166 #define WA_MCSBUFWIN 0x00 167 #define WA_UPMWIN 0x80 168 #define WA_INITWIN 0xc0 169 170 #define MBR (sc->sc_pc[15]) 171 172 #define ISCSR (sc->sc_ps[2]) 173 174 #define CCR (sc->sc_pcx[0]) 175 #define OIR (sc->sc_pcx[1]) 176 #define AMR (sc->sc_pcx[2]) 177 #define SMR (sc->sc_pcx[3]) 178 #define SRR (sc->sc_pcx[4]) 179 #define STR (sc->sc_pcx[5]) 180 #define RTR (sc->sc_pcx[6]) 181 #define ATR (sc->sc_pcx[7]) 182 #define PER (sc->sc_pcx[8]) 183 #define IER (sc->sc_pcx[9]) 184 #define IE_ALL 0xBF 185 186 #define GLR (sc->sc_pcx[10]) 187 #define DMR (sc->sc_pcx[11]) 188 #define IMR (sc->sc_pcx[12]) 189 190 191 #ifndef DDB 193 #define Debugger() panic("should call debugger here (mha.c)") 194 #endif /* ! DDB */ 195 196 197 #if SPC_DEBUG 198 #define SPC_SHOWACBS 0x01 199 #define SPC_SHOWINTS 0x02 200 #define SPC_SHOWCMDS 0x04 201 #define SPC_SHOWMISC 0x08 202 #define SPC_SHOWTRAC 0x10 203 #define SPC_SHOWSTART 0x20 204 #define SPC_SHOWPHASE 0x40 205 #define SPC_SHOWDMA 0x80 206 #define SPC_SHOWCCMDS 0x100 207 #define SPC_SHOWMSGS 0x200 208 #define SPC_DOBREAK 0x400 209 210 int mha_debug = 211 #if 0 212 0x7FF; 213 #else 214 SPC_SHOWSTART|SPC_SHOWTRAC; 215 #endif 216 217 218 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 219 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 220 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 221 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 222 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 223 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 224 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 225 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 226 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 227 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 228 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 229 #else 230 #define SPC_ACBS(str) 231 #define SPC_MISC(str) 232 #define SPC_INTS(str) 233 #define SPC_TRACE(str) 234 #define SPC_CMDS(str) 235 #define SPC_START(str) 236 #define SPC_PHASE(str) 237 #define SPC_DMA(str) 238 #define SPC_MSGS(str) 239 #define SPC_BREAK() 240 #define SPC_ASSERT(x) 241 #endif 242 243 int mhamatch __P((struct device *, struct cfdata *, void *)); 244 void mhaattach __P((struct device *, struct device *, void *)); 245 void mhaselect __P((struct mha_softc *, 246 u_char, u_char, u_char *, u_char)); 247 void mha_scsi_reset __P((struct mha_softc *)); 248 void mha_reset __P((struct mha_softc *)); 249 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 250 void mha_sense __P((struct mha_softc *, struct acb *)); 251 void mha_msgin __P((struct mha_softc *)); 252 void mha_msgout __P((struct mha_softc *)); 253 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 254 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 255 int mha_dataout __P((struct mha_softc *, u_char *, int)); 256 int mha_datain __P((struct mha_softc *, u_char *, int)); 257 void mha_abort __P((struct mha_softc *, struct acb *)); 258 void mha_init __P((struct mha_softc *)); 259 void mha_scsi_request __P((struct scsipi_channel *, 260 scsipi_adapter_req_t, void *)); 261 void mha_poll __P((struct mha_softc *, struct acb *)); 262 void mha_sched __P((struct mha_softc *)); 263 void mha_done __P((struct mha_softc *, struct acb *)); 264 int mhaintr __P((void*)); 265 void mha_timeout __P((void *)); 266 void mha_minphys __P((struct buf *)); 267 void mha_dequeue __P((struct mha_softc *, struct acb *)); 268 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 269 #if SPC_DEBUG 270 void mha_print_acb __P((struct acb *)); 271 void mha_show_scsi_cmd __P((struct acb *)); 272 void mha_print_active_acb __P((void)); 273 void mha_dump_driver __P((struct mha_softc *)); 274 #endif 275 276 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 277 278 CFATTACH_DECL(mha, sizeof(struct mha_softc), 279 mhamatch, mhaattach, NULL, NULL); 280 281 extern struct cfdriver mha_cd; 282 283 284 /* 286 * returns non-zero value if a controller is found. 287 */ 288 int 289 mhamatch(parent, cf, aux) 290 struct device *parent; 291 struct cfdata *cf; 292 void *aux; 293 { 294 struct intio_attach_args *ia = aux; 295 bus_space_tag_t iot = ia->ia_bst; 296 bus_space_handle_t ioh; 297 298 ia->ia_size=0x20; 299 if (ia->ia_addr != 0xea0000) 300 return 0; 301 302 if (intio_map_allocate_region(parent->dv_parent, ia, 303 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 304 return 0; 305 306 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 307 &ioh) < 0) 308 return 0; 309 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 310 return 0; 311 bus_space_unmap(iot, ioh, 0x20); 312 313 return 1; 314 } 315 316 /* 317 */ 318 319 struct mha_softc *tmpsc; 320 321 void 322 mhaattach(parent, self, aux) 323 struct device *parent, *self; 324 void *aux; 325 { 326 struct mha_softc *sc = (void *)self; 327 struct intio_attach_args *ia = aux; 328 329 tmpsc = sc; /* XXX */ 330 331 printf (": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 332 333 SPC_TRACE(("mhaattach ")); 334 sc->sc_state = SPC_INIT; 335 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 336 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 337 /* XXX: FAKE */ 338 sc->sc_dmat = ia->ia_dmat; 339 340 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 341 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 342 sc->sc_pcx = &sc->sc_pc[0x10]; 343 344 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 345 346 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 347 348 mha_init(sc); /* Init chip and driver */ 349 350 mha_scsi_reset(sc); /* XXX: some devices need this. */ 351 352 sc->sc_phase = BUSFREE_PHASE; 353 354 /* 355 * Fill in the adapter. 356 */ 357 sc->sc_adapter.adapt_dev = &sc->sc_dev; 358 sc->sc_adapter.adapt_nchannels = 1; 359 sc->sc_adapter.adapt_openings = 7; 360 sc->sc_adapter.adapt_max_periph = 1; 361 sc->sc_adapter.adapt_ioctl = NULL; 362 sc->sc_adapter.adapt_minphys = mha_minphys; 363 sc->sc_adapter.adapt_request = mha_scsi_request; 364 365 sc->sc_channel.chan_adapter = &sc->sc_adapter; 366 sc->sc_channel.chan_bustype = &scsi_bustype; 367 sc->sc_channel.chan_channel = 0; 368 sc->sc_channel.chan_ntargets = 8; 369 sc->sc_channel.chan_nluns = 8; 370 sc->sc_channel.chan_id = sc->sc_id; 371 372 sc->sc_spcinitialized = 0; 373 WAR = WA_INITWIN; 374 #if 1 375 CCR = 0x14; 376 OIR = sc->sc_id; 377 AMR = 0x00; 378 SMR = 0x00; 379 SRR = 0x00; 380 STR = 0x20; 381 RTR = 0x40; 382 ATR = 0x01; 383 PER = 0xc9; 384 #endif 385 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 386 #if 1 387 GLR = 0x00; 388 DMR = 0x30; 389 IMR = 0x00; 390 #endif 391 WAR = WA_MCSBUFWIN; 392 393 /* drop off */ 394 while (SSR & SS_IREQUEST) 395 { 396 (void) ISCSR; 397 } 398 399 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 400 401 SPC_TRACE(("waiting for intr...")); 402 while (!(SSR & SS_IREQUEST)) 403 delay(10); 404 mhaintr (sc); 405 406 tmpsc = NULL; 407 408 config_found(self, &sc->sc_channel, scsiprint); 409 } 410 411 #if 0 412 void 413 mha_reset(sc) 414 struct mha_softc *sc; 415 { 416 u_short dummy; 417 printf("reset..."); 418 CMR = CMD_SOFT_RESET; 419 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 420 dummy = sc->sc_ps[-1]; 421 dummy = sc->sc_ps[-1]; 422 dummy = sc->sc_ps[-1]; 423 dummy = sc->sc_ps[-1]; 424 asm volatile ("nop"); 425 CMR = CMD_SOFT_RESET; 426 sc->sc_spcinitialized = 0; 427 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 428 while(!sc->sc_spcinitialized); 429 430 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 431 printf("done.\n"); 432 } 433 #endif 434 435 /* 436 * Pull the SCSI RST line for 500us. 437 */ 438 void 439 mha_scsi_reset(sc) /* FINISH? */ 440 struct mha_softc *sc; 441 { 442 443 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 444 while (!(SSR&SS_IREQUEST)) 445 delay(10); 446 } 447 448 /* 449 * Initialize mha SCSI driver. 450 */ 451 void 452 mha_init(sc) 453 struct mha_softc *sc; 454 { 455 struct acb *acb; 456 int r; 457 458 if (sc->sc_state == SPC_INIT) { 459 /* First time through; initialize. */ 460 TAILQ_INIT(&sc->ready_list); 461 TAILQ_INIT(&sc->nexus_list); 462 TAILQ_INIT(&sc->free_list); 463 sc->sc_nexus = NULL; 464 acb = sc->sc_acb; 465 memset(acb, 0, sizeof(sc->sc_acb)); 466 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 467 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 468 acb++; 469 } 470 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 471 472 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 473 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 474 BUS_DMA_NOWAIT); 475 if (r) 476 panic("mha_init: cannot allocate DMA memory"); 477 if (sc->sc_ndmasegs != 1) 478 panic("mha_init: number of segment > 1??"); 479 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 480 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 481 if (r) 482 panic("mha_init: cannot map DMA memory"); 483 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 484 MAXBSIZE, 0, BUS_DMA_NOWAIT, 485 &sc->sc_dmamap); 486 if (r) 487 panic("mha_init: cannot create dmamap structure"); 488 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 489 sc->sc_dmabuf, MAXBSIZE, NULL, 490 BUS_DMA_NOWAIT); 491 if (r) 492 panic("mha_init: cannot load DMA buffer into dmamap"); 493 sc->sc_p = 0; 494 } else { 495 /* Cancel any active commands. */ 496 sc->sc_flags |= SPC_ABORTING; 497 sc->sc_state = SPC_IDLE; 498 if ((acb = sc->sc_nexus) != NULL) { 499 acb->xs->error = XS_DRIVER_STUFFUP; 500 mha_done(sc, acb); 501 } 502 while ((acb = sc->nexus_list.tqh_first) != NULL) { 503 acb->xs->error = XS_DRIVER_STUFFUP; 504 mha_done(sc, acb); 505 } 506 } 507 508 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 509 for (r = 0; r < 8; r++) { 510 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 511 512 ti->flags = 0; 513 #if SPC_USE_SYNCHRONOUS 514 ti->flags |= T_SYNCMODE; 515 ti->period = sc->sc_minsync; 516 ti->offset = SPC_SYNC_REQ_ACK_OFS; 517 #else 518 ti->period = ti->offset = 0; 519 #endif 520 ti->width = 0; 521 } 522 523 sc->sc_state = SPC_IDLE; 524 } 525 526 void 527 mha_free_acb(sc, acb, flags) 528 struct mha_softc *sc; 529 struct acb *acb; 530 int flags; 531 { 532 int s; 533 534 s = splbio(); 535 536 acb->flags = 0; 537 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 538 539 /* 540 * If there were none, wake anybody waiting for one to come free, 541 * starting with queued entries. 542 */ 543 if (acb->chain.tqe_next == 0) 544 wakeup(&sc->free_list); 545 546 splx(s); 547 } 548 549 550 /* 552 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 553 */ 554 555 /* 556 * Expected sequence: 557 * 1) Command inserted into ready list 558 * 2) Command selected for execution 559 * 3) Command won arbitration and has selected target device 560 * 4) Send message out (identify message, eventually also sync.negotiations) 561 * 5) Send command 562 * 5a) Receive disconnect message, disconnect. 563 * 5b) Reselected by target 564 * 5c) Receive identify message from target. 565 * 6) Send or receive data 566 * 7) Receive status 567 * 8) Receive message (command complete etc.) 568 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 569 * Repeat 2-8 (no disconnects please...) 570 */ 571 572 /* 573 * Start a selection. This is used by mha_sched() to select an idle target, 574 * and by mha_done() to immediately reselect a target to get sense information. 575 */ 576 void 577 mhaselect(sc, target, lun, cmd, clen) 578 struct mha_softc *sc; 579 u_char target, lun; 580 u_char *cmd; 581 u_char clen; 582 { 583 int i; 584 int s; 585 586 s = splbio(); /* XXX */ 587 588 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 589 590 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 591 /* Now the command into the FIFO */ 592 WAIT; 593 #if 1 594 SPC_MISC(("[cmd:")); 595 for (i = 0; i < clen; i++) 596 { 597 unsigned c = cmd[i]; 598 if (i == 1) 599 c |= lun << 5; 600 SPC_MISC((" %02x", c)); 601 sc->sc_pcx[i] = c; 602 } 603 SPC_MISC(("], target=%d\n", target)); 604 #else 605 memcpy(sc->sc_pcx, cmd, clen); 606 #endif 607 if (NSR & 0x80) 608 panic("scsistart: already selected..."); 609 sc->sc_phase = COMMAND_PHASE; 610 611 /* new state ASP_SELECTING */ 612 sc->sc_state = SPC_SELECTING; 613 614 SIR = target; 615 #if 0 616 CMR = CMD_SELECT; 617 #else 618 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 619 #endif 620 splx(s); 621 } 622 623 #if 0 624 int 625 mha_reselect(sc, message) 626 struct mha_softc *sc; 627 u_char message; 628 { 629 u_char selid, target, lun; 630 struct acb *acb; 631 struct scsipi_periph *periph; 632 struct spc_tinfo *ti; 633 634 /* 635 * The SCSI chip made a snapshot of the data bus while the reselection 636 * was being negotiated. This enables us to determine which target did 637 * the reselect. 638 */ 639 selid = sc->sc_selid & ~(1 << sc->sc_id); 640 if (selid & (selid - 1)) { 641 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 642 sc->sc_dev.dv_xname, selid); 643 SPC_BREAK(); 644 goto reset; 645 } 646 647 /* 648 * Search wait queue for disconnected cmd 649 * The list should be short, so I haven't bothered with 650 * any more sophisticated structures than a simple 651 * singly linked list. 652 */ 653 target = ffs(selid) - 1; 654 lun = message & 0x07; 655 for (acb = sc->nexus_list.tqh_first; acb != NULL; 656 acb = acb->chain.tqe_next) { 657 periph = acb->xs->xs_periph; 658 if (periph->periph_target == target && 659 periph->periph_lun == lun) 660 break; 661 } 662 if (acb == NULL) { 663 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 664 sc->sc_dev.dv_xname, target, lun); 665 SPC_BREAK(); 666 goto abort; 667 } 668 669 /* Make this nexus active again. */ 670 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 671 sc->sc_state = SPC_HASNEXUS; 672 sc->sc_nexus = acb; 673 ti = &sc->sc_tinfo[target]; 674 ti->lubusy |= (1 << lun); 675 mha_setsync(sc, ti); 676 677 if (acb->flags & ACB_RESET) 678 mha_sched_msgout(sc, SEND_DEV_RESET); 679 else if (acb->flags & ACB_ABORTED) 680 mha_sched_msgout(sc, SEND_ABORT); 681 682 /* Do an implicit RESTORE POINTERS. */ 683 sc->sc_dp = acb->daddr; 684 sc->sc_dleft = acb->dleft; 685 sc->sc_cp = (u_char *)&acb->cmd; 686 sc->sc_cleft = acb->clen; 687 688 return (0); 689 690 reset: 691 mha_sched_msgout(sc, SEND_DEV_RESET); 692 return (1); 693 694 abort: 695 mha_sched_msgout(sc, SEND_ABORT); 696 return (1); 697 } 698 #endif 699 /* 700 * Start a SCSI-command 701 * This function is called by the higher level SCSI-driver to queue/run 702 * SCSI-commands. 703 */ 704 void 705 mha_scsi_request(chan, req, arg) 706 struct scsipi_channel *chan; 707 scsipi_adapter_req_t req; 708 void *arg; 709 { 710 struct scsipi_xfer *xs; 711 struct scsipi_periph *periph; 712 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 713 struct acb *acb; 714 int s, flags; 715 716 switch (req) { 717 case ADAPTER_REQ_RUN_XFER: 718 xs = arg; 719 periph = xs->xs_periph; 720 721 SPC_TRACE(("[mha_scsi_cmd] ")); 722 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 723 periph->periph_target)); 724 725 flags = xs->xs_control; 726 727 /* Get a mha command block */ 728 s = splbio(); 729 acb = sc->free_list.tqh_first; 730 if (acb) { 731 TAILQ_REMOVE(&sc->free_list, acb, chain); 732 ACB_SETQ(acb, ACB_QNONE); 733 } 734 735 if (acb == NULL) { 736 xs->error = XS_RESOURCE_SHORTAGE; 737 scsipi_done(xs); 738 splx(s); 739 return; 740 } 741 splx(s); 742 743 /* Initialize acb */ 744 acb->xs = xs; 745 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 746 acb->clen = xs->cmdlen; 747 acb->daddr = xs->data; 748 acb->dleft = xs->datalen; 749 acb->stat = 0; 750 751 s = splbio(); 752 ACB_SETQ(acb, ACB_QREADY); 753 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 754 #if 1 755 callout_reset(&acb->xs->xs_callout, 756 mstohz(xs->timeout), mha_timeout, acb); 757 #endif 758 759 /* 760 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 761 */ 762 if (sc->sc_state == SPC_IDLE) 763 mha_sched(sc); 764 765 splx(s); 766 767 if (flags & XS_CTL_POLL) { 768 /* Not allowed to use interrupts, use polling instead */ 769 mha_poll(sc, acb); 770 } 771 772 SPC_MISC(("SUCCESSFULLY_QUEUED")); 773 return; 774 775 case ADAPTER_REQ_GROW_RESOURCES: 776 /* XXX Not supported. */ 777 return; 778 779 case ADAPTER_REQ_SET_XFER_MODE: 780 /* XXX Not supported. */ 781 return; 782 } 783 } 784 785 /* 786 * Adjust transfer size in buffer structure 787 */ 788 void 789 mha_minphys(bp) 790 struct buf *bp; 791 { 792 793 SPC_TRACE(("mha_minphys ")); 794 minphys(bp); 795 } 796 797 /* 798 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 799 */ 800 void 801 mha_poll(sc, acb) 802 struct mha_softc *sc; 803 struct acb *acb; 804 { 805 struct scsipi_xfer *xs = acb->xs; 806 int count = xs->timeout * 100; 807 int s = splbio(); 808 809 SPC_TRACE(("[mha_poll] ")); 810 811 while (count) { 812 /* 813 * If we had interrupts enabled, would we 814 * have got an interrupt? 815 */ 816 if (SSR & SS_IREQUEST) 817 mhaintr(sc); 818 if ((xs->xs_status & XS_STS_DONE) != 0) 819 break; 820 DELAY(10); 821 #if 1 822 if (sc->sc_state == SPC_IDLE) { 823 SPC_TRACE(("[mha_poll: rescheduling] ")); 824 mha_sched(sc); 825 } 826 #endif 827 count--; 828 } 829 830 if (count == 0) { 831 SPC_MISC(("mha_poll: timeout")); 832 mha_timeout((caddr_t)acb); 833 } 834 splx(s); 835 scsipi_done(xs); 836 } 837 838 /* 840 * LOW LEVEL SCSI UTILITIES 841 */ 842 843 /* 844 * Set synchronous transfer offset and period. 845 */ 846 inline void 847 mha_setsync(sc, ti) 848 struct mha_softc *sc; 849 struct spc_tinfo *ti; 850 { 851 } 852 853 854 /* 856 * Schedule a SCSI operation. This has now been pulled out of the interrupt 857 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 858 * save us an unecessary interrupt just to get things going. Should only be 859 * called when state == SPC_IDLE and at bio pl. 860 */ 861 void 862 mha_sched(sc) 863 register struct mha_softc *sc; 864 { 865 struct scsipi_periph *periph; 866 struct acb *acb; 867 int t; 868 869 SPC_TRACE(("[mha_sched] ")); 870 if (sc->sc_state != SPC_IDLE) 871 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 872 873 if (sc->sc_flags & SPC_ABORTING) 874 return; 875 876 /* 877 * Find first acb in ready queue that is for a target/lunit 878 * combinations that is not busy. 879 */ 880 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 881 struct spc_tinfo *ti; 882 periph = acb->xs->xs_periph; 883 t = periph->periph_target; 884 ti = &sc->sc_tinfo[t]; 885 if (!(ti->lubusy & (1 << periph->periph_lun))) { 886 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 887 panic("mha: busy entry on ready list"); 888 TAILQ_REMOVE(&sc->ready_list, acb, chain); 889 ACB_SETQ(acb, ACB_QNONE); 890 sc->sc_nexus = acb; 891 sc->sc_flags = 0; 892 sc->sc_prevphase = INVALID_PHASE; 893 sc->sc_dp = acb->daddr; 894 sc->sc_dleft = acb->dleft; 895 ti->lubusy |= (1<<periph->periph_lun); 896 mhaselect(sc, t, periph->periph_lun, 897 (u_char *)&acb->cmd, acb->clen); 898 break; 899 } else { 900 SPC_MISC(("%d:%d busy\n", 901 periph->periph_target, 902 periph->periph_lun)); 903 } 904 } 905 } 906 907 /* 909 * POST PROCESSING OF SCSI_CMD (usually current) 910 */ 911 void 912 mha_done(sc, acb) 913 struct mha_softc *sc; 914 struct acb *acb; 915 { 916 struct scsipi_xfer *xs = acb->xs; 917 struct scsipi_periph *periph = xs->xs_periph; 918 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 919 920 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 921 922 #if 1 923 callout_stop(&acb->xs->xs_callout); 924 #endif 925 926 /* 927 * Now, if we've come here with no error code, i.e. we've kept the 928 * initial XS_NOERROR, and the status code signals that we should 929 * check sense, we'll need to set up a request sense cmd block and 930 * push the command back into the ready queue *before* any other 931 * commands for this target/lunit, else we lose the sense info. 932 * We don't support chk sense conditions for the request sense cmd. 933 */ 934 if (xs->error == XS_NOERROR) { 935 if ((acb->flags & ACB_ABORTED) != 0) { 936 xs->error = XS_TIMEOUT; 937 } else if (acb->flags & ACB_CHKSENSE) { 938 xs->error = XS_SENSE; 939 } else { 940 xs->status = acb->stat & ST_MASK; 941 switch (xs->status) { 942 case SCSI_CHECK: 943 xs->resid = acb->dleft; 944 /* FALLTHOUGH */ 945 case SCSI_BUSY: 946 xs->error = XS_BUSY; 947 break; 948 case SCSI_OK: 949 xs->resid = acb->dleft; 950 break; 951 default: 952 xs->error = XS_DRIVER_STUFFUP; 953 #if SPC_DEBUG 954 printf("%s: mha_done: bad stat 0x%x\n", 955 sc->sc_dev.dv_xname, acb->stat); 956 #endif 957 break; 958 } 959 } 960 } 961 962 #if SPC_DEBUG 963 if ((mha_debug & SPC_SHOWMISC) != 0) { 964 if (xs->resid != 0) 965 printf("resid=%d ", xs->resid); 966 if (xs->error == XS_SENSE) 967 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 968 else 969 printf("error=%d\n", xs->error); 970 } 971 #endif 972 973 /* 974 * Remove the ACB from whatever queue it's on. 975 */ 976 switch (acb->flags & ACB_QBITS) { 977 case ACB_QNONE: 978 if (acb != sc->sc_nexus) { 979 panic("%s: floating acb", sc->sc_dev.dv_xname); 980 } 981 sc->sc_nexus = NULL; 982 sc->sc_state = SPC_IDLE; 983 ti->lubusy &= ~(1<<periph->periph_lun); 984 mha_sched(sc); 985 break; 986 case ACB_QREADY: 987 TAILQ_REMOVE(&sc->ready_list, acb, chain); 988 break; 989 case ACB_QNEXUS: 990 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 991 ti->lubusy &= ~(1<<periph->periph_lun); 992 break; 993 case ACB_QFREE: 994 panic("%s: dequeue: busy acb on free list", 995 sc->sc_dev.dv_xname); 996 break; 997 default: 998 panic("%s: dequeue: unknown queue %d", 999 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 1000 } 1001 1002 /* Put it on the free list, and clear flags. */ 1003 #if 0 1004 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 1005 acb->flags = ACB_QFREE; 1006 #else 1007 mha_free_acb(sc, acb, xs->xs_control); 1008 #endif 1009 1010 ti->cmds++; 1011 scsipi_done(xs); 1012 } 1013 1014 void 1015 mha_dequeue(sc, acb) 1016 struct mha_softc *sc; 1017 struct acb *acb; 1018 { 1019 1020 if (acb->flags & ACB_QNEXUS) { 1021 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1022 } else { 1023 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1024 } 1025 } 1026 1027 /* 1029 * INTERRUPT/PROTOCOL ENGINE 1030 */ 1031 1032 /* 1033 * Schedule an outgoing message by prioritizing it, and asserting 1034 * attention on the bus. We can only do this when we are the initiator 1035 * else there will be an illegal command interrupt. 1036 */ 1037 #define mha_sched_msgout(m) \ 1038 do { \ 1039 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1040 CMR = CMD_SET_ATN; \ 1041 sc->sc_msgpriq |= (m); \ 1042 } while (0) 1043 1044 /* 1045 * Precondition: 1046 * The SCSI bus is already in the MSGI phase and there is a message byte 1047 * on the bus, along with an asserted REQ signal. 1048 */ 1049 void 1050 mha_msgin(sc) 1051 register struct mha_softc *sc; 1052 { 1053 register int v; 1054 1055 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1056 1057 /* 1058 * Prepare for a new message. A message should (according 1059 * to the SCSI standard) be transmitted in one single 1060 * MESSAGE_IN_PHASE. If we have been in some other phase, 1061 * then this is a new message. 1062 */ 1063 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1064 sc->sc_flags &= ~SPC_DROP_MSGI; 1065 sc->sc_imlen = 0; 1066 } 1067 1068 WAIT; 1069 1070 v = MBR; /* modified byte */ 1071 v = sc->sc_pcx[0]; 1072 1073 sc->sc_imess[sc->sc_imlen] = v; 1074 1075 /* 1076 * If we're going to reject the message, don't bother storing 1077 * the incoming bytes. But still, we need to ACK them. 1078 */ 1079 1080 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1081 CMR = CMD_SET_ATN; 1082 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1083 printf("<dropping msg byte %x>", 1084 sc->sc_imess[sc->sc_imlen]); 1085 return; 1086 } 1087 1088 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1089 mha_sched_msgout(SEND_REJECT); 1090 sc->sc_flags |= SPC_DROP_MSGI; 1091 } else { 1092 sc->sc_imlen++; 1093 /* 1094 * This testing is suboptimal, but most 1095 * messages will be of the one byte variety, so 1096 * it should not effect performance 1097 * significantly. 1098 */ 1099 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1100 goto gotit; 1101 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1102 goto gotit; 1103 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1104 sc->sc_imlen == sc->sc_imess[1] + 2) 1105 goto gotit; 1106 } 1107 #if 0 1108 /* Ack what we have so far */ 1109 ESPCMD(sc, ESPCMD_MSGOK); 1110 #endif 1111 return; 1112 1113 gotit: 1114 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1115 /* 1116 * Now we should have a complete message (1 byte, 2 byte 1117 * and moderately long extended messages). We only handle 1118 * extended messages which total length is shorter than 1119 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1120 */ 1121 if (sc->sc_state == SPC_HASNEXUS) { 1122 struct acb *acb = sc->sc_nexus; 1123 struct spc_tinfo *ti = 1124 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1125 1126 switch (sc->sc_imess[0]) { 1127 case MSG_CMDCOMPLETE: 1128 SPC_MSGS(("cmdcomplete ")); 1129 if (sc->sc_dleft < 0) { 1130 struct scsipi_periph *periph = acb->xs->xs_periph; 1131 printf("mha: %d extra bytes from %d:%d\n", 1132 -sc->sc_dleft, 1133 periph->periph_target, 1134 periph->periph_lun); 1135 sc->sc_dleft = 0; 1136 } 1137 acb->xs->resid = acb->dleft = sc->sc_dleft; 1138 sc->sc_flags |= SPC_BUSFREE_OK; 1139 break; 1140 1141 case MSG_MESSAGE_REJECT: 1142 #if SPC_DEBUG 1143 if (mha_debug & SPC_SHOWMSGS) 1144 printf("%s: our msg rejected by target\n", 1145 sc->sc_dev.dv_xname); 1146 #endif 1147 #if 1 /* XXX - must remember last message */ 1148 scsipi_printaddr(acb->xs->xs_periph); 1149 printf("MSG_MESSAGE_REJECT>>"); 1150 #endif 1151 if (sc->sc_flags & SPC_SYNCHNEGO) { 1152 ti->period = ti->offset = 0; 1153 sc->sc_flags &= ~SPC_SYNCHNEGO; 1154 ti->flags &= ~T_NEGOTIATE; 1155 } 1156 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1157 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1158 mha_sched_msgout(SEND_ABORT); 1159 break; 1160 case MSG_NOOP: 1161 SPC_MSGS(("noop ")); 1162 break; 1163 case MSG_DISCONNECT: 1164 SPC_MSGS(("disconnect ")); 1165 ti->dconns++; 1166 sc->sc_flags |= SPC_DISCON; 1167 sc->sc_flags |= SPC_BUSFREE_OK; 1168 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1169 break; 1170 /*FALLTHROUGH*/ 1171 case MSG_SAVEDATAPOINTER: 1172 SPC_MSGS(("save datapointer ")); 1173 acb->dleft = sc->sc_dleft; 1174 acb->daddr = sc->sc_dp; 1175 break; 1176 case MSG_RESTOREPOINTERS: 1177 SPC_MSGS(("restore datapointer ")); 1178 if (!acb) { 1179 mha_sched_msgout(SEND_ABORT); 1180 printf("%s: no DATAPOINTERs to restore\n", 1181 sc->sc_dev.dv_xname); 1182 break; 1183 } 1184 sc->sc_dp = acb->daddr; 1185 sc->sc_dleft = acb->dleft; 1186 break; 1187 case MSG_PARITY_ERROR: 1188 printf("%s:target%d: MSG_PARITY_ERROR\n", 1189 sc->sc_dev.dv_xname, 1190 acb->xs->xs_periph->periph_target); 1191 break; 1192 case MSG_EXTENDED: 1193 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1194 switch (sc->sc_imess[2]) { 1195 case MSG_EXT_SDTR: 1196 SPC_MSGS(("SDTR period %d, offset %d ", 1197 sc->sc_imess[3], sc->sc_imess[4])); 1198 ti->period = sc->sc_imess[3]; 1199 ti->offset = sc->sc_imess[4]; 1200 if (sc->sc_minsync == 0) { 1201 /* We won't do synch */ 1202 ti->offset = 0; 1203 mha_sched_msgout(SEND_SDTR); 1204 } else if (ti->offset == 0) { 1205 printf("%s:%d: async\n", "mha", 1206 acb->xs->xs_periph->periph_target); 1207 ti->offset = 0; 1208 sc->sc_flags &= ~SPC_SYNCHNEGO; 1209 } else if (ti->period > 124) { 1210 printf("%s:%d: async\n", "mha", 1211 acb->xs->xs_periph->periph_target); 1212 ti->offset = 0; 1213 mha_sched_msgout(SEND_SDTR); 1214 } else { 1215 #if 0 1216 int p; 1217 p = mha_stp2cpb(sc, ti->period); 1218 ti->period = mha_cpb2stp(sc, p); 1219 #endif 1220 1221 #if SPC_DEBUG 1222 scsipi_printaddr(acb->xs->xs_periph); 1223 #endif 1224 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1225 /* Target initiated negotiation */ 1226 if (ti->flags & T_SYNCMODE) { 1227 ti->flags &= ~T_SYNCMODE; 1228 #if SPC_DEBUG 1229 printf("renegotiated "); 1230 #endif 1231 } 1232 TMR=TM_ASYNC; 1233 /* Clamp to our maxima */ 1234 if (ti->period < sc->sc_minsync) 1235 ti->period = sc->sc_minsync; 1236 if (ti->offset > 15) 1237 ti->offset = 15; 1238 mha_sched_msgout(SEND_SDTR); 1239 } else { 1240 /* we are sync */ 1241 sc->sc_flags &= ~SPC_SYNCHNEGO; 1242 TMR = TM_SYNC; 1243 ti->flags |= T_SYNCMODE; 1244 } 1245 } 1246 ti->flags &= ~T_NEGOTIATE; 1247 break; 1248 default: /* Extended messages we don't handle */ 1249 CMR = CMD_SET_ATN; /* XXX? */ 1250 break; 1251 } 1252 break; 1253 default: 1254 SPC_MSGS(("ident ")); 1255 /* thanks for that ident... */ 1256 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1257 SPC_MISC(("unknown ")); 1258 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1259 CMR = CMD_SET_ATN; /* XXX? */ 1260 } 1261 break; 1262 } 1263 } else if (sc->sc_state == SPC_RESELECTED) { 1264 struct scsipi_periph *periph = NULL; 1265 struct acb *acb; 1266 struct spc_tinfo *ti; 1267 u_char lunit; 1268 1269 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1270 SPC_MISC(("searching ")); 1271 /* 1272 * Search wait queue for disconnected cmd 1273 * The list should be short, so I haven't bothered with 1274 * any more sophisticated structures than a simple 1275 * singly linked list. 1276 */ 1277 lunit = sc->sc_imess[0] & 0x07; 1278 for (acb = sc->nexus_list.tqh_first; acb; 1279 acb = acb->chain.tqe_next) { 1280 periph = acb->xs->xs_periph; 1281 if (periph->periph_lun == lunit && 1282 sc->sc_selid == (1<<periph->periph_target)) { 1283 TAILQ_REMOVE(&sc->nexus_list, acb, 1284 chain); 1285 ACB_SETQ(acb, ACB_QNONE); 1286 break; 1287 } 1288 } 1289 1290 if (!acb) { /* Invalid reselection! */ 1291 mha_sched_msgout(SEND_ABORT); 1292 printf("mha: invalid reselect (idbit=0x%2x)\n", 1293 sc->sc_selid); 1294 } else { /* Reestablish nexus */ 1295 /* 1296 * Setup driver data structures and 1297 * do an implicit RESTORE POINTERS 1298 */ 1299 ti = &sc->sc_tinfo[periph->periph_target]; 1300 sc->sc_nexus = acb; 1301 sc->sc_dp = acb->daddr; 1302 sc->sc_dleft = acb->dleft; 1303 sc->sc_tinfo[periph->periph_target].lubusy 1304 |= (1<<periph->periph_lun); 1305 if (ti->flags & T_SYNCMODE) { 1306 TMR = TM_SYNC; /* XXX */ 1307 } else { 1308 TMR = TM_ASYNC; 1309 } 1310 SPC_MISC(("... found acb")); 1311 sc->sc_state = SPC_HASNEXUS; 1312 } 1313 } else { 1314 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1315 sc->sc_dev.dv_xname, sc->sc_selid); 1316 mha_sched_msgout(SEND_DEV_RESET); 1317 } 1318 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1319 printf("%s: unexpected message in; will send DEV_RESET\n", 1320 sc->sc_dev.dv_xname); 1321 mha_sched_msgout(SEND_DEV_RESET); 1322 } 1323 1324 /* Ack last message byte */ 1325 #if 0 1326 ESPCMD(sc, ESPCMD_MSGOK); 1327 #endif 1328 1329 /* Done, reset message pointer. */ 1330 sc->sc_flags &= ~SPC_DROP_MSGI; 1331 sc->sc_imlen = 0; 1332 } 1333 1334 /* 1335 * Send the highest priority, scheduled message. 1336 */ 1337 void 1338 mha_msgout(sc) 1339 register struct mha_softc *sc; 1340 { 1341 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE) 1342 struct spc_tinfo *ti; 1343 #endif 1344 int n; 1345 1346 SPC_TRACE(("mha_msgout ")); 1347 1348 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1349 if (sc->sc_omp == sc->sc_omess) { 1350 /* 1351 * This is a retransmission. 1352 * 1353 * We get here if the target stayed in MESSAGE OUT 1354 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1355 * that all of the previously transmitted messages must 1356 * be sent again, in the same order. Therefore, we 1357 * requeue all the previously transmitted messages, and 1358 * start again from the top. Our simple priority 1359 * scheme keeps the messages in the right order. 1360 */ 1361 SPC_MISC(("retransmitting ")); 1362 sc->sc_msgpriq |= sc->sc_msgoutq; 1363 /* 1364 * Set ATN. If we're just sending a trivial 1-byte 1365 * message, we'll clear ATN later on anyway. 1366 */ 1367 CMR = CMD_SET_ATN; /* XXX? */ 1368 } else { 1369 /* This is a continuation of the previous message. */ 1370 n = sc->sc_omp - sc->sc_omess; 1371 goto nextbyte; 1372 } 1373 } 1374 1375 /* No messages transmitted so far. */ 1376 sc->sc_msgoutq = 0; 1377 sc->sc_lastmsg = 0; 1378 1379 nextmsg: 1380 /* Pick up highest priority message. */ 1381 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1382 sc->sc_msgpriq &= ~sc->sc_currmsg; 1383 sc->sc_msgoutq |= sc->sc_currmsg; 1384 1385 /* Build the outgoing message data. */ 1386 switch (sc->sc_currmsg) { 1387 case SEND_IDENTIFY: 1388 SPC_ASSERT(sc->sc_nexus != NULL); 1389 sc->sc_omess[0] = 1390 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1391 n = 1; 1392 break; 1393 1394 #if SPC_USE_SYNCHRONOUS 1395 case SEND_SDTR: 1396 SPC_ASSERT(sc->sc_nexus != NULL); 1397 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1398 sc->sc_omess[4] = MSG_EXTENDED; 1399 sc->sc_omess[3] = 3; 1400 sc->sc_omess[2] = MSG_EXT_SDTR; 1401 sc->sc_omess[1] = ti->period >> 2; 1402 sc->sc_omess[0] = ti->offset; 1403 n = 5; 1404 break; 1405 #endif 1406 1407 #if SPC_USE_WIDE 1408 case SEND_WDTR: 1409 SPC_ASSERT(sc->sc_nexus != NULL); 1410 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1411 sc->sc_omess[3] = MSG_EXTENDED; 1412 sc->sc_omess[2] = 2; 1413 sc->sc_omess[1] = MSG_EXT_WDTR; 1414 sc->sc_omess[0] = ti->width; 1415 n = 4; 1416 break; 1417 #endif 1418 1419 case SEND_DEV_RESET: 1420 sc->sc_flags |= SPC_ABORTING; 1421 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1422 n = 1; 1423 break; 1424 1425 case SEND_REJECT: 1426 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1427 n = 1; 1428 break; 1429 1430 case SEND_PARITY_ERROR: 1431 sc->sc_omess[0] = MSG_PARITY_ERROR; 1432 n = 1; 1433 break; 1434 1435 case SEND_INIT_DET_ERR: 1436 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1437 n = 1; 1438 break; 1439 1440 case SEND_ABORT: 1441 sc->sc_flags |= SPC_ABORTING; 1442 sc->sc_omess[0] = MSG_ABORT; 1443 n = 1; 1444 break; 1445 1446 default: 1447 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1448 sc->sc_dev.dv_xname); 1449 SPC_BREAK(); 1450 sc->sc_omess[0] = MSG_NOOP; 1451 n = 1; 1452 break; 1453 } 1454 sc->sc_omp = &sc->sc_omess[n]; 1455 1456 nextbyte: 1457 /* Send message bytes. */ 1458 /* send TRANSFER command. */ 1459 sc->sc_ps[3] = 1; 1460 sc->sc_ps[4] = n >> 8; 1461 sc->sc_pc[10] = n; 1462 sc->sc_ps[-1] = 0x000F; /* burst */ 1463 asm volatile ("nop"); 1464 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1465 for (;;) { 1466 if ((SSR & SS_BUSY) != 0) 1467 break; 1468 if (SSR & SS_IREQUEST) 1469 goto out; 1470 } 1471 for (;;) { 1472 #if 0 1473 for (;;) { 1474 if ((PSNS & PSNS_REQ) != 0) 1475 break; 1476 /* Wait for REQINIT. XXX Need timeout. */ 1477 } 1478 #endif 1479 if (SSR & SS_IREQUEST) { 1480 /* 1481 * Target left MESSAGE OUT, possibly to reject 1482 * our message. 1483 * 1484 * If this is the last message being sent, then we 1485 * deassert ATN, since either the target is going to 1486 * ignore this message, or it's going to ask for a 1487 * retransmission via MESSAGE PARITY ERROR (in which 1488 * case we reassert ATN anyway). 1489 */ 1490 #if 0 1491 if (sc->sc_msgpriq == 0) 1492 CMR = CMD_RESET_ATN; 1493 #endif 1494 goto out; 1495 } 1496 1497 #if 0 1498 /* Clear ATN before last byte if this is the last message. */ 1499 if (n == 1 && sc->sc_msgpriq == 0) 1500 CMR = CMD_RESET_ATN; 1501 #endif 1502 1503 while ((SSR & SS_DREG_FULL) != 0) 1504 ; 1505 /* Send message byte. */ 1506 sc->sc_pc[0] = *--sc->sc_omp; 1507 --n; 1508 /* Keep track of the last message we've sent any bytes of. */ 1509 sc->sc_lastmsg = sc->sc_currmsg; 1510 1511 if (n == 0) 1512 break; 1513 } 1514 1515 /* We get here only if the entire message has been transmitted. */ 1516 if (sc->sc_msgpriq != 0) { 1517 /* There are more outgoing messages. */ 1518 goto nextmsg; 1519 } 1520 1521 /* 1522 * The last message has been transmitted. We need to remember the last 1523 * message transmitted (in case the target switches to MESSAGE IN phase 1524 * and sends a MESSAGE REJECT), and the list of messages transmitted 1525 * this time around (in case the target stays in MESSAGE OUT phase to 1526 * request a retransmit). 1527 */ 1528 1529 out: 1530 /* Disable REQ/ACK protocol. */ 1531 return; 1532 } 1533 1534 1535 /*************************************************************** 1537 * 1538 * datain/dataout 1539 * 1540 */ 1541 1542 int 1543 mha_datain_pio(sc, p, n) 1544 register struct mha_softc *sc; 1545 u_char *p; 1546 int n; 1547 { 1548 u_short d; 1549 int a; 1550 int total_n = n; 1551 1552 SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n)); 1553 1554 WAIT; 1555 sc->sc_ps[3] = 1; 1556 sc->sc_ps[4] = n >> 8; 1557 sc->sc_pc[10] = n; 1558 /* $BHa$7$-%=%U%HE>Aw(B */ 1559 CMR = CMD_RECEIVE_TO_MPU; 1560 for (;;) { 1561 a = SSR; 1562 if (a & 0x04) { 1563 d = sc->sc_ps[0]; 1564 *p++ = d >> 8; 1565 if (--n > 0) { 1566 *p++ = d; 1567 --n; 1568 } 1569 a = SSR; 1570 } 1571 if (a & 0x40) 1572 continue; 1573 if (a & 0x80) 1574 break; 1575 } 1576 SPC_TRACE(("...%d resd]", n)); 1577 return total_n - n; 1578 } 1579 1580 int 1581 mha_dataout_pio(sc, p, n) 1582 register struct mha_softc *sc; 1583 u_char *p; 1584 int n; 1585 { 1586 u_short d; 1587 int a; 1588 int total_n = n; 1589 1590 SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n)); 1591 1592 WAIT; 1593 sc->sc_ps[3] = 1; 1594 sc->sc_ps[4] = n >> 8; 1595 sc->sc_pc[10] = n; 1596 /* $BHa$7$-%=%U%HE>Aw(B */ 1597 CMR = CMD_SEND_FROM_MPU; 1598 for (;;) { 1599 a = SSR; 1600 if (a & 0x04) { 1601 d = *p++ << 8; 1602 if (--n > 0) { 1603 d |= *p++; 1604 --n; 1605 } 1606 sc->sc_ps[0] = d; 1607 a = SSR; 1608 } 1609 if (a & 0x40) 1610 continue; 1611 if (a & 0x80) 1612 break; 1613 } 1614 SPC_TRACE(("...%d resd]", n)); 1615 return total_n - n; 1616 } 1617 1618 static int 1619 mha_dataio_dma(dw, cw, sc, p, n) 1620 int dw; /* DMA word */ 1621 int cw; /* CMR word */ 1622 register struct mha_softc *sc; 1623 u_char *p; 1624 int n; 1625 { 1626 char *paddr; 1627 1628 if (n > MAXBSIZE) 1629 panic("transfer size exceeds MAXBSIZE"); 1630 if (sc->sc_dmasize > 0) 1631 panic("DMA request while another DMA transfer is in pregress"); 1632 1633 if (cw == CMD_SEND_FROM_DMA) { 1634 memcpy(sc->sc_dmabuf, p, n); 1635 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1636 } else { 1637 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1638 } 1639 sc->sc_p = p; 1640 sc->sc_dmasize = n; 1641 1642 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1643 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1644 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1645 dw &= ~(1 << 3); 1646 #endif 1647 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1648 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1649 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1650 WAIT; 1651 sc->sc_ps[3] = 1; 1652 sc->sc_ps[4] = n >> 8; 1653 sc->sc_pc[10] = n; 1654 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1655 3 ... short bus cycle 1656 2 ... MAXIMUM XFER. 1657 1 ... BURST XFER. 1658 0 ... R/W */ 1659 sc->sc_ps[-1] = dw; /* burst */ 1660 asm volatile ("nop"); 1661 CMR = cw; /* receive to DMA */ 1662 return n; 1663 } 1664 int 1665 mha_dataout(sc, p, n) 1666 register struct mha_softc *sc; 1667 u_char *p; 1668 int n; 1669 { 1670 if (n == 0) 1671 return n; 1672 1673 if (n & 1) 1674 return mha_dataout_pio(sc, p, n); 1675 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1676 } 1677 1678 int 1680 mha_datain(sc, p, n) 1681 register struct mha_softc *sc; 1682 u_char *p; 1683 int n; 1684 { 1685 register struct acb *acb = sc->sc_nexus; 1686 1687 if (n == 0) 1688 return n; 1689 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1690 return mha_datain_pio(sc, p, n); 1691 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1692 } 1693 1694 1696 /* 1697 * Catch an interrupt from the adaptor 1698 */ 1699 /* 1700 * This is the workhorse routine of the driver. 1701 * Deficiencies (for now): 1702 * 1) always uses programmed I/O 1703 */ 1704 int 1705 mhaintr(arg) 1706 void *arg; 1707 { 1708 struct mha_softc *sc = arg; 1709 #if 0 1710 u_char ints; 1711 #endif 1712 struct acb *acb; 1713 u_char ph; 1714 u_short r; 1715 int n; 1716 1717 #if 1 /* XXX called during attach? */ 1718 if (tmpsc != NULL) { 1719 SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc)); 1720 sc = tmpsc; 1721 } else { 1722 #endif 1723 1724 #if 1 /* XXX */ 1725 } 1726 #endif 1727 1728 #if 0 1729 /* 1730 * $B3d$j9~$_6X;_$K$9$k(B 1731 */ 1732 SCTL &= ~SCTL_INTR_ENAB; 1733 #endif 1734 1735 SPC_TRACE(("[mhaintr]")); 1736 1737 /* 1738 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1739 */ 1740 /* 1741 * First check for abnormal conditions, such as reset. 1742 */ 1743 #if 0 1744 #if 1 /* XXX? */ 1745 while (((ints = SSR) & SS_IREQUEST) == 0) 1746 delay(1); 1747 SPC_MISC(("ints = 0x%x ", ints)); 1748 #else /* usually? */ 1749 ints = SSR; 1750 #endif 1751 #endif 1752 while (SSR & SS_IREQUEST) { 1753 acb = sc->sc_nexus; 1754 r = ISCSR; 1755 SPC_MISC(("[r=0x%x]", r)); 1756 switch (r >> 8) { 1757 default: 1758 printf("[addr=%p\n" 1759 "result=0x%x\n" 1760 "cmd=0x%x\n" 1761 "ph=0x%x(ought to be %d)]\n", 1762 &ISCSR, 1763 r, 1764 acb->xs->cmd->opcode, 1765 SCR, sc->sc_phase); 1766 panic("unexpected result."); 1767 case 0x82: /* selection timeout */ 1768 SPC_MISC(("selection timeout ")); 1769 sc->sc_phase = BUSFREE_PHASE; 1770 SPC_ASSERT(sc->sc_nexus != NULL); 1771 acb = sc->sc_nexus; 1772 delay(250); 1773 acb->xs->error = XS_SELTIMEOUT; 1774 mha_done(sc, acb); 1775 continue; /* XXX ??? msaitoh */ 1776 case 0x60: /* command completed */ 1777 sc->sc_spcinitialized++; 1778 if (sc->sc_phase == BUSFREE_PHASE) 1779 continue; 1780 ph = SCR; 1781 if (ph & PSNS_ACK) { 1782 int s; 1783 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1784 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1785 ph & PHASE_MASK, sc->sc_phase)); 1786 #if 0 1787 /* switch (sc->sc_phase) {*/ 1788 #else 1789 switch (ph & PHASE_MASK) { 1790 #endif 1791 case STATUS_PHASE: 1792 if (sc->sc_state != SPC_HASNEXUS) 1793 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1794 sc->sc_state); 1795 SPC_ASSERT(sc->sc_nexus != NULL); 1796 acb = sc->sc_nexus; 1797 WAIT; 1798 s = MBR; 1799 SPC_ASSERT(s == 1); 1800 acb->stat = sc->sc_pcx[0]; /* XXX */ 1801 SPC_MISC(("stat=0x%02x ", acb->stat)); 1802 sc->sc_prevphase = STATUS_PHASE; 1803 break; 1804 case MESSAGE_IN_PHASE: 1805 mha_msgin(sc); 1806 sc->sc_prevphase = MESSAGE_IN_PHASE; 1807 /* thru */ 1808 case DATA_IN_PHASE: 1809 if (sc->sc_dmasize == 0) 1810 break; 1811 bus_dmamap_sync(sc->sc_dmat, 1812 sc->sc_dmamap, 1813 0, sc->sc_dmasize, 1814 BUS_DMASYNC_POSTREAD); 1815 memcpy(sc->sc_p, sc->sc_dmabuf, 1816 sc->sc_dmasize); 1817 sc->sc_dmasize = 0; 1818 break; 1819 case DATA_OUT_PHASE: 1820 if (sc->sc_dmasize == 0) 1821 break; 1822 bus_dmamap_sync(sc->sc_dmat, 1823 sc->sc_dmamap, 1824 0, sc->sc_dmasize, 1825 BUS_DMASYNC_POSTWRITE); 1826 sc->sc_dmasize = 0; 1827 break; 1828 } 1829 WAIT; 1830 CMR = CMD_RESET_ACK; /* reset ack */ 1831 /*mha_done(sc, acb); XXX */ 1832 continue; 1833 } else if (NSR & 0x80) { /* nexus */ 1834 #if 1 1835 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1836 sc->sc_state = SPC_HASNEXUS; 1837 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1838 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1839 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1840 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1841 WAIT; 1842 if (SSR & SS_IREQUEST) 1843 continue; 1844 switch (sc->sc_phase) { 1845 default: 1846 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1847 case MESSAGE_IN_PHASE: 1848 /* $B2?$b$7$J$$(B */ 1849 continue; 1850 case STATUS_PHASE: 1851 sc->sc_phase = MESSAGE_IN_PHASE; 1852 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1853 continue; 1854 case DATA_IN_PHASE: 1855 sc->sc_prevphase = DATA_IN_PHASE; 1856 if (sc->sc_dleft == 0) { 1857 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1858 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1859 sc->sc_phase = STATUS_PHASE; 1860 CMR = CMD_RECEIVE_STS; /* receive sts */ 1861 continue; 1862 } 1863 n = mha_datain(sc, sc->sc_dp, 1864 sc->sc_dleft); 1865 sc->sc_dp += n; 1866 sc->sc_dleft -= n; 1867 continue; 1868 case DATA_OUT_PHASE: 1869 sc->sc_prevphase = DATA_OUT_PHASE; 1870 if (sc->sc_dleft == 0) { 1871 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1872 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1873 sc->sc_phase = STATUS_PHASE; 1874 CMR = CMD_RECEIVE_STS; /* receive sts */ 1875 continue; 1876 } 1877 /* data phase $B$NB3$-$r$d$m$&(B */ 1878 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1879 sc->sc_dp += n; 1880 sc->sc_dleft -= n; 1881 continue; 1882 case COMMAND_PHASE: 1883 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1884 if (acb->dleft) { 1885 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1886 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1887 sc->sc_phase = DATA_IN_PHASE; 1888 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1889 sc->sc_dp += n; 1890 sc->sc_dleft -= n; 1891 } 1892 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1893 sc->sc_phase = DATA_OUT_PHASE; 1894 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1895 sc->sc_dp += n; 1896 sc->sc_dleft -= n; 1897 } 1898 continue; 1899 } 1900 else { 1901 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1902 WAIT; 1903 sc->sc_phase = STATUS_PHASE; 1904 CMR = CMD_RECEIVE_STS; /* receive sts */ 1905 continue; 1906 } 1907 } 1908 #endif 1909 } 1910 continue; 1911 case 0x31: /* disconnected in xfer progress. */ 1912 SPC_MISC(("[0x31]")); 1913 case 0x70: /* disconnected. */ 1914 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1915 sc->sc_phase = BUSFREE_PHASE; 1916 sc->sc_state = SPC_IDLE; 1917 #if 1 1918 acb = sc->sc_nexus; 1919 SPC_ASSERT(sc->sc_nexus != NULL); 1920 acb->xs->error = XS_NOERROR; 1921 mha_done(sc, acb); 1922 #else 1923 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1924 mha_sched(sc); 1925 #endif 1926 continue; 1927 case 0x32: /* phase error in xfer progress. */ 1928 SPC_MISC(("[0x32]")); 1929 #if 0 1930 case 0x65: /* invalid command. 1931 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1932 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1933 #if 1 1934 SPC_MISC(("[0x%04x]", r)); 1935 #endif 1936 #endif 1937 case 0x54: /* initial-phase error. */ 1938 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1939 NSR, 1940 SCR, sc->sc_phase)); 1941 /* thru */ 1942 case 0x71: /* assert req */ 1943 WAIT; 1944 if (SSR & 0x40) { 1945 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1946 SSR, r, NSR, SCR); 1947 WAIT; 1948 } 1949 ph = SCR; 1950 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1951 sc->sc_state = SPC_HASNEXUS; 1952 } 1953 if (ph & 0x80) { 1954 switch (ph & PHASE_MASK) { 1955 default: 1956 printf("phase = %x\n", ph); 1957 panic("assert req: the phase I don't know!"); 1958 case DATA_IN_PHASE: 1959 sc->sc_prevphase = DATA_IN_PHASE; 1960 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1961 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1962 sc->sc_dp += n; 1963 sc->sc_dleft -= n; 1964 SPC_MISC(("done\n")); 1965 continue; 1966 case DATA_OUT_PHASE: 1967 sc->sc_prevphase = DATA_OUT_PHASE; 1968 SPC_MISC(("DATAOUT\n")); 1969 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1970 sc->sc_dp += n; 1971 sc->sc_dleft -= n; 1972 continue; 1973 case STATUS_PHASE: 1974 sc->sc_phase = STATUS_PHASE; 1975 SPC_MISC(("[RECV_STS]")); 1976 WAIT; 1977 CMR = CMD_RECEIVE_STS; /* receive sts */ 1978 continue; 1979 case MESSAGE_IN_PHASE: 1980 sc->sc_phase = MESSAGE_IN_PHASE; 1981 WAIT; 1982 CMR = CMD_RECEIVE_MSG; 1983 continue; 1984 } 1985 } 1986 continue; 1987 } 1988 } 1989 1990 return 1; 1991 } 1992 1993 void 1994 mha_abort(sc, acb) 1995 struct mha_softc *sc; 1996 struct acb *acb; 1997 { 1998 acb->flags |= ACB_ABORTED; 1999 2000 if (acb == sc->sc_nexus) { 2001 /* 2002 * If we're still selecting, the message will be scheduled 2003 * after selection is complete. 2004 */ 2005 if (sc->sc_state == SPC_HASNEXUS) { 2006 sc->sc_flags |= SPC_ABORTING; 2007 mha_sched_msgout(SEND_ABORT); 2008 } 2009 } else { 2010 if (sc->sc_state == SPC_IDLE) 2011 mha_sched(sc); 2012 } 2013 } 2014 2015 void 2016 mha_timeout(arg) 2017 void *arg; 2018 { 2019 int s = splbio(); 2020 struct acb *acb = (struct acb *)arg; 2021 struct scsipi_xfer *xs = acb->xs; 2022 struct scsipi_periph *periph = xs->xs_periph; 2023 struct mha_softc *sc = 2024 (void*)periph->periph_channel->chan_adapter->adapt_dev; 2025 2026 scsipi_printaddr(periph); 2027 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2028 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2029 sc->sc_dev.dv_xname, 2030 acb, acb->flags, acb->dleft, acb->stat, 2031 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2032 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2033 ); 2034 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2035 panic("timeout, ouch!"); 2036 2037 if (acb->flags & ACB_ABORTED) { 2038 /* abort timed out */ 2039 printf(" AGAIN\n"); 2040 #if 0 2041 mha_init(sc, 1); /* XXX 1?*/ 2042 #endif 2043 } else { 2044 /* abort the operation that has timed out */ 2045 printf("\n"); 2046 xs->error = XS_TIMEOUT; 2047 mha_abort(sc, acb); 2048 } 2049 2050 splx(s); 2051 } 2052 2053 #if SPC_DEBUG 2055 /* 2056 * The following functions are mostly used for debugging purposes, either 2057 * directly called from the driver or from the kernel debugger. 2058 */ 2059 2060 void 2061 mha_show_scsi_cmd(acb) 2062 struct acb *acb; 2063 { 2064 u_char *b = (u_char *)&acb->cmd; 2065 struct scsipi_periph *periph = acb->xs->xs_periph; 2066 int i; 2067 2068 scsipi_printaddr(periph); 2069 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2070 for (i = 0; i < acb->clen; i++) { 2071 if (i) 2072 printf(","); 2073 printf("%x", b[i]); 2074 } 2075 printf("\n"); 2076 } else 2077 printf("RESET\n"); 2078 } 2079 2080 void 2081 mha_print_acb(acb) 2082 struct acb *acb; 2083 { 2084 2085 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2086 printf(" dp=%p dleft=%d stat=%x\n", 2087 acb->daddr, acb->dleft, acb->stat); 2088 mha_show_scsi_cmd(acb); 2089 } 2090 2091 void 2092 mha_print_active_acb() 2093 { 2094 struct acb *acb; 2095 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2096 2097 printf("ready list:\n"); 2098 for (acb = sc->ready_list.tqh_first; acb != NULL; 2099 acb = acb->chain.tqe_next) 2100 mha_print_acb(acb); 2101 printf("nexus:\n"); 2102 if (sc->sc_nexus != NULL) 2103 mha_print_acb(sc->sc_nexus); 2104 printf("nexus list:\n"); 2105 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2106 acb = acb->chain.tqe_next) 2107 mha_print_acb(acb); 2108 } 2109 2110 void 2111 mha_dump_driver(sc) 2112 struct mha_softc *sc; 2113 { 2114 struct spc_tinfo *ti; 2115 int i; 2116 2117 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2118 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2119 sc->sc_state, sc->sc_imess[0], 2120 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2121 for (i = 0; i < 7; i++) { 2122 ti = &sc->sc_tinfo[i]; 2123 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2124 i, ti->cmds, ti->dconns, ti->touts); 2125 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2126 } 2127 } 2128 #endif 2129
Indexes created Sat Oct 18 08:10:09 GMT 2025