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mha.c revision 1.49
      1 /*	$NetBSD: mha.c,v 1.49 2008/11/29 05:59:40 isaki Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996-1999 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and
      9  * Minoura Makoto.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31 */
     32 
     33 /*-
     34  * Copyright (c) 1994 Jarle Greipsland
     35  * All rights reserved.
     36  *
     37  * Redistribution and use in source and binary forms, with or without
     38  * modification, are permitted provided that the following conditions
     39  * are met:
     40  * 1. Redistributions of source code must retain the above copyright
     41  *    notice, this list of conditions and the following disclaimer.
     42  * 2. Redistributions in binary form must reproduce the above copyright
     43  *    notice, this list of conditions and the following disclaimer in the
     44  *    documentation and/or other materials provided with the distribution.
     45  * 3. The name of the author may not be used to endorse or promote products
     46  *    derived from this software without specific prior written permission.
     47  *
     48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     50  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     51  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     52  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     53  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     54  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     55  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     56  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     57  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     58  * POSSIBILITY OF SUCH DAMAGE.
     59  */
     60 
     61 #include <sys/cdefs.h>
     62 __KERNEL_RCSID(0, "$NetBSD: mha.c,v 1.49 2008/11/29 05:59:40 isaki Exp $");
     63 
     64 #include "opt_ddb.h"
     65 
     66 /* Synchronous data transfers? */
     67 #define SPC_USE_SYNCHRONOUS	0
     68 #define SPC_SYNC_REQ_ACK_OFS 	8
     69 
     70 /* Default DMA mode? */
     71 #define MHA_DMA_LIMIT_XFER	1
     72 #define MHA_DMA_BURST_XFER	1
     73 #define MHA_DMA_SHORT_BUS_CYCLE	1
     74 
     75 #define MHA_DMA_DATAIN	(0 | (MHA_DMA_LIMIT_XFER << 1)		\
     76 			   | (MHA_DMA_BURST_XFER << 2)		\
     77 			   | (MHA_DMA_SHORT_BUS_CYCLE << 3))
     78 #define MHA_DMA_DATAOUT	(1 | (MHA_DMA_LIMIT_XFER << 1)		\
     79 			   | (MHA_DMA_BURST_XFER << 2)		\
     80 			   | (MHA_DMA_SHORT_BUS_CYCLE << 3))
     81 
     82 /* Include debug functions?  At the end of this file there are a bunch of
     83  * functions that will print out various information regarding queued SCSI
     84  * commands, driver state and chip contents.  You can call them from the
     85  * kernel debugger.  If you set SPC_DEBUG to 0 they are not included (the
     86  * kernel uses less memory) but you lose the debugging facilities.
     87  */
     88 #define SPC_DEBUG		0
     89 
     90 /* End of customizable parameters */
     91 
     92 /*
     93  * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2
     94  */
     95 
     96 #include <sys/types.h>
     97 #include <sys/param.h>
     98 #include <sys/systm.h>
     99 #include <sys/kernel.h>
    100 #include <sys/errno.h>
    101 #include <sys/ioctl.h>
    102 #include <sys/device.h>
    103 #include <sys/buf.h>
    104 #include <sys/proc.h>
    105 #include <sys/user.h>
    106 #include <sys/queue.h>
    107 
    108 #include <machine/bus.h>
    109 
    110 #include <dev/scsipi/scsi_spc.h>
    111 #include <dev/scsipi/scsi_all.h>
    112 #include <dev/scsipi/scsipi_all.h>
    113 #include <dev/scsipi/scsi_message.h>
    114 #include <dev/scsipi/scsiconf.h>
    115 
    116 #include <x68k/x68k/iodevice.h>
    117 #include <x68k/dev/mb86601reg.h>
    118 #include <x68k/dev/mhavar.h>
    119 #include <x68k/dev/intiovar.h>
    120 #include <x68k/dev/scsiromvar.h>
    121 
    122 #if 0
    123 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}}
    124 #else
    125 #define WAIT {while (sc->sc_pc[2] & 0x40);}
    126 #endif
    127 
    128 #define SSR	(sc->sc_pc[2])
    129 #define	SS_IREQUEST	0x80
    130 #define	SS_BUSY		0x40
    131 #define	SS_DREG_FULL	0x02
    132 
    133 #define	NSR	(sc->sc_pc[3])
    134 
    135 #define	SIR	(sc->sc_pc[4])
    136 
    137 #define	CMR	(sc->sc_pc[5])
    138 #define	CMD_SEL_AND_CMD	0x00
    139 #define	CMD_SELECT	0x09
    140 #define	CMD_SET_ATN	0x0a
    141 #define	CMD_RESET_ATN	0x0b
    142 #define	CMD_RESET_ACK	0x0d
    143 #define	CMD_SEND_FROM_MPU	0x10
    144 #define	CMD_SEND_FROM_DMA	0x11
    145 #define	CMD_RECEIVE_TO_MPU	0x12
    146 #define	CMD_RECEIVE_TO_DMA	0x13
    147 #define	CMD_RECEIVE_MSG	0x1a
    148 #define	CMD_RECEIVE_STS	0x1c
    149 #define	CMD_SOFT_RESET	0x40
    150 #define	CMD_SCSI_RESET	0x42
    151 #define	CMD_SET_UP_REG	0x43
    152 
    153 #define	SCR	(sc->sc_pc[11])
    154 
    155 #define	TMR	(sc->sc_pc[12])
    156 #define	TM_SYNC		0x80
    157 #define	TM_ASYNC	0x00
    158 
    159 #define	WAR	(sc->sc_pc[15])
    160 #define	WA_MCSBUFWIN	0x00
    161 #define	WA_UPMWIN	0x80
    162 #define	WA_INITWIN	0xc0
    163 
    164 #define	MBR	(sc->sc_pc[15])
    165 
    166 #define ISCSR	(sc->sc_ps[2])
    167 
    168 #define	CCR	(sc->sc_pcx[0])
    169 #define	OIR	(sc->sc_pcx[1])
    170 #define	AMR	(sc->sc_pcx[2])
    171 #define	SMR	(sc->sc_pcx[3])
    172 #define	SRR	(sc->sc_pcx[4])
    173 #define	STR	(sc->sc_pcx[5])
    174 #define	RTR	(sc->sc_pcx[6])
    175 #define	ATR	(sc->sc_pcx[7])
    176 #define	PER	(sc->sc_pcx[8])
    177 #define	IER	(sc->sc_pcx[9])
    178 #define	IE_ALL	0xBF
    179 
    180 #define	GLR	(sc->sc_pcx[10])
    181 #define	DMR	(sc->sc_pcx[11])
    182 #define	IMR	(sc->sc_pcx[12])
    183 
    184 #ifndef DDB
    185 #define	Debugger() panic("should call debugger here (mha.c)")
    186 #endif /* ! DDB */
    187 
    188 
    189 #if SPC_DEBUG
    190 #define SPC_SHOWACBS	0x01
    191 #define SPC_SHOWINTS	0x02
    192 #define SPC_SHOWCMDS	0x04
    193 #define SPC_SHOWMISC	0x08
    194 #define SPC_SHOWTRAC	0x10
    195 #define SPC_SHOWSTART	0x20
    196 #define SPC_SHOWPHASE	0x40
    197 #define SPC_SHOWDMA	0x80
    198 #define SPC_SHOWCCMDS	0x100
    199 #define SPC_SHOWMSGS	0x200
    200 #define SPC_DOBREAK	0x400
    201 
    202 int mha_debug =
    203 #if 0
    204 0x7FF;
    205 #else
    206 SPC_SHOWSTART|SPC_SHOWTRAC;
    207 #endif
    208 
    209 
    210 #define SPC_ACBS(str)  do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0)
    211 #define SPC_MISC(str)  do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0)
    212 #define SPC_INTS(str)  do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0)
    213 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0)
    214 #define SPC_CMDS(str)  do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0)
    215 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0)
    216 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0)
    217 #define SPC_DMA(str)   do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0)
    218 #define SPC_MSGS(str)  do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0)
    219 #define	SPC_BREAK()    do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0)
    220 #define	SPC_ASSERT(x)  do {if (x) {} else {printf("%s at line %d: assertion failed\n", device_xname(sc->sc_dev), __LINE__); Debugger();}} while (0)
    221 #else
    222 #define SPC_ACBS(str)
    223 #define SPC_MISC(str)
    224 #define SPC_INTS(str)
    225 #define SPC_TRACE(str)
    226 #define SPC_CMDS(str)
    227 #define SPC_START(str)
    228 #define SPC_PHASE(str)
    229 #define SPC_DMA(str)
    230 #define SPC_MSGS(str)
    231 #define	SPC_BREAK()
    232 #define	SPC_ASSERT(x)
    233 #endif
    234 
    235 int	mhamatch(device_t, cfdata_t, void *);
    236 void	mhaattach(device_t, device_t, void *);
    237 void	mhaselect(struct mha_softc *, u_char, u_char, u_char *, u_char);
    238 void	mha_scsi_reset(struct mha_softc *);
    239 void	mha_reset(struct mha_softc *);
    240 void	mha_free_acb(struct mha_softc *, struct acb *, int);
    241 void	mha_sense(struct mha_softc *, struct acb *);
    242 void	mha_msgin(struct mha_softc *);
    243 void	mha_msgout(struct mha_softc *);
    244 int	mha_dataout_pio(struct mha_softc *, u_char *, int);
    245 int	mha_datain_pio(struct mha_softc *, u_char *, int);
    246 int	mha_dataout(struct mha_softc *, u_char *, int);
    247 int	mha_datain(struct mha_softc *, u_char *, int);
    248 void	mha_abort(struct mha_softc *, struct acb *);
    249 void 	mha_init(struct mha_softc *);
    250 void	mha_scsi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *);
    251 void	mha_poll(struct mha_softc *, struct acb *);
    252 void	mha_sched(struct mha_softc *);
    253 void	mha_done(struct mha_softc *, struct acb *);
    254 int	mhaintr(void *);
    255 void	mha_timeout(void *);
    256 void	mha_minphys(struct buf *);
    257 void	mha_dequeue(struct mha_softc *, struct acb *);
    258 inline void	mha_setsync(struct mha_softc *, struct spc_tinfo *);
    259 #if SPC_DEBUG
    260 void	mha_print_acb(struct acb *);
    261 void	mha_show_scsi_cmd(struct acb *);
    262 void	mha_print_active_acb(void);
    263 void	mha_dump_driver(struct mha_softc *);
    264 #endif
    265 
    266 static int mha_dataio_dma(int, int, struct mha_softc *, u_char *, int);
    267 
    268 CFATTACH_DECL_NEW(mha, sizeof(struct mha_softc),
    269     mhamatch, mhaattach, NULL, NULL);
    270 
    271 extern struct cfdriver mha_cd;
    272 
    273 /*
    274  * returns non-zero value if a controller is found.
    275  */
    276 int
    277 mhamatch(device_t parent, cfdata_t cf, void *aux)
    278 {
    279 	struct intio_attach_args *ia = aux;
    280 	bus_space_tag_t iot = ia->ia_bst;
    281 	bus_space_handle_t ioh;
    282 
    283 	ia->ia_size=0x20;
    284 	if (ia->ia_addr != 0xea0000)
    285 		return 0;
    286 
    287 	if (intio_map_allocate_region(device_parent(parent), ia,
    288 				      INTIO_MAP_TESTONLY) < 0) /* FAKE */
    289 		return 0;
    290 
    291 	if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED,
    292 			  &ioh) < 0)
    293 		return 0;
    294 	if (!badaddr(INTIO_ADDR(ia->ia_addr + 0)))
    295 		return 0;
    296 	bus_space_unmap(iot, ioh, 0x20);
    297 
    298 	return 1;
    299 }
    300 
    301 /*
    302  */
    303 
    304 struct mha_softc *tmpsc;
    305 
    306 void
    307 mhaattach(device_t parent, device_t self, void *aux)
    308 {
    309 	struct mha_softc *sc = device_private(self);
    310 	struct intio_attach_args *ia = aux;
    311 
    312 	tmpsc = sc;	/* XXX */
    313 	sc->sc_dev = self;
    314 
    315 	aprint_normal(": Mankai Mach-2 Fast SCSI Host Adaptor\n");
    316 
    317 	SPC_TRACE(("mhaattach  "));
    318 	sc->sc_state = SPC_INIT;
    319 	sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */
    320 	intio_map_allocate_region(device_parent(parent), ia, INTIO_MAP_ALLOCATE);
    321 				/* XXX: FAKE  */
    322 	sc->sc_dmat = ia->ia_dmat;
    323 
    324 	sc->sc_pc = (volatile u_char *)sc->sc_iobase;
    325 	sc->sc_ps = (volatile u_short *)sc->sc_iobase;
    326 	sc->sc_pcx = &sc->sc_pc[0x10];
    327 
    328 	sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */
    329 
    330 	intio_intr_establish(ia->ia_intr, "mha", mhaintr, sc);
    331 
    332 	mha_init(sc);	/* Init chip and driver */
    333 
    334 	mha_scsi_reset(sc);	/* XXX: some devices need this. */
    335 
    336 	sc->sc_phase  = BUSFREE_PHASE;
    337 
    338 	/*
    339 	 * Fill in the adapter.
    340 	 */
    341 	sc->sc_adapter.adapt_dev = sc->sc_dev;
    342 	sc->sc_adapter.adapt_nchannels = 1;
    343 	sc->sc_adapter.adapt_openings = 7;
    344 	sc->sc_adapter.adapt_max_periph = 1;
    345 	sc->sc_adapter.adapt_ioctl = NULL;
    346 	sc->sc_adapter.adapt_minphys = mha_minphys;
    347 	sc->sc_adapter.adapt_request = mha_scsi_request;
    348 
    349 	sc->sc_channel.chan_adapter = &sc->sc_adapter;
    350 	sc->sc_channel.chan_bustype = &scsi_bustype;
    351 	sc->sc_channel.chan_channel = 0;
    352 	sc->sc_channel.chan_ntargets = 8;
    353 	sc->sc_channel.chan_nluns = 8;
    354 	sc->sc_channel.chan_id = sc->sc_id;
    355 
    356 	sc->sc_spcinitialized = 0;
    357 	WAR = WA_INITWIN;
    358 #if 1
    359 	CCR = 0x14;
    360 	OIR = sc->sc_id;
    361 	AMR = 0x00;
    362 	SMR = 0x00;
    363 	SRR = 0x00;
    364 	STR = 0x20;
    365 	RTR = 0x40;
    366 	ATR = 0x01;
    367 	PER = 0xc9;
    368 #endif
    369 	IER = IE_ALL;	/* $B$9$Y$F$N3d$j9~$_$r5v2D(B */
    370 #if 1
    371 	GLR = 0x00;
    372 	DMR = 0x30;
    373 	IMR = 0x00;
    374 #endif
    375 	WAR = WA_MCSBUFWIN;
    376 
    377 	/* drop off */
    378 	while (SSR & SS_IREQUEST) {
    379 		(void) ISCSR;
    380 	}
    381 
    382 	CMR = CMD_SET_UP_REG;	/* setup reg cmd. */
    383 
    384 	SPC_TRACE(("waiting for intr..."));
    385 	while (!(SSR & SS_IREQUEST))
    386 		delay(10);
    387 	mhaintr(sc);
    388 
    389 	tmpsc = NULL;
    390 
    391 	config_found(self, &sc->sc_channel, scsiprint);
    392 }
    393 
    394 #if 0
    395 void
    396 mha_reset(struct mha_softc *sc)
    397 {
    398 	u_short	dummy;
    399 printf("reset...");
    400 	CMR = CMD_SOFT_RESET;
    401 	__asm volatile ("nop");	/* XXX wait (4clk in 20 MHz) ??? */
    402 	dummy = sc->sc_ps[-1];
    403 	dummy = sc->sc_ps[-1];
    404 	dummy = sc->sc_ps[-1];
    405 	dummy = sc->sc_ps[-1];
    406 	__asm volatile ("nop");
    407 	CMR = CMD_SOFT_RESET;
    408 	sc->sc_spcinitialized = 0;
    409 	CMR = CMD_SET_UP_REG;	/* setup reg cmd. */
    410 	while(!sc->sc_spcinitialized);
    411 
    412 	sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */
    413 printf("done.\n");
    414 }
    415 #endif
    416 
    417 /*
    418  * Pull the SCSI RST line for 500us.
    419  */
    420 void
    421 mha_scsi_reset(struct mha_softc *sc)
    422 {
    423 
    424 	CMR = CMD_SCSI_RESET;	/* SCSI RESET */
    425 	while (!(SSR&SS_IREQUEST))
    426 		delay(10);
    427 }
    428 
    429 /*
    430  * Initialize mha SCSI driver.
    431  */
    432 void
    433 mha_init(struct mha_softc *sc)
    434 {
    435 	struct acb *acb;
    436 	int r;
    437 
    438 	if (sc->sc_state == SPC_INIT) {
    439 		/* First time through; initialize. */
    440 		TAILQ_INIT(&sc->ready_list);
    441 		TAILQ_INIT(&sc->nexus_list);
    442 		TAILQ_INIT(&sc->free_list);
    443 		sc->sc_nexus = NULL;
    444 		acb = sc->sc_acb;
    445 		memset(acb, 0, sizeof(sc->sc_acb));
    446 		for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) {
    447 			TAILQ_INSERT_TAIL(&sc->free_list, acb, chain);
    448 			acb++;
    449 		}
    450 		memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
    451 
    452 		r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0,
    453 				     sc->sc_dmaseg, 1, &sc->sc_ndmasegs,
    454 				     BUS_DMA_NOWAIT);
    455 		if (r)
    456 			panic("mha_init: cannot allocate DMA memory");
    457 		if (sc->sc_ndmasegs != 1)
    458 			panic("mha_init: number of segment > 1??");
    459 		r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs,
    460 				   MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT);
    461 		if (r)
    462 			panic("mha_init: cannot map DMA memory");
    463 		r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1,
    464 				      MAXBSIZE, 0, BUS_DMA_NOWAIT,
    465 				      &sc->sc_dmamap);
    466 		if (r)
    467 			panic("mha_init: cannot create dmamap structure");
    468 		r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
    469 				    sc->sc_dmabuf, MAXBSIZE, NULL,
    470 				    BUS_DMA_NOWAIT);
    471 		if (r)
    472 			panic("mha_init: cannot load DMA buffer into dmamap");
    473 		sc->sc_p = 0;
    474 	} else {
    475 		/* Cancel any active commands. */
    476 		sc->sc_flags |= SPC_ABORTING;
    477 		sc->sc_state = SPC_IDLE;
    478 		if ((acb = sc->sc_nexus) != NULL) {
    479 			acb->xs->error = XS_DRIVER_STUFFUP;
    480 			mha_done(sc, acb);
    481 		}
    482 		while ((acb = sc->nexus_list.tqh_first) != NULL) {
    483 			acb->xs->error = XS_DRIVER_STUFFUP;
    484 			mha_done(sc, acb);
    485 		}
    486 	}
    487 
    488 	sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
    489 	for (r = 0; r < 8; r++) {
    490 		struct spc_tinfo *ti = &sc->sc_tinfo[r];
    491 
    492 		ti->flags = 0;
    493 #if SPC_USE_SYNCHRONOUS
    494 		ti->flags |= T_SYNCMODE;
    495 		ti->period = sc->sc_minsync;
    496 		ti->offset = SPC_SYNC_REQ_ACK_OFS;
    497 #else
    498 		ti->period = ti->offset = 0;
    499 #endif
    500 		ti->width = 0;
    501 	}
    502 
    503 	sc->sc_state = SPC_IDLE;
    504 }
    505 
    506 void
    507 mha_free_acb(struct mha_softc *sc, struct acb *acb, int flags)
    508 {
    509 	int s;
    510 
    511 	s = splbio();
    512 
    513 	acb->flags = 0;
    514 	TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
    515 
    516 	/*
    517 	 * If there were none, wake anybody waiting for one to come free,
    518 	 * starting with queued entries.
    519 	 */
    520 	if (acb->chain.tqe_next == 0)
    521 		wakeup(&sc->free_list);
    522 
    523 	splx(s);
    524 }
    525 
    526 /*
    527  * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
    528  */
    529 
    530 /*
    531  * Expected sequence:
    532  * 1) Command inserted into ready list
    533  * 2) Command selected for execution
    534  * 3) Command won arbitration and has selected target device
    535  * 4) Send message out (identify message, eventually also sync.negotiations)
    536  * 5) Send command
    537  * 5a) Receive disconnect message, disconnect.
    538  * 5b) Reselected by target
    539  * 5c) Receive identify message from target.
    540  * 6) Send or receive data
    541  * 7) Receive status
    542  * 8) Receive message (command complete etc.)
    543  * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd.
    544  *    Repeat 2-8 (no disconnects please...)
    545  */
    546 
    547 /*
    548  * Start a selection.  This is used by mha_sched() to select an idle target,
    549  * and by mha_done() to immediately reselect a target to get sense information.
    550  */
    551 void
    552 mhaselect(struct mha_softc *sc, u_char target, u_char lun, u_char *cmd,
    553     u_char clen)
    554 {
    555 	int i;
    556 	int s;
    557 
    558 	s = splbio();	/* XXX */
    559 
    560 	SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd));
    561 
    562 	/* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */
    563 	/* Now the command into the FIFO */
    564 	WAIT;
    565 #if 1
    566 	SPC_MISC(("[cmd:"));
    567 	for (i = 0; i < clen; i++) {
    568 		unsigned c = cmd[i];
    569 		if (i == 1)
    570 			c |= lun << 5;
    571 		SPC_MISC((" %02x", c));
    572 		sc->sc_pcx[i] = c;
    573 	}
    574 	SPC_MISC(("], target=%d\n", target));
    575 #else
    576 	memcpy(sc->sc_pcx, cmd, clen);
    577 #endif
    578 	if (NSR & 0x80)
    579 		panic("scsistart: already selected...");
    580 	sc->sc_phase  = COMMAND_PHASE;
    581 
    582 	/* new state ASP_SELECTING */
    583 	sc->sc_state = SPC_SELECTING;
    584 
    585 	SIR = target;
    586 #if 0
    587 	CMR = CMD_SELECT;
    588 #else
    589 	CMR = CMD_SEL_AND_CMD;	/* select & cmd */
    590 #endif
    591 	splx(s);
    592 }
    593 
    594 #if 0
    595 int
    596 mha_reselect(struct mha_softc *sc, u_char message)
    597 {
    598 	u_char selid, target, lun;
    599 	struct acb *acb;
    600 	struct scsipi_periph *periph;
    601 	struct spc_tinfo *ti;
    602 
    603 	/*
    604 	 * The SCSI chip made a snapshot of the data bus while the reselection
    605 	 * was being negotiated.  This enables us to determine which target did
    606 	 * the reselect.
    607 	 */
    608 	selid = sc->sc_selid & ~(1 << sc->sc_id);
    609 	if (selid & (selid - 1)) {
    610 		printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n",
    611 		    device_xname(sc->sc_dev), selid);
    612 		SPC_BREAK();
    613 		goto reset;
    614 	}
    615 
    616 	/*
    617 	 * Search wait queue for disconnected cmd
    618 	 * The list should be short, so I haven't bothered with
    619 	 * any more sophisticated structures than a simple
    620 	 * singly linked list.
    621 	 */
    622 	target = ffs(selid) - 1;
    623 	lun = message & 0x07;
    624 	for (acb = sc->nexus_list.tqh_first; acb != NULL;
    625 	     acb = acb->chain.tqe_next) {
    626 		periph = acb->xs->xs_periph;
    627 		if (periph->periph_target == target &&
    628 		    periph->periph_lun == lun)
    629 			break;
    630 	}
    631 	if (acb == NULL) {
    632 		printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n",
    633 		    device_xname(sc->sc_dev), target, lun);
    634 		SPC_BREAK();
    635 		goto abort;
    636 	}
    637 
    638 	/* Make this nexus active again. */
    639 	TAILQ_REMOVE(&sc->nexus_list, acb, chain);
    640 	sc->sc_state = SPC_HASNEXUS;
    641 	sc->sc_nexus = acb;
    642 	ti = &sc->sc_tinfo[target];
    643 	ti->lubusy |= (1 << lun);
    644 	mha_setsync(sc, ti);
    645 
    646 	if (acb->flags & ACB_RESET)
    647 		mha_sched_msgout(sc, SEND_DEV_RESET);
    648 	else if (acb->flags & ACB_ABORTED)
    649 		mha_sched_msgout(sc, SEND_ABORT);
    650 
    651 	/* Do an implicit RESTORE POINTERS. */
    652 	sc->sc_dp = acb->daddr;
    653 	sc->sc_dleft = acb->dleft;
    654 	sc->sc_cp = (u_char *)&acb->cmd;
    655 	sc->sc_cleft = acb->clen;
    656 
    657 	return (0);
    658 
    659 reset:
    660 	mha_sched_msgout(sc, SEND_DEV_RESET);
    661 	return (1);
    662 
    663 abort:
    664 	mha_sched_msgout(sc, SEND_ABORT);
    665 	return (1);
    666 }
    667 #endif
    668 /*
    669  * Start a SCSI-command
    670  * This function is called by the higher level SCSI-driver to queue/run
    671  * SCSI-commands.
    672  */
    673 void
    674 mha_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
    675     void *arg)
    676 {
    677 	struct scsipi_xfer *xs;
    678 	struct scsipi_periph *periph;
    679 	struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev;
    680 	struct acb *acb;
    681 	int s, flags;
    682 
    683 	switch (req) {
    684 	case ADAPTER_REQ_RUN_XFER:
    685 		xs = arg;
    686 		periph = xs->xs_periph;
    687 
    688 		SPC_TRACE(("[mha_scsi_cmd] "));
    689 		SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
    690 		    periph->periph_target));
    691 
    692 		flags = xs->xs_control;
    693 
    694 		/* Get a mha command block */
    695 		s = splbio();
    696 		acb = sc->free_list.tqh_first;
    697 		if (acb) {
    698 			TAILQ_REMOVE(&sc->free_list, acb, chain);
    699 			ACB_SETQ(acb, ACB_QNONE);
    700 		}
    701 
    702 		if (acb == NULL) {
    703 			xs->error = XS_RESOURCE_SHORTAGE;
    704 			scsipi_done(xs);
    705 			splx(s);
    706 			return;
    707 		}
    708 		splx(s);
    709 
    710 		/* Initialize acb */
    711 		acb->xs = xs;
    712 		memcpy(&acb->cmd, xs->cmd, xs->cmdlen);
    713 		acb->clen = xs->cmdlen;
    714 		acb->daddr = xs->data;
    715 		acb->dleft = xs->datalen;
    716 		acb->stat = 0;
    717 
    718 		s = splbio();
    719 		ACB_SETQ(acb, ACB_QREADY);
    720 		TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
    721 #if 1
    722 		callout_reset(&acb->xs->xs_callout,
    723 		    mstohz(xs->timeout), mha_timeout, acb);
    724 #endif
    725 
    726 		/*
    727 		 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B
    728 		 */
    729 		if (sc->sc_state == SPC_IDLE)
    730 			mha_sched(sc);
    731 
    732 		splx(s);
    733 
    734 		if (flags & XS_CTL_POLL) {
    735 			/* Not allowed to use interrupts, use polling instead */
    736 			mha_poll(sc, acb);
    737 		}
    738 
    739 		SPC_MISC(("SUCCESSFULLY_QUEUED"));
    740 		return;
    741 
    742 	case ADAPTER_REQ_GROW_RESOURCES:
    743 		/* XXX Not supported. */
    744 		return;
    745 
    746 	case ADAPTER_REQ_SET_XFER_MODE:
    747 		/* XXX Not supported. */
    748 		return;
    749 	}
    750 }
    751 
    752 /*
    753  * Adjust transfer size in buffer structure
    754  */
    755 void
    756 mha_minphys(struct buf *bp)
    757 {
    758 
    759 	SPC_TRACE(("mha_minphys  "));
    760 	minphys(bp);
    761 }
    762 
    763 /*
    764  * Used when interrupt driven I/O isn't allowed, e.g. during boot.
    765  */
    766 void
    767 mha_poll(struct mha_softc *sc, struct acb *acb)
    768 {
    769 	struct scsipi_xfer *xs = acb->xs;
    770 	int count = xs->timeout * 100;
    771 	int s;
    772 
    773 	s = splbio();
    774 
    775 	SPC_TRACE(("[mha_poll] "));
    776 
    777 	while (count) {
    778 		/*
    779 		 * If we had interrupts enabled, would we
    780 		 * have got an interrupt?
    781 		 */
    782 		if (SSR & SS_IREQUEST)
    783 			mhaintr(sc);
    784 		if ((xs->xs_status & XS_STS_DONE) != 0)
    785 			break;
    786 		DELAY(10);
    787 #if 1
    788 		if (sc->sc_state == SPC_IDLE) {
    789 			SPC_TRACE(("[mha_poll: rescheduling] "));
    790 			mha_sched(sc);
    791 		}
    792 #endif
    793 		count--;
    794 	}
    795 
    796 	if (count == 0) {
    797 		SPC_MISC(("mha_poll: timeout"));
    798 		mha_timeout((void *)acb);
    799 	}
    800 	splx(s);
    801 	scsipi_done(xs);
    802 }
    803 
    804 /*
    805  * LOW LEVEL SCSI UTILITIES
    806  */
    807 
    808 /*
    809  * Set synchronous transfer offset and period.
    810  */
    811 inline void
    812 mha_setsync(struct mha_softc *sc, struct spc_tinfo *ti)
    813 {
    814 }
    815 
    816 /*
    817  * Schedule a SCSI operation.  This has now been pulled out of the interrupt
    818  * handler so that we may call it from mha_scsi_cmd and mha_done.  This may
    819  * save us an unecessary interrupt just to get things going.  Should only be
    820  * called when state == SPC_IDLE and at bio pl.
    821  */
    822 void
    823 mha_sched(struct mha_softc *sc)
    824 {
    825 	struct scsipi_periph *periph;
    826 	struct acb *acb;
    827 	int t;
    828 
    829 	SPC_TRACE(("[mha_sched] "));
    830 	if (sc->sc_state != SPC_IDLE)
    831 		panic("mha_sched: not IDLE (state=%d)", sc->sc_state);
    832 
    833 	if (sc->sc_flags & SPC_ABORTING)
    834 		return;
    835 
    836 	/*
    837 	 * Find first acb in ready queue that is for a target/lunit
    838 	 * combinations that is not busy.
    839 	 */
    840 	for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) {
    841 		struct spc_tinfo *ti;
    842 		periph = acb->xs->xs_periph;
    843 		t = periph->periph_target;
    844 		ti = &sc->sc_tinfo[t];
    845 		if (!(ti->lubusy & (1 << periph->periph_lun))) {
    846 			if ((acb->flags & ACB_QBITS) != ACB_QREADY)
    847 				panic("mha: busy entry on ready list");
    848 			TAILQ_REMOVE(&sc->ready_list, acb, chain);
    849 			ACB_SETQ(acb, ACB_QNONE);
    850 			sc->sc_nexus = acb;
    851 			sc->sc_flags = 0;
    852 			sc->sc_prevphase = INVALID_PHASE;
    853 			sc->sc_dp = acb->daddr;
    854 			sc->sc_dleft = acb->dleft;
    855 			ti->lubusy |= (1<<periph->periph_lun);
    856 			mhaselect(sc, t, periph->periph_lun,
    857 				     (u_char *)&acb->cmd, acb->clen);
    858 			break;
    859 		} else {
    860 			SPC_MISC(("%d:%d busy\n",
    861 			    periph->periph_target,
    862 			    periph->periph_lun));
    863 		}
    864 	}
    865 }
    866 
    867 /*
    868  * POST PROCESSING OF SCSI_CMD (usually current)
    869  */
    870 void
    871 mha_done(struct mha_softc *sc, struct acb *acb)
    872 {
    873 	struct scsipi_xfer *xs = acb->xs;
    874 	struct scsipi_periph *periph = xs->xs_periph;
    875 	struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target];
    876 
    877 	SPC_TRACE(("[mha_done(error:%x)] ", xs->error));
    878 
    879 #if 1
    880 	callout_stop(&acb->xs->xs_callout);
    881 #endif
    882 
    883 	/*
    884 	 * Now, if we've come here with no error code, i.e. we've kept the
    885 	 * initial XS_NOERROR, and the status code signals that we should
    886 	 * check sense, we'll need to set up a request sense cmd block and
    887 	 * push the command back into the ready queue *before* any other
    888 	 * commands for this target/lunit, else we lose the sense info.
    889 	 * We don't support chk sense conditions for the request sense cmd.
    890 	 */
    891 	if (xs->error == XS_NOERROR) {
    892 		if ((acb->flags & ACB_ABORTED) != 0) {
    893 			xs->error = XS_TIMEOUT;
    894 		} else if (acb->flags & ACB_CHKSENSE) {
    895 			xs->error = XS_SENSE;
    896 		} else {
    897 			xs->status = acb->stat & ST_MASK;
    898 			switch (xs->status) {
    899 			case SCSI_CHECK:
    900 				xs->resid = acb->dleft;
    901 				/* FALLTHROUGH */
    902 			case SCSI_BUSY:
    903 				xs->error = XS_BUSY;
    904 				break;
    905 			case SCSI_OK:
    906 				xs->resid = acb->dleft;
    907 				break;
    908 			default:
    909 				xs->error = XS_DRIVER_STUFFUP;
    910 #if SPC_DEBUG
    911 				printf("%s: mha_done: bad stat 0x%x\n",
    912 					device_xname(sc->sc_dev), acb->stat);
    913 #endif
    914 				break;
    915 			}
    916 		}
    917 	}
    918 
    919 #if SPC_DEBUG
    920 	if ((mha_debug & SPC_SHOWMISC) != 0) {
    921 		if (xs->resid != 0)
    922 			printf("resid=%d ", xs->resid);
    923 		if (xs->error == XS_SENSE)
    924 			printf("sense=0x%02x\n", xs->sense.scsi_sense.response_code);
    925 		else
    926 			printf("error=%d\n", xs->error);
    927 	}
    928 #endif
    929 
    930 	/*
    931 	 * Remove the ACB from whatever queue it's on.
    932 	 */
    933 	switch (acb->flags & ACB_QBITS) {
    934 	case ACB_QNONE:
    935 		if (acb != sc->sc_nexus) {
    936 			panic("%s: floating acb", device_xname(sc->sc_dev));
    937 		}
    938 		sc->sc_nexus = NULL;
    939 		sc->sc_state = SPC_IDLE;
    940 		ti->lubusy &= ~(1<<periph->periph_lun);
    941 		mha_sched(sc);
    942 		break;
    943 	case ACB_QREADY:
    944 		TAILQ_REMOVE(&sc->ready_list, acb, chain);
    945 		break;
    946 	case ACB_QNEXUS:
    947 		TAILQ_REMOVE(&sc->nexus_list, acb, chain);
    948 		ti->lubusy &= ~(1<<periph->periph_lun);
    949 		break;
    950 	case ACB_QFREE:
    951 		panic("%s: dequeue: busy acb on free list",
    952 			device_xname(sc->sc_dev));
    953 		break;
    954 	default:
    955 		panic("%s: dequeue: unknown queue %d",
    956 			device_xname(sc->sc_dev), acb->flags & ACB_QBITS);
    957 	}
    958 
    959 	/* Put it on the free list, and clear flags. */
    960 #if 0
    961 	TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
    962 	acb->flags = ACB_QFREE;
    963 #else
    964 	mha_free_acb(sc, acb, xs->xs_control);
    965 #endif
    966 
    967 	ti->cmds++;
    968 	scsipi_done(xs);
    969 }
    970 
    971 void
    972 mha_dequeue(struct mha_softc *sc, struct acb *acb)
    973 {
    974 
    975 	if (acb->flags & ACB_QNEXUS) {
    976 		TAILQ_REMOVE(&sc->nexus_list, acb, chain);
    977 	} else {
    978 		TAILQ_REMOVE(&sc->ready_list, acb, chain);
    979 	}
    980 }
    981 
    982 /*
    983  * INTERRUPT/PROTOCOL ENGINE
    984  */
    985 
    986 /*
    987  * Schedule an outgoing message by prioritizing it, and asserting
    988  * attention on the bus. We can only do this when we are the initiator
    989  * else there will be an illegal command interrupt.
    990  */
    991 #define mha_sched_msgout(m) \
    992 	do {				\
    993 		SPC_MISC(("mha_sched_msgout %d ", m)); \
    994 		CMR = CMD_SET_ATN;	\
    995 		sc->sc_msgpriq |= (m);	\
    996 	} while (0)
    997 
    998 /*
    999  * Precondition:
   1000  * The SCSI bus is already in the MSGI phase and there is a message byte
   1001  * on the bus, along with an asserted REQ signal.
   1002  */
   1003 void
   1004 mha_msgin(struct mha_softc *sc)
   1005 {
   1006 	int v;
   1007 
   1008 	SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen));
   1009 
   1010 	/*
   1011 	 * Prepare for a new message.  A message should (according
   1012 	 * to the SCSI standard) be transmitted in one single
   1013 	 * MESSAGE_IN_PHASE. If we have been in some other phase,
   1014 	 * then this is a new message.
   1015 	 */
   1016 	if (sc->sc_prevphase != MESSAGE_IN_PHASE) {
   1017 		sc->sc_flags &= ~SPC_DROP_MSGI;
   1018 		sc->sc_imlen = 0;
   1019 	}
   1020 
   1021 	WAIT;
   1022 
   1023 	v = MBR;	/* modified byte */
   1024 	v = sc->sc_pcx[0];
   1025 
   1026 	sc->sc_imess[sc->sc_imlen] = v;
   1027 
   1028 	/*
   1029 	 * If we're going to reject the message, don't bother storing
   1030 	 * the incoming bytes.  But still, we need to ACK them.
   1031 	 */
   1032 
   1033 	if ((sc->sc_flags & SPC_DROP_MSGI)) {
   1034 		CMR = CMD_SET_ATN;
   1035 /*		ESPCMD(sc, ESPCMD_MSGOK);*/
   1036 		printf("<dropping msg byte %x>",
   1037 			sc->sc_imess[sc->sc_imlen]);
   1038 		return;
   1039 	}
   1040 
   1041 	if (sc->sc_imlen >= SPC_MAX_MSG_LEN) {
   1042 		mha_sched_msgout(SEND_REJECT);
   1043 		sc->sc_flags |= SPC_DROP_MSGI;
   1044 	} else {
   1045 		sc->sc_imlen++;
   1046 		/*
   1047 		 * This testing is suboptimal, but most
   1048 		 * messages will be of the one byte variety, so
   1049 		 * it should not effect performance
   1050 		 * significantly.
   1051 		 */
   1052 		if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0]))
   1053 			goto gotit;
   1054 		if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0]))
   1055 			goto gotit;
   1056 		if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) &&
   1057 		    sc->sc_imlen == sc->sc_imess[1] + 2)
   1058 			goto gotit;
   1059 	}
   1060 #if 0
   1061 	/* Ack what we have so far */
   1062 	ESPCMD(sc, ESPCMD_MSGOK);
   1063 #endif
   1064 	return;
   1065 
   1066 gotit:
   1067 	SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0]));
   1068 	/*
   1069 	 * Now we should have a complete message (1 byte, 2 byte
   1070 	 * and moderately long extended messages).  We only handle
   1071 	 * extended messages which total length is shorter than
   1072 	 * SPC_MAX_MSG_LEN.  Longer messages will be amputated.
   1073 	 */
   1074 	if (sc->sc_state == SPC_HASNEXUS) {
   1075 		struct acb *acb = sc->sc_nexus;
   1076 		struct spc_tinfo *ti =
   1077 			&sc->sc_tinfo[acb->xs->xs_periph->periph_target];
   1078 
   1079 		switch (sc->sc_imess[0]) {
   1080 		case MSG_CMDCOMPLETE:
   1081 			SPC_MSGS(("cmdcomplete "));
   1082 			if (sc->sc_dleft < 0) {
   1083 				struct scsipi_periph *periph = acb->xs->xs_periph;
   1084 				printf("mha: %d extra bytes from %d:%d\n",
   1085 					-sc->sc_dleft,
   1086 					periph->periph_target,
   1087 				        periph->periph_lun);
   1088 				sc->sc_dleft = 0;
   1089 			}
   1090 			acb->xs->resid = acb->dleft = sc->sc_dleft;
   1091 			sc->sc_flags |= SPC_BUSFREE_OK;
   1092 			break;
   1093 
   1094 		case MSG_MESSAGE_REJECT:
   1095 #if SPC_DEBUG
   1096 			if (mha_debug & SPC_SHOWMSGS)
   1097 				printf("%s: our msg rejected by target\n",
   1098 					device_xname(sc->sc_dev));
   1099 #endif
   1100 #if 1 /* XXX - must remember last message */
   1101 			scsipi_printaddr(acb->xs->xs_periph);
   1102 			printf("MSG_MESSAGE_REJECT>>");
   1103 #endif
   1104 			if (sc->sc_flags & SPC_SYNCHNEGO) {
   1105 				ti->period = ti->offset = 0;
   1106 				sc->sc_flags &= ~SPC_SYNCHNEGO;
   1107 				ti->flags &= ~T_NEGOTIATE;
   1108 			}
   1109 			/* Not all targets understand INITIATOR_DETECTED_ERR */
   1110 			if (sc->sc_msgout == SEND_INIT_DET_ERR)
   1111 				mha_sched_msgout(SEND_ABORT);
   1112 			break;
   1113 		case MSG_NOOP:
   1114 			SPC_MSGS(("noop "));
   1115 			break;
   1116 		case MSG_DISCONNECT:
   1117 			SPC_MSGS(("disconnect "));
   1118 			ti->dconns++;
   1119 			sc->sc_flags |= SPC_DISCON;
   1120 			sc->sc_flags |= SPC_BUSFREE_OK;
   1121 			if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0)
   1122 				break;
   1123 			/*FALLTHROUGH*/
   1124 		case MSG_SAVEDATAPOINTER:
   1125 			SPC_MSGS(("save datapointer "));
   1126 			acb->dleft = sc->sc_dleft;
   1127 			acb->daddr = sc->sc_dp;
   1128 			break;
   1129 		case MSG_RESTOREPOINTERS:
   1130 			SPC_MSGS(("restore datapointer "));
   1131 			if (!acb) {
   1132 				mha_sched_msgout(SEND_ABORT);
   1133 				printf("%s: no DATAPOINTERs to restore\n",
   1134 				    device_xname(sc->sc_dev));
   1135 				break;
   1136 			}
   1137 			sc->sc_dp = acb->daddr;
   1138 			sc->sc_dleft = acb->dleft;
   1139 			break;
   1140 		case MSG_PARITY_ERROR:
   1141 			printf("%s:target%d: MSG_PARITY_ERROR\n",
   1142 				device_xname(sc->sc_dev),
   1143 				acb->xs->xs_periph->periph_target);
   1144 			break;
   1145 		case MSG_EXTENDED:
   1146 			SPC_MSGS(("extended(%x) ", sc->sc_imess[2]));
   1147 			switch (sc->sc_imess[2]) {
   1148 			case MSG_EXT_SDTR:
   1149 				SPC_MSGS(("SDTR period %d, offset %d ",
   1150 					sc->sc_imess[3], sc->sc_imess[4]));
   1151 				ti->period = sc->sc_imess[3];
   1152 				ti->offset = sc->sc_imess[4];
   1153 				if (sc->sc_minsync == 0) {
   1154 					/* We won't do synch */
   1155 					ti->offset = 0;
   1156 					mha_sched_msgout(SEND_SDTR);
   1157 				} else if (ti->offset == 0) {
   1158 					printf("%s:%d: async\n", "mha",
   1159 						acb->xs->xs_periph->periph_target);
   1160 					ti->offset = 0;
   1161 					sc->sc_flags &= ~SPC_SYNCHNEGO;
   1162 				} else if (ti->period > 124) {
   1163 					printf("%s:%d: async\n", "mha",
   1164 						acb->xs->xs_periph->periph_target);
   1165 					ti->offset = 0;
   1166 					mha_sched_msgout(SEND_SDTR);
   1167 				} else {
   1168 #if 0
   1169 					int p;
   1170 					p =  mha_stp2cpb(sc, ti->period);
   1171 					ti->period = mha_cpb2stp(sc, p);
   1172 #endif
   1173 
   1174 #if SPC_DEBUG
   1175 					scsipi_printaddr(acb->xs->xs_periph);
   1176 #endif
   1177 					if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) {
   1178 						/* Target initiated negotiation */
   1179 						if (ti->flags & T_SYNCMODE) {
   1180 						    ti->flags &= ~T_SYNCMODE;
   1181 #if SPC_DEBUG
   1182 						    printf("renegotiated ");
   1183 #endif
   1184 						}
   1185 						TMR=TM_ASYNC;
   1186 						/* Clamp to our maxima */
   1187 						if (ti->period < sc->sc_minsync)
   1188 							ti->period = sc->sc_minsync;
   1189 						if (ti->offset > 15)
   1190 							ti->offset = 15;
   1191 						mha_sched_msgout(SEND_SDTR);
   1192 					} else {
   1193 						/* we are sync */
   1194 						sc->sc_flags &= ~SPC_SYNCHNEGO;
   1195 						TMR = TM_SYNC;
   1196 						ti->flags |= T_SYNCMODE;
   1197 					}
   1198 				}
   1199 				ti->flags &= ~T_NEGOTIATE;
   1200 				break;
   1201 			default: /* Extended messages we don't handle */
   1202 				CMR = CMD_SET_ATN; /* XXX? */
   1203 				break;
   1204 			}
   1205 			break;
   1206 		default:
   1207 			SPC_MSGS(("ident "));
   1208 			/* thanks for that ident... */
   1209 			if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
   1210 				SPC_MISC(("unknown "));
   1211 printf("%s: unimplemented message: %d\n", device_xname(sc->sc_dev), sc->sc_imess[0]);
   1212 				CMR = CMD_SET_ATN; /* XXX? */
   1213 			}
   1214 			break;
   1215 		}
   1216 	} else if (sc->sc_state == SPC_RESELECTED) {
   1217 		struct scsipi_periph *periph = NULL;
   1218 		struct acb *acb;
   1219 		struct spc_tinfo *ti;
   1220 		u_char lunit;
   1221 
   1222 		if (MSG_ISIDENTIFY(sc->sc_imess[0])) { 	/* Identify? */
   1223 			SPC_MISC(("searching "));
   1224 			/*
   1225 			 * Search wait queue for disconnected cmd
   1226 			 * The list should be short, so I haven't bothered with
   1227 			 * any more sophisticated structures than a simple
   1228 			 * singly linked list.
   1229 			 */
   1230 			lunit = sc->sc_imess[0] & 0x07;
   1231 			for (acb = sc->nexus_list.tqh_first; acb;
   1232 			     acb = acb->chain.tqe_next) {
   1233 				periph = acb->xs->xs_periph;
   1234 				if (periph->periph_lun == lunit &&
   1235 				    sc->sc_selid == (1<<periph->periph_target)) {
   1236 					TAILQ_REMOVE(&sc->nexus_list, acb,
   1237 					    chain);
   1238 					ACB_SETQ(acb, ACB_QNONE);
   1239 					break;
   1240 				}
   1241 			}
   1242 
   1243 			if (!acb) {		/* Invalid reselection! */
   1244 				mha_sched_msgout(SEND_ABORT);
   1245 				printf("mha: invalid reselect (idbit=0x%2x)\n",
   1246 				    sc->sc_selid);
   1247 			} else {		/* Reestablish nexus */
   1248 				/*
   1249 				 * Setup driver data structures and
   1250 				 * do an implicit RESTORE POINTERS
   1251 				 */
   1252 				ti = &sc->sc_tinfo[periph->periph_target];
   1253 				sc->sc_nexus = acb;
   1254 				sc->sc_dp = acb->daddr;
   1255 				sc->sc_dleft = acb->dleft;
   1256 				sc->sc_tinfo[periph->periph_target].lubusy
   1257 					|= (1<<periph->periph_lun);
   1258 				if (ti->flags & T_SYNCMODE) {
   1259 					TMR = TM_SYNC;	/* XXX */
   1260 				} else {
   1261 					TMR = TM_ASYNC;
   1262 				}
   1263 				SPC_MISC(("... found acb"));
   1264 				sc->sc_state = SPC_HASNEXUS;
   1265 			}
   1266 		} else {
   1267 			printf("%s: bogus reselect (no IDENTIFY) %0x2x\n",
   1268 			    device_xname(sc->sc_dev), sc->sc_selid);
   1269 			mha_sched_msgout(SEND_DEV_RESET);
   1270 		}
   1271 	} else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */
   1272 		printf("%s: unexpected message in; will send DEV_RESET\n",
   1273 		    device_xname(sc->sc_dev));
   1274 		mha_sched_msgout(SEND_DEV_RESET);
   1275 	}
   1276 
   1277 	/* Ack last message byte */
   1278 #if 0
   1279 	ESPCMD(sc, ESPCMD_MSGOK);
   1280 #endif
   1281 
   1282 	/* Done, reset message pointer. */
   1283 	sc->sc_flags &= ~SPC_DROP_MSGI;
   1284 	sc->sc_imlen = 0;
   1285 }
   1286 
   1287 /*
   1288  * Send the highest priority, scheduled message.
   1289  */
   1290 void
   1291 mha_msgout(struct mha_softc *sc)
   1292 {
   1293 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE)
   1294 	struct spc_tinfo *ti;
   1295 #endif
   1296 	int n;
   1297 
   1298 	SPC_TRACE(("mha_msgout  "));
   1299 
   1300 	if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
   1301 		if (sc->sc_omp == sc->sc_omess) {
   1302 			/*
   1303 			 * This is a retransmission.
   1304 			 *
   1305 			 * We get here if the target stayed in MESSAGE OUT
   1306 			 * phase.  Section 5.1.9.2 of the SCSI 2 spec indicates
   1307 			 * that all of the previously transmitted messages must
   1308 			 * be sent again, in the same order.  Therefore, we
   1309 			 * requeue all the previously transmitted messages, and
   1310 			 * start again from the top.  Our simple priority
   1311 			 * scheme keeps the messages in the right order.
   1312 			 */
   1313 			SPC_MISC(("retransmitting  "));
   1314 			sc->sc_msgpriq |= sc->sc_msgoutq;
   1315 			/*
   1316 			 * Set ATN.  If we're just sending a trivial 1-byte
   1317 			 * message, we'll clear ATN later on anyway.
   1318 			 */
   1319 			CMR = CMD_SET_ATN; /* XXX? */
   1320 		} else {
   1321 			/* This is a continuation of the previous message. */
   1322 			n = sc->sc_omp - sc->sc_omess;
   1323 			goto nextbyte;
   1324 		}
   1325 	}
   1326 
   1327 	/* No messages transmitted so far. */
   1328 	sc->sc_msgoutq = 0;
   1329 	sc->sc_lastmsg = 0;
   1330 
   1331 nextmsg:
   1332 	/* Pick up highest priority message. */
   1333 	sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq;
   1334 	sc->sc_msgpriq &= ~sc->sc_currmsg;
   1335 	sc->sc_msgoutq |= sc->sc_currmsg;
   1336 
   1337 	/* Build the outgoing message data. */
   1338 	switch (sc->sc_currmsg) {
   1339 	case SEND_IDENTIFY:
   1340 		SPC_ASSERT(sc->sc_nexus != NULL);
   1341 		sc->sc_omess[0] =
   1342 		    MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1);
   1343 		n = 1;
   1344 		break;
   1345 
   1346 #if SPC_USE_SYNCHRONOUS
   1347 	case SEND_SDTR:
   1348 		SPC_ASSERT(sc->sc_nexus != NULL);
   1349 		ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
   1350 		sc->sc_omess[4] = MSG_EXTENDED;
   1351 		sc->sc_omess[3] = 3;
   1352 		sc->sc_omess[2] = MSG_EXT_SDTR;
   1353 		sc->sc_omess[1] = ti->period >> 2;
   1354 		sc->sc_omess[0] = ti->offset;
   1355 		n = 5;
   1356 		break;
   1357 #endif
   1358 
   1359 #if SPC_USE_WIDE
   1360 	case SEND_WDTR:
   1361 		SPC_ASSERT(sc->sc_nexus != NULL);
   1362 		ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
   1363 		sc->sc_omess[3] = MSG_EXTENDED;
   1364 		sc->sc_omess[2] = 2;
   1365 		sc->sc_omess[1] = MSG_EXT_WDTR;
   1366 		sc->sc_omess[0] = ti->width;
   1367 		n = 4;
   1368 		break;
   1369 #endif
   1370 
   1371 	case SEND_DEV_RESET:
   1372 		sc->sc_flags |= SPC_ABORTING;
   1373 		sc->sc_omess[0] = MSG_BUS_DEV_RESET;
   1374 		n = 1;
   1375 		break;
   1376 
   1377 	case SEND_REJECT:
   1378 		sc->sc_omess[0] = MSG_MESSAGE_REJECT;
   1379 		n = 1;
   1380 		break;
   1381 
   1382 	case SEND_PARITY_ERROR:
   1383 		sc->sc_omess[0] = MSG_PARITY_ERROR;
   1384 		n = 1;
   1385 		break;
   1386 
   1387 	case SEND_INIT_DET_ERR:
   1388 		sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
   1389 		n = 1;
   1390 		break;
   1391 
   1392 	case SEND_ABORT:
   1393 		sc->sc_flags |= SPC_ABORTING;
   1394 		sc->sc_omess[0] = MSG_ABORT;
   1395 		n = 1;
   1396 		break;
   1397 
   1398 	default:
   1399 		printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
   1400 		    device_xname(sc->sc_dev));
   1401 		SPC_BREAK();
   1402 		sc->sc_omess[0] = MSG_NOOP;
   1403 		n = 1;
   1404 		break;
   1405 	}
   1406 	sc->sc_omp = &sc->sc_omess[n];
   1407 
   1408 nextbyte:
   1409 	/* Send message bytes. */
   1410 	/* send TRANSFER command. */
   1411 	sc->sc_ps[3] = 1;
   1412 	sc->sc_ps[4] = n >> 8;
   1413 	sc->sc_pc[10] = n;
   1414 	sc->sc_ps[-1] = 0x000F;	/* burst */
   1415 	__asm volatile ("nop");
   1416 	CMR = CMD_SEND_FROM_DMA;	/* send from DMA */
   1417 	for (;;) {
   1418 		if ((SSR & SS_BUSY) != 0)
   1419 			break;
   1420 		if (SSR & SS_IREQUEST)
   1421 			goto out;
   1422 	}
   1423 	for (;;) {
   1424 #if 0
   1425 		for (;;) {
   1426 			if ((PSNS & PSNS_REQ) != 0)
   1427 				break;
   1428 			/* Wait for REQINIT.  XXX Need timeout. */
   1429 		}
   1430 #endif
   1431 		if (SSR & SS_IREQUEST) {
   1432 			/*
   1433 			 * Target left MESSAGE OUT, possibly to reject
   1434 			 * our message.
   1435 			 *
   1436 			 * If this is the last message being sent, then we
   1437 			 * deassert ATN, since either the target is going to
   1438 			 * ignore this message, or it's going to ask for a
   1439 			 * retransmission via MESSAGE PARITY ERROR (in which
   1440 			 * case we reassert ATN anyway).
   1441 			 */
   1442 #if 0
   1443 			if (sc->sc_msgpriq == 0)
   1444 				CMR = CMD_RESET_ATN;
   1445 #endif
   1446 			goto out;
   1447 		}
   1448 
   1449 #if 0
   1450 		/* Clear ATN before last byte if this is the last message. */
   1451 		if (n == 1 && sc->sc_msgpriq == 0)
   1452 			CMR = CMD_RESET_ATN;
   1453 #endif
   1454 
   1455 		while ((SSR & SS_DREG_FULL) != 0)
   1456 			;
   1457 		/* Send message byte. */
   1458 		sc->sc_pc[0] = *--sc->sc_omp;
   1459 		--n;
   1460 		/* Keep track of the last message we've sent any bytes of. */
   1461 		sc->sc_lastmsg = sc->sc_currmsg;
   1462 
   1463 		if (n == 0)
   1464 			break;
   1465 	}
   1466 
   1467 	/* We get here only if the entire message has been transmitted. */
   1468 	if (sc->sc_msgpriq != 0) {
   1469 		/* There are more outgoing messages. */
   1470 		goto nextmsg;
   1471 	}
   1472 
   1473 	/*
   1474 	 * The last message has been transmitted.  We need to remember the last
   1475 	 * message transmitted (in case the target switches to MESSAGE IN phase
   1476 	 * and sends a MESSAGE REJECT), and the list of messages transmitted
   1477 	 * this time around (in case the target stays in MESSAGE OUT phase to
   1478 	 * request a retransmit).
   1479 	 */
   1480 
   1481 out:
   1482 	/* Disable REQ/ACK protocol. */
   1483 	return;
   1484 }
   1485 
   1486 /***************************************************************
   1487  *
   1488  *	datain/dataout
   1489  *
   1490  */
   1491 
   1492 int
   1493 mha_datain_pio(struct mha_softc *sc, u_char *p, int n)
   1494 {
   1495 	u_short d;
   1496 	int a;
   1497 	int total_n = n;
   1498 
   1499 	SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n));
   1500 
   1501 	WAIT;
   1502 	sc->sc_ps[3] = 1;
   1503 	sc->sc_ps[4] = n >> 8;
   1504 	sc->sc_pc[10] = n;
   1505 	/* $BHa$7$-%=%U%HE>Aw(B */
   1506 	CMR = CMD_RECEIVE_TO_MPU;
   1507 	for (;;) {
   1508 		a = SSR;
   1509 		if (a & 0x04) {
   1510 			d = sc->sc_ps[0];
   1511 			*p++ = d >> 8;
   1512 			if (--n > 0) {
   1513 				*p++ = d;
   1514 				--n;
   1515 			}
   1516 			a = SSR;
   1517 		}
   1518 		if (a & 0x40)
   1519 			continue;
   1520 		if (a & 0x80)
   1521 			break;
   1522 	}
   1523 	SPC_TRACE(("...%d resd]", n));
   1524 	return total_n - n;
   1525 }
   1526 
   1527 int
   1528 mha_dataout_pio(struct mha_softc *sc, u_char *p, int n)
   1529 {
   1530 	u_short d;
   1531 	int a;
   1532 	int total_n = n;
   1533 
   1534 	SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n));
   1535 
   1536 	WAIT;
   1537 	sc->sc_ps[3] = 1;
   1538 	sc->sc_ps[4] = n >> 8;
   1539 	sc->sc_pc[10] = n;
   1540 	/* $BHa$7$-%=%U%HE>Aw(B */
   1541 	CMR = CMD_SEND_FROM_MPU;
   1542 	for (;;) {
   1543 		a = SSR;
   1544 		if (a & 0x04) {
   1545 			d = *p++ << 8;
   1546 			if (--n > 0) {
   1547 				d |= *p++;
   1548 				--n;
   1549 			}
   1550 			sc->sc_ps[0] = d;
   1551 			a = SSR;
   1552 		}
   1553 		if (a & 0x40)
   1554 			continue;
   1555 		if (a & 0x80)
   1556 			break;
   1557 	}
   1558 	SPC_TRACE(("...%d resd]", n));
   1559 	return total_n - n;
   1560 }
   1561 
   1562 /*
   1563  * dw: DMA word
   1564  * cw: CMR word
   1565  */
   1566 static int
   1567 mha_dataio_dma(int dw, int cw, struct mha_softc *sc, u_char *p, int n)
   1568 {
   1569 	char *paddr;
   1570 
   1571 	if (n > MAXBSIZE)
   1572 		panic("transfer size exceeds MAXBSIZE");
   1573 	if (sc->sc_dmasize > 0)
   1574 		panic("DMA request while another DMA transfer is in pregress");
   1575 
   1576 	if (cw == CMD_SEND_FROM_DMA) {
   1577 		memcpy(sc->sc_dmabuf, p, n);
   1578 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE);
   1579 	} else {
   1580 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD);
   1581 	}
   1582 	sc->sc_p = p;
   1583 	sc->sc_dmasize = n;
   1584 
   1585 	paddr = (char *)sc->sc_dmaseg[0].ds_addr;
   1586 #if MHA_DMA_SHORT_BUS_CYCLE == 1
   1587 	if ((*(volatile int *)&IODEVbase->io_sram[0xac]) &
   1588 	    (1 << ((paddr_t)paddr >> 19)))
   1589 		dw &= ~(1 << 3);
   1590 #endif
   1591 	sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0;
   1592 	sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0;
   1593 	sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0;
   1594 	WAIT;
   1595 	sc->sc_ps[3] = 1;
   1596 	sc->sc_ps[4] = n >> 8;
   1597 	sc->sc_pc[10] = n;
   1598 	/* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B
   1599 	   3 ... short bus cycle
   1600 	   2 ... MAXIMUM XFER.
   1601 	   1 ... BURST XFER.
   1602 	   0 ... R/W */
   1603 	sc->sc_ps[-1] = dw;	/* burst */
   1604 	__asm volatile ("nop");
   1605 	CMR = cw;	/* receive to DMA */
   1606 	return n;
   1607 }
   1608 
   1609 int
   1610 mha_dataout(struct mha_softc *sc, u_char *p, int n)
   1611 {
   1612 	if (n == 0)
   1613 		return n;
   1614 
   1615 	if (n & 1)
   1616 		return mha_dataout_pio(sc, p, n);
   1617 	return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n);
   1618 }
   1619 
   1620 int
   1621 mha_datain(struct mha_softc *sc, u_char *p, int n)
   1622 {
   1623 	 struct acb *acb = sc->sc_nexus;
   1624 
   1625 	 if (n == 0)
   1626 		 return n;
   1627 	 if (acb->cmd.opcode == SCSI_REQUEST_SENSE || (n & 1))
   1628 		 return mha_datain_pio(sc, p, n);
   1629 	 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n);
   1630 }
   1631 
   1632 /*
   1633  * Catch an interrupt from the adaptor
   1634  */
   1635 /*
   1636  * This is the workhorse routine of the driver.
   1637  * Deficiencies (for now):
   1638  * 1) always uses programmed I/O
   1639  */
   1640 int
   1641 mhaintr(void *arg)
   1642 {
   1643 	struct mha_softc *sc = arg;
   1644 #if 0
   1645 	u_char ints;
   1646 #endif
   1647 	struct acb *acb;
   1648 	u_char ph;
   1649 	u_short r;
   1650 	int n;
   1651 
   1652 #if 1	/* XXX called during attach? */
   1653 	if (tmpsc != NULL) {
   1654 		SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc));
   1655 		sc = tmpsc;
   1656 	} else {
   1657 #endif
   1658 
   1659 #if 1	/* XXX */
   1660 	}
   1661 #endif
   1662 
   1663 #if 0
   1664 	/*
   1665 	 * $B3d$j9~$_6X;_$K$9$k(B
   1666 	 */
   1667 	SCTL &= ~SCTL_INTR_ENAB;
   1668 #endif
   1669 
   1670 	SPC_TRACE(("[mhaintr]"));
   1671 
   1672 	/*
   1673 	 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B
   1674 	 */
   1675 	/*
   1676 	 * First check for abnormal conditions, such as reset.
   1677 	 */
   1678 #if 0
   1679 #if 1 /* XXX? */
   1680 	while (((ints = SSR) & SS_IREQUEST) == 0)
   1681 		delay(1);
   1682 	SPC_MISC(("ints = 0x%x  ", ints));
   1683 #else /* usually? */
   1684 	ints = SSR;
   1685 #endif
   1686 #endif
   1687 	while (SSR & SS_IREQUEST) {
   1688 		acb = sc->sc_nexus;
   1689 		r = ISCSR;
   1690 		SPC_MISC(("[r=0x%x]", r));
   1691 		switch (r >> 8) {
   1692 		default:
   1693 			printf("[addr=%p\n"
   1694 			       "result=0x%x\n"
   1695 			       "cmd=0x%x\n"
   1696 			       "ph=0x%x(ought to be %d)]\n",
   1697 			       &ISCSR,
   1698 			       r,
   1699 			       acb->xs->cmd->opcode,
   1700 			       SCR, sc->sc_phase);
   1701 			panic("unexpected result.");
   1702 		case 0x82:	/* selection timeout */
   1703 			SPC_MISC(("selection timeout  "));
   1704 			sc->sc_phase = BUSFREE_PHASE;
   1705 			SPC_ASSERT(sc->sc_nexus != NULL);
   1706 			acb = sc->sc_nexus;
   1707 			delay(250);
   1708 			acb->xs->error = XS_SELTIMEOUT;
   1709 			mha_done(sc, acb);
   1710 			continue;	/* XXX ??? msaitoh */
   1711 		case 0x60:	/* command completed */
   1712 			sc->sc_spcinitialized++;
   1713 			if (sc->sc_phase == BUSFREE_PHASE)
   1714 				continue;
   1715 			ph = SCR;
   1716 			if (ph & PSNS_ACK) {
   1717 				int s;
   1718 				/* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */
   1719 				SPC_MISC(("0x60)phase = %x(ought to be %x)\n",
   1720 					  ph & PHASE_MASK, sc->sc_phase));
   1721 #if 0
   1722 /*				switch (sc->sc_phase) {*/
   1723 #else
   1724 				switch (ph & PHASE_MASK) {
   1725 #endif
   1726 				case STATUS_PHASE:
   1727 					if (sc->sc_state != SPC_HASNEXUS)
   1728 						printf("stsin: !SPC_HASNEXUS->(%d)\n",
   1729 						       sc->sc_state);
   1730 					SPC_ASSERT(sc->sc_nexus != NULL);
   1731 					acb = sc->sc_nexus;
   1732 					WAIT;
   1733 					s = MBR;
   1734 					SPC_ASSERT(s == 1);
   1735 					acb->stat = sc->sc_pcx[0]; /* XXX */
   1736 					SPC_MISC(("stat=0x%02x  ", acb->stat));
   1737 					sc->sc_prevphase = STATUS_PHASE;
   1738 					break;
   1739 				case MESSAGE_IN_PHASE:
   1740 					mha_msgin(sc);
   1741 					sc->sc_prevphase = MESSAGE_IN_PHASE;
   1742 					/* thru */
   1743 				case DATA_IN_PHASE:
   1744 					if (sc->sc_dmasize == 0)
   1745 						break;
   1746 					bus_dmamap_sync(sc->sc_dmat,
   1747 							sc->sc_dmamap,
   1748 							0, sc->sc_dmasize,
   1749 							BUS_DMASYNC_POSTREAD);
   1750 					memcpy(sc->sc_p, sc->sc_dmabuf,
   1751 					       sc->sc_dmasize);
   1752 					sc->sc_dmasize = 0;
   1753 					break;
   1754 				case DATA_OUT_PHASE:
   1755 					if (sc->sc_dmasize == 0)
   1756 						break;
   1757 					bus_dmamap_sync(sc->sc_dmat,
   1758 							sc->sc_dmamap,
   1759 							0, sc->sc_dmasize,
   1760 							BUS_DMASYNC_POSTWRITE);
   1761 					sc->sc_dmasize = 0;
   1762 					break;
   1763 				}
   1764 				WAIT;
   1765 				CMR = CMD_RESET_ACK;	/* reset ack */
   1766 				/*mha_done(sc, acb);	XXX */
   1767 				continue;
   1768 			} else if (NSR & 0x80) { /* nexus */
   1769 #if 1
   1770 				if (sc->sc_state == SPC_SELECTING)	/* XXX msaitoh */
   1771 					sc->sc_state = SPC_HASNEXUS;
   1772 				/* $B%U%'!<%:$N7h$aBG$A$r$9$k(B
   1773 				   $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B
   1774 				   $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B
   1775 				   $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */
   1776 				WAIT;
   1777 				if (SSR & SS_IREQUEST)
   1778 					continue;
   1779 				switch (sc->sc_phase) {
   1780 				default:
   1781 					panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B");
   1782 				case MESSAGE_IN_PHASE:
   1783 					/* $B2?$b$7$J$$(B */
   1784 					continue;
   1785 				case STATUS_PHASE:
   1786 					sc->sc_phase = MESSAGE_IN_PHASE;
   1787 					CMR = CMD_RECEIVE_MSG;	/* receive msg */
   1788 					continue;
   1789 				case DATA_IN_PHASE:
   1790 					sc->sc_prevphase = DATA_IN_PHASE;
   1791 					if (sc->sc_dleft == 0) {
   1792 						/* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B
   1793 						   $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */
   1794 						sc->sc_phase = STATUS_PHASE;
   1795 						CMR = CMD_RECEIVE_STS;	/* receive sts */
   1796 						continue;
   1797 					}
   1798 					n = mha_datain(sc, sc->sc_dp,
   1799 						       sc->sc_dleft);
   1800 					sc->sc_dp += n;
   1801 					sc->sc_dleft -= n;
   1802 					continue;
   1803 				case DATA_OUT_PHASE:
   1804 					sc->sc_prevphase = DATA_OUT_PHASE;
   1805 					if (sc->sc_dleft == 0) {
   1806 						/* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B
   1807 						   $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */
   1808 						sc->sc_phase = STATUS_PHASE;
   1809 						CMR = CMD_RECEIVE_STS;	/* receive sts */
   1810 						continue;
   1811 					}
   1812 					/* data phase $B$NB3$-$r$d$m$&(B */
   1813 					n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
   1814 					sc->sc_dp += n;
   1815 					sc->sc_dleft -= n;
   1816 					continue;
   1817 				case COMMAND_PHASE:
   1818 					/* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */
   1819 					if (acb->dleft) {
   1820 						/* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */
   1821 						if (acb->xs->xs_control & XS_CTL_DATA_IN) {
   1822 							sc->sc_phase = DATA_IN_PHASE;
   1823 							n = mha_datain(sc, sc->sc_dp, sc->sc_dleft);
   1824 							sc->sc_dp += n;
   1825 							sc->sc_dleft -= n;
   1826 						}
   1827 						else if (acb->xs->xs_control & XS_CTL_DATA_OUT) {
   1828 							sc->sc_phase = DATA_OUT_PHASE;
   1829 							n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
   1830 							sc->sc_dp += n;
   1831 							sc->sc_dleft -= n;
   1832 						}
   1833 						continue;
   1834 					}
   1835 					else {
   1836 						/* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */
   1837 						WAIT;
   1838 						sc->sc_phase = STATUS_PHASE;
   1839 						CMR = CMD_RECEIVE_STS;	/* receive sts */
   1840 						continue;
   1841 					}
   1842 				}
   1843 #endif
   1844 			}
   1845 			continue;
   1846 		case 0x31:	/* disconnected in xfer progress. */
   1847 			SPC_MISC(("[0x31]"));
   1848 		case 0x70:	/* disconnected. */
   1849 			SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK);
   1850 			sc->sc_phase = BUSFREE_PHASE;
   1851 			sc->sc_state = SPC_IDLE;
   1852 #if 1
   1853 			acb = sc->sc_nexus;
   1854 			SPC_ASSERT(sc->sc_nexus != NULL);
   1855 			acb->xs->error = XS_NOERROR;
   1856 			mha_done(sc, acb);
   1857 #else
   1858 			TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain);
   1859 			mha_sched(sc);
   1860 #endif
   1861 			continue;
   1862 		case 0x32:	/* phase error in xfer progress. */
   1863 			SPC_MISC(("[0x32]"));
   1864 #if 0
   1865 		case 0x65:	/* invalid command.
   1866 				   $B$J$<$3$s$J$b$N$,=P$k$N$+(B
   1867 				   $B26$K$OA4$/M}2r$G$-$J$$(B */
   1868 #if 1
   1869 			SPC_MISC(("[0x%04x]", r));
   1870 #endif
   1871 #endif
   1872 		case 0x54:	/* initial-phase error. */
   1873 			SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]",
   1874 				  NSR,
   1875 				  SCR, sc->sc_phase));
   1876 			/* thru */
   1877 		case 0x71:	/* assert req */
   1878 			WAIT;
   1879 			if (SSR & 0x40) {
   1880 				printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n",
   1881 				       SSR, r, NSR, SCR);
   1882 				WAIT;
   1883 			}
   1884 			ph = SCR;
   1885 			if (sc->sc_state == SPC_SELECTING) {	/* XXX msaitoh */
   1886 				sc->sc_state = SPC_HASNEXUS;
   1887 			}
   1888 			if (ph & 0x80) {
   1889 				switch (ph & PHASE_MASK) {
   1890 				default:
   1891 					printf("phase = %x\n", ph);
   1892 					panic("assert req: the phase I don't know!");
   1893 				case DATA_IN_PHASE:
   1894 					sc->sc_prevphase = DATA_IN_PHASE;
   1895 					SPC_MISC(("DATAIN(%d)...", sc->sc_dleft));
   1896 					n = mha_datain(sc, sc->sc_dp, sc->sc_dleft);
   1897 					sc->sc_dp += n;
   1898 					sc->sc_dleft -= n;
   1899 					SPC_MISC(("done\n"));
   1900 					continue;
   1901 				case DATA_OUT_PHASE:
   1902 					sc->sc_prevphase = DATA_OUT_PHASE;
   1903 					SPC_MISC(("DATAOUT\n"));
   1904 					n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
   1905 					sc->sc_dp += n;
   1906 					sc->sc_dleft -= n;
   1907 					continue;
   1908 				case STATUS_PHASE:
   1909 					sc->sc_phase = STATUS_PHASE;
   1910 					SPC_MISC(("[RECV_STS]"));
   1911 					WAIT;
   1912 					CMR = CMD_RECEIVE_STS;	/* receive sts */
   1913 					continue;
   1914 				case MESSAGE_IN_PHASE:
   1915 					sc->sc_phase = MESSAGE_IN_PHASE;
   1916 					WAIT;
   1917 					CMR = CMD_RECEIVE_MSG;
   1918 					continue;
   1919 				}
   1920 			}
   1921 			continue;
   1922 		}
   1923 	}
   1924 
   1925 	return 1;
   1926 }
   1927 
   1928 void
   1929 mha_abort(struct mha_softc *sc, struct acb *acb)
   1930 {
   1931 	acb->flags |= ACB_ABORTED;
   1932 
   1933 	if (acb == sc->sc_nexus) {
   1934 		/*
   1935 		 * If we're still selecting, the message will be scheduled
   1936 		 * after selection is complete.
   1937 		 */
   1938 		if (sc->sc_state == SPC_HASNEXUS) {
   1939 			sc->sc_flags |= SPC_ABORTING;
   1940 			mha_sched_msgout(SEND_ABORT);
   1941 		}
   1942 	} else {
   1943 		if (sc->sc_state == SPC_IDLE)
   1944 			mha_sched(sc);
   1945 	}
   1946 }
   1947 
   1948 void
   1949 mha_timeout(void *arg)
   1950 {
   1951 	struct acb *acb = (struct acb *)arg;
   1952 	struct scsipi_xfer *xs = acb->xs;
   1953 	struct scsipi_periph *periph = xs->xs_periph;
   1954 	struct mha_softc *sc =
   1955 	    (void *)periph->periph_channel->chan_adapter->adapt_dev;
   1956 	int s;
   1957 
   1958 	s = splbio();
   1959 
   1960 	scsipi_printaddr(periph);
   1961 	printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], "
   1962 	       "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >",
   1963 		device_xname(sc->sc_dev),
   1964 		acb, acb->flags, acb->dleft, acb->stat,
   1965 		sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase,
   1966 		sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout
   1967 		);
   1968 	printf("[%04x %02x]\n", sc->sc_ps[1], SCR);
   1969 	panic("timeout, ouch!");
   1970 
   1971 	if (acb->flags & ACB_ABORTED) {
   1972 		/* abort timed out */
   1973 		printf(" AGAIN\n");
   1974 #if 0
   1975 		mha_init(sc, 1); /* XXX 1?*/
   1976 #endif
   1977 	} else {
   1978 		/* abort the operation that has timed out */
   1979 		printf("\n");
   1980 		xs->error = XS_TIMEOUT;
   1981 		mha_abort(sc, acb);
   1982 	}
   1983 
   1984 	splx(s);
   1985 }
   1986 
   1987 #if SPC_DEBUG
   1988 /*
   1989  * The following functions are mostly used for debugging purposes, either
   1990  * directly called from the driver or from the kernel debugger.
   1991  */
   1992 
   1993 void
   1994 mha_show_scsi_cmd(struct acb *acb)
   1995 {
   1996 	u_char *b = (u_char *)&acb->cmd;
   1997 	struct scsipi_periph *periph = acb->xs->xs_periph;
   1998 	int i;
   1999 
   2000 	scsipi_printaddr(periph);
   2001 	if ((acb->xs->xs_control & XS_CTL_RESET) == 0) {
   2002 		for (i = 0; i < acb->clen; i++) {
   2003 			if (i)
   2004 				printf(",");
   2005 			printf("%x", b[i]);
   2006 		}
   2007 		printf("\n");
   2008 	} else
   2009 		printf("RESET\n");
   2010 }
   2011 
   2012 void
   2013 mha_print_acb(struct acb *acb)
   2014 {
   2015 
   2016 	printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags);
   2017 	printf(" dp=%p dleft=%d stat=%x\n",
   2018 	    acb->daddr, acb->dleft, acb->stat);
   2019 	mha_show_scsi_cmd(acb);
   2020 }
   2021 
   2022 void
   2023 mha_print_active_acb(void)
   2024 {
   2025 	struct acb *acb;
   2026 	struct mha_softc *sc = device_lookup_private(&mha_cd, 0); /* XXX */
   2027 
   2028 	printf("ready list:\n");
   2029 	for (acb = sc->ready_list.tqh_first; acb != NULL;
   2030 	    acb = acb->chain.tqe_next)
   2031 		mha_print_acb(acb);
   2032 	printf("nexus:\n");
   2033 	if (sc->sc_nexus != NULL)
   2034 		mha_print_acb(sc->sc_nexus);
   2035 	printf("nexus list:\n");
   2036 	for (acb = sc->nexus_list.tqh_first; acb != NULL;
   2037 	    acb = acb->chain.tqe_next)
   2038 		mha_print_acb(acb);
   2039 }
   2040 
   2041 void
   2042 mha_dump_driver(struct mha_softc *sc)
   2043 {
   2044 	struct spc_tinfo *ti;
   2045 	int i;
   2046 
   2047 	printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase);
   2048 	printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n",
   2049 	    sc->sc_state, sc->sc_imess[0],
   2050 	    sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg);
   2051 	for (i = 0; i < 7; i++) {
   2052 		ti = &sc->sc_tinfo[i];
   2053 		printf("tinfo%d: %d cmds %d disconnects %d timeouts",
   2054 		    i, ti->cmds, ti->dconns, ti->touts);
   2055 		printf(" %d senses flags=%x\n", ti->senses, ti->flags);
   2056 	}
   2057 }
   2058 #endif
   2059