zs.c revision 1.15
1 /* $NetBSD: zs.c,v 1.15 1999/03/16 16:30:20 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 #include <arch/x68k/dev/intiovar.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/ic/z8530reg.h> 67 68 #include "zsc.h" /* NZSC */ 69 #include "opt_zsc.h" 70 #ifndef ZSCN_SPEED 71 #define ZSCN_SPEED 9600 72 #endif 73 #include "zstty.h" 74 75 76 extern void Debugger __P((void)); 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 85 int zs_major = 12; 86 87 /* 88 * X68k provides a 5.0 MHz clock to the ZS chips. 89 */ 90 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 91 92 93 /* Default physical addresses. */ 94 #define ZS_MAXDEV 5 95 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 96 0x00e98000, 97 0x00eafc00, 98 0x00eafc10, 99 0x00eafc20, 100 0x00eafc30 101 }; 102 103 static u_char zs_init_reg[16] = { 104 0, /* 0: CMD (reset, etc.) */ 105 0, /* 1: No interrupts yet. */ 106 0x70, /* 2: XXX: IVECT */ 107 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 108 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 109 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 110 0, /* 6: TXSYNC/SYNCLO */ 111 0, /* 7: RXSYNC/SYNCHI */ 112 0, /* 8: alias for data port */ 113 ZSWR9_MASTER_IE, 114 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 115 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 116 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 117 0, /*13: BAUDHI (default=9600) */ 118 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 119 ZSWR15_BREAK_IE, 120 }; 121 122 static volatile struct zschan *conschan = 0; 123 124 125 /**************************************************************** 126 * Autoconfig 127 ****************************************************************/ 128 129 /* Definition of the driver for autoconfig. */ 130 static int zs_match __P((struct device *, struct cfdata *, void *)); 131 static void zs_attach __P((struct device *, struct device *, void *)); 132 static int zs_print __P((void *, const char *name)); 133 134 struct cfattach zsc_ca = { 135 sizeof(struct zsc_softc), zs_match, zs_attach 136 }; 137 138 extern struct cfdriver zsc_cd; 139 140 static int zshard __P((void *)); 141 int zssoft __P((void *)); 142 static int zs_get_speed __P((struct zs_chanstate *)); 143 144 145 /* 146 * Is the zs chip present? 147 */ 148 static int 149 zs_match(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct intio_attach_args *ia = aux; 155 int unit = cf->cf_unit; 156 struct zsdevice *zsaddr = (void*) ia->ia_addr; 157 int i; 158 159 if (strcmp (ia->ia_name, "zsc") != 0) 160 return 0; 161 162 for (i = 0; i < ZS_MAXDEV; i++) 163 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 164 break; 165 166 ia->ia_size = 8; 167 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 168 return 0; 169 170 if (zsaddr != (void*) zs_physaddr[i]) 171 return 0; 172 if (badaddr(INTIO_ADDR(zsaddr))) 173 return 0; 174 175 return (1); 176 } 177 178 /* 179 * Attach a found zs. 180 */ 181 static void 182 zs_attach(parent, self, aux) 183 struct device *parent; 184 struct device *self; 185 void *aux; 186 { 187 struct zsc_softc *zsc = (void *) self; 188 struct intio_attach_args *ia = aux; 189 struct zsc_attach_args zsc_args; 190 volatile struct zschan *zc; 191 struct zs_chanstate *cs; 192 int r, s, zs_unit, channel; 193 194 zs_unit = zsc->zsc_dev.dv_unit; 195 zsc->zsc_addr = (void*) ia->ia_addr; 196 197 ia->ia_size = 8; 198 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 199 #ifdef DIAGNOSTIC 200 if (r) 201 panic ("zs: intio IO map corruption"); 202 #endif 203 204 printf("\n"); 205 206 /* 207 * Initialize software state for each channel. 208 */ 209 for (channel = 0; channel < 2; channel++) { 210 struct device *child; 211 212 zsc_args.channel = channel; 213 zsc_args.hwflags = 0; 214 cs = &zsc->zsc_cs_store[channel]; 215 zsc->zsc_cs[channel] = cs; 216 217 cs->cs_channel = channel; 218 cs->cs_private = NULL; 219 cs->cs_ops = &zsops_null; 220 cs->cs_brg_clk = PCLK / 16; 221 222 if (channel == 0) 223 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 224 else 225 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 226 cs->cs_reg_csr = &zc->zc_csr; 227 cs->cs_reg_data = &zc->zc_data; 228 229 zs_init_reg[2] = ia->ia_intr; 230 bcopy(zs_init_reg, cs->cs_creg, 16); 231 bcopy(zs_init_reg, cs->cs_preg, 16); 232 233 if (zc == conschan) { 234 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 235 cs->cs_defspeed = zs_get_speed(cs); 236 cs->cs_defcflag = zscn_def_cflag; 237 } else { 238 cs->cs_defspeed = 9600; 239 cs->cs_defcflag = zs_def_cflag; 240 } 241 242 /* Make these correspond to cs_defcflag (-crtscts) */ 243 cs->cs_rr0_dcd = ZSRR0_DCD; 244 cs->cs_rr0_cts = 0; 245 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 246 cs->cs_wr5_rts = 0; 247 248 /* 249 * Clear the master interrupt enable. 250 * The INTENA is common to both channels, 251 * so just do it on the A channel. 252 */ 253 if (channel == 0) { 254 s = splzs(); 255 zs_write_reg(cs, 9, 0); 256 splx(s); 257 } 258 259 /* 260 * Look for a child driver for this channel. 261 * The child attach will setup the hardware. 262 */ 263 child = config_found(self, (void *)&zsc_args, zs_print); 264 #if ZSTTY > 0 265 if (zc == conschan && 266 ((child && strcmp (child->dv_xname, "zstty0")) || 267 child == NULL)) /* XXX */ 268 panic ("zs_attach: console device mismatch"); 269 #endif 270 if (child == NULL) { 271 /* No sub-driver. Just reset it. */ 272 u_char reset = (channel == 0) ? 273 ZSWR9_A_RESET : ZSWR9_B_RESET; 274 s = splzs(); 275 zs_write_reg(cs, 9, reset); 276 splx(s); 277 } 278 } 279 280 /* 281 * Now safe to install interrupt handlers. 282 */ 283 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 284 panic("zs_attach: interrupt vector busy"); 285 /* XXX; evcnt_attach() ? */ 286 287 /* 288 * Set the master interrupt enable and interrupt vector. 289 * (common to both channels, do it on A) 290 */ 291 cs = zsc->zsc_cs[0]; 292 s = splzs(); 293 /* interrupt vector */ 294 zs_write_reg(cs, 2, ia->ia_intr); 295 /* master interrupt control (enable) */ 296 zs_write_reg(cs, 9, zs_init_reg[9]); 297 splx(s); 298 } 299 300 static int 301 zs_print(aux, name) 302 void *aux; 303 const char *name; 304 { 305 struct zsc_attach_args *args = aux; 306 307 if (name != NULL) 308 printf("%s: ", name); 309 310 if (args->channel != -1) 311 printf(" channel %d", args->channel); 312 313 return UNCONF; 314 } 315 316 317 /* 318 * For x68k-port, we don't use autovectored interrupt. 319 * We do not need to look at all of the zs chips. 320 */ 321 static int 322 zshard(arg) 323 void *arg; 324 { 325 register struct zsc_softc *zsc = arg; 326 register int rval; 327 int s; 328 329 /* 330 * Actually, zs hardware ipl is 5. 331 * Here we disable all interrupts to shorten the zshard 332 * handling time. Otherwise, too many characters are 333 * dropped. 334 */ 335 s = splhigh(); 336 rval = zsc_intr_hard(zsc); 337 338 /* We are at splzs here, so no need to lock. */ 339 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 340 setsoftserial(); 341 342 return (rval); 343 } 344 345 /* 346 * Shared among the all chips. We have to look at all of them. 347 */ 348 int 349 zssoft(arg) 350 void *arg; 351 { 352 register struct zsc_softc *zsc; 353 register int s, unit; 354 355 /* Make sure we call the tty layer at spltty. */ 356 s = spltty(); 357 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 358 zsc = zsc_cd.cd_devs[unit]; 359 if (zsc == NULL) 360 continue; 361 (void) zsc_intr_soft(zsc); 362 } 363 splx(s); 364 365 return (1); 366 } 367 368 369 /* 370 * Compute the current baud rate given a ZS channel. 371 */ 372 static int 373 zs_get_speed(cs) 374 struct zs_chanstate *cs; 375 { 376 int tconst; 377 378 tconst = zs_read_reg(cs, 12); 379 tconst |= zs_read_reg(cs, 13) << 8; 380 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 381 } 382 383 /* 384 * MD functions for setting the baud rate and control modes. 385 */ 386 int 387 zs_set_speed(cs, bps) 388 struct zs_chanstate *cs; 389 int bps; /* bits per second */ 390 { 391 int tconst, real_bps; 392 393 if (bps == 0) 394 return (0); 395 396 #ifdef DIAGNOSTIC 397 if (cs->cs_brg_clk == 0) 398 panic("zs_set_speed"); 399 #endif 400 401 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 402 if (tconst < 0) 403 return (EINVAL); 404 405 /* Convert back to make sure we can do it. */ 406 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 407 408 #if 0 /* XXX */ 409 /* XXX - Allow some tolerance here? */ 410 if (real_bps != bps) 411 return (EINVAL); 412 #else 413 /* 414 * Since our PCLK has somewhat strange value, 415 * we have to allow tolerance here. 416 */ 417 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 418 return (EINVAL); 419 #endif 420 421 cs->cs_preg[12] = tconst; 422 cs->cs_preg[13] = tconst >> 8; 423 424 /* Caller will stuff the pending registers. */ 425 return (0); 426 } 427 428 int 429 zs_set_modes(cs, cflag) 430 struct zs_chanstate *cs; 431 int cflag; /* bits per second */ 432 { 433 int s; 434 435 /* 436 * Output hardware flow control on the chip is horrendous: 437 * if carrier detect drops, the receiver is disabled, and if 438 * CTS drops, the transmitter is stoped IN MID CHARACTER! 439 * Therefore, NEVER set the HFC bit, and instead use the 440 * status interrupt to detect CTS changes. 441 */ 442 s = splzs(); 443 if ((cflag & (CLOCAL | MDMBUF)) != 0) 444 cs->cs_rr0_dcd = 0; 445 else 446 cs->cs_rr0_dcd = ZSRR0_DCD; 447 if ((cflag & CRTSCTS) != 0) { 448 cs->cs_wr5_dtr = ZSWR5_DTR; 449 cs->cs_wr5_rts = ZSWR5_RTS; 450 cs->cs_rr0_cts = ZSRR0_CTS; 451 } else if ((cflag & MDMBUF) != 0) { 452 cs->cs_wr5_dtr = 0; 453 cs->cs_wr5_rts = ZSWR5_DTR; 454 cs->cs_rr0_cts = ZSRR0_DCD; 455 } else { 456 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 457 cs->cs_wr5_rts = 0; 458 cs->cs_rr0_cts = 0; 459 } 460 splx(s); 461 462 /* Caller will stuff the pending registers. */ 463 return (0); 464 } 465 466 467 /* 468 * Read or write the chip with suitable delays. 469 */ 470 471 u_char 472 zs_read_reg(cs, reg) 473 struct zs_chanstate *cs; 474 u_char reg; 475 { 476 u_char val; 477 478 *cs->cs_reg_csr = reg; 479 ZS_DELAY(); 480 val = *cs->cs_reg_csr; 481 ZS_DELAY(); 482 return val; 483 } 484 485 void 486 zs_write_reg(cs, reg, val) 487 struct zs_chanstate *cs; 488 u_char reg, val; 489 { 490 *cs->cs_reg_csr = reg; 491 ZS_DELAY(); 492 *cs->cs_reg_csr = val; 493 ZS_DELAY(); 494 } 495 496 u_char zs_read_csr(cs) 497 struct zs_chanstate *cs; 498 { 499 register u_char val; 500 501 val = *cs->cs_reg_csr; 502 ZS_DELAY(); 503 return val; 504 } 505 506 void zs_write_csr(cs, val) 507 struct zs_chanstate *cs; 508 u_char val; 509 { 510 *cs->cs_reg_csr = val; 511 ZS_DELAY(); 512 } 513 514 u_char zs_read_data(cs) 515 struct zs_chanstate *cs; 516 { 517 register u_char val; 518 519 val = *cs->cs_reg_data; 520 ZS_DELAY(); 521 return val; 522 } 523 524 void zs_write_data(cs, val) 525 struct zs_chanstate *cs; 526 u_char val; 527 { 528 *cs->cs_reg_data = val; 529 ZS_DELAY(); 530 } 531 532 533 static struct zs_chanstate zscn_cs; 534 535 /**************************************************************** 536 * Console support functions (x68k specific!) 537 * Note: this code is allowed to know about the layout of 538 * the chip registers, and uses that to keep things simple. 539 * XXX - I think I like the mvme167 code better. -gwr 540 ****************************************************************/ 541 542 /* 543 * Handle user request to enter kernel debugger. 544 */ 545 void 546 zs_abort(cs) 547 struct zs_chanstate *cs; 548 { 549 int rr0; 550 551 /* Wait for end of break to avoid PROM abort. */ 552 /* XXX - Limit the wait? */ 553 do { 554 rr0 = *cs->cs_reg_csr; 555 ZS_DELAY(); 556 } while (rr0 & ZSRR0_BREAK); 557 558 #ifdef DDB 559 Debugger(); 560 #else 561 printf ("BREAK!!\n"); 562 #endif 563 } 564 565 566 #if NZSTTY > 0 567 568 #include <dev/cons.h> 569 cons_decl(zs); 570 571 static int zs_getc __P((void)); 572 static void zs_putc __P((int)); 573 574 /* 575 * Polled input char. 576 */ 577 static int 578 zs_getc(void) 579 { 580 register int s, c, rr0; 581 582 s = splzs(); 583 /* Wait for a character to arrive. */ 584 do { 585 rr0 = zs_read_csr(&zscn_cs); 586 } while ((rr0 & ZSRR0_RX_READY) == 0); 587 588 c = zs_read_data (&zscn_cs); 589 splx(s); 590 591 /* 592 * This is used by the kd driver to read scan codes, 593 * so don't translate '\r' ==> '\n' here... 594 */ 595 return (c); 596 } 597 598 /* 599 * Polled output char. 600 */ 601 static void 602 zs_putc(c) 603 int c; 604 { 605 register int s, rr0; 606 607 s = splzs(); 608 /* Wait for transmitter to become ready. */ 609 do { 610 rr0 = zs_read_csr (&zscn_cs); 611 } while ((rr0 & ZSRR0_TX_READY) == 0); 612 613 zs_write_data(&zscn_cs, c); 614 splx(s); 615 } 616 617 void 618 zscninit(cn) 619 struct consdev *cn; 620 { 621 volatile struct zschan *cnchan = (void*) INTIO_ADDR(ZSCN_PHYSADDR); 622 int s; 623 624 bzero (&zscn_cs, sizeof (struct zs_chanstate)); 625 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 626 zscn_cs.cs_reg_data = &cnchan->zc_data; 627 zscn_cs.cs_channel = 0; 628 zscn_cs.cs_brg_clk = PCLK / 16; 629 bcopy (zs_init_reg, zscn_cs.cs_preg, 16); 630 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 631 zscn_cs.cs_preg[9] = 0; 632 zs_set_speed(&zscn_cs, ZSCN_SPEED); 633 s = splzs(); 634 zs_loadchannelregs(&zscn_cs); 635 splx(s); 636 conschan = cnchan; 637 } 638 639 /* 640 * Polled console input putchar. 641 */ 642 int 643 zscngetc(dev) 644 dev_t dev; 645 { 646 return (zs_getc()); 647 } 648 649 /* 650 * Polled console output putchar. 651 */ 652 void 653 zscnputc(dev, c) 654 dev_t dev; 655 int c; 656 { 657 zs_putc(c); 658 } 659 660 extern int zsopen(dev_t, int, int, struct proc *); 661 662 void 663 zscnprobe(cd) 664 struct consdev *cd; 665 { 666 int maj; 667 668 /* locate the major number */ 669 for (maj = 0; maj < nchrdev; maj++) 670 if (cdevsw[maj].d_open == zsopen) 671 break; 672 /* XXX: minor number is 0 */ 673 674 if (cdevsw[maj].d_open != zsopen) 675 cd->cn_pri = CN_DEAD; 676 else { 677 #ifdef ZSCONSOLE 678 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 679 #else 680 cd->cn_pri = CN_NORMAL; 681 #endif 682 cd->cn_dev = makedev(maj, 0); 683 } 684 } 685 686 void 687 zscnpollc(dev, on) 688 dev_t dev; 689 int on; 690 { 691 } 692 693 #endif 694
Indexes created Tue Sep 30 07:10:03 GMT 2025