zs.c revision 1.17
1 /* $NetBSD: zs.c,v 1.17 1999/03/27 01:21:37 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 #include <arch/x68k/dev/intiovar.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/ic/z8530reg.h> 67 68 #include "zsc.h" /* NZSC */ 69 #include "opt_zsc.h" 70 #ifndef ZSCN_SPEED 71 #define ZSCN_SPEED 9600 72 #endif 73 #include "zstty.h" 74 75 76 extern void Debugger __P((void)); 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 85 int zs_major = 12; 86 87 /* 88 * X68k provides a 5.0 MHz clock to the ZS chips. 89 */ 90 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 91 92 93 /* Default physical addresses. */ 94 #define ZS_MAXDEV 5 95 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 96 0x00e98000, 97 0x00eafc00, 98 0x00eafc10, 99 0x00eafc20, 100 0x00eafc30 101 }; 102 103 static u_char zs_init_reg[16] = { 104 0, /* 0: CMD (reset, etc.) */ 105 0, /* 1: No interrupts yet. */ 106 0x70, /* 2: XXX: IVECT */ 107 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 108 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 109 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 110 0, /* 6: TXSYNC/SYNCLO */ 111 0, /* 7: RXSYNC/SYNCHI */ 112 0, /* 8: alias for data port */ 113 ZSWR9_MASTER_IE, 114 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 115 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 116 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 117 0, /*13: BAUDHI (default=9600) */ 118 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 119 ZSWR15_BREAK_IE, 120 }; 121 122 static volatile struct zschan *conschan = 0; 123 124 125 /**************************************************************** 126 * Autoconfig 127 ****************************************************************/ 128 129 /* Definition of the driver for autoconfig. */ 130 static int zs_match __P((struct device *, struct cfdata *, void *)); 131 static void zs_attach __P((struct device *, struct device *, void *)); 132 static int zs_print __P((void *, const char *name)); 133 134 struct cfattach zsc_ca = { 135 sizeof(struct zsc_softc), zs_match, zs_attach 136 }; 137 138 extern struct cfdriver zsc_cd; 139 140 static int zshard __P((void *)); 141 int zssoft __P((void *)); 142 static int zs_get_speed __P((struct zs_chanstate *)); 143 144 145 /* 146 * Is the zs chip present? 147 */ 148 static int 149 zs_match(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct intio_attach_args *ia = aux; 155 struct zsdevice *zsaddr = (void*) ia->ia_addr; 156 int i; 157 158 if (strcmp (ia->ia_name, "zsc") != 0) 159 return 0; 160 161 for (i = 0; i < ZS_MAXDEV; i++) 162 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 163 break; 164 165 ia->ia_size = 8; 166 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 167 return 0; 168 169 if (zsaddr != (void*) zs_physaddr[i]) 170 return 0; 171 if (badaddr((caddr_t)INTIO_ADDR(zsaddr))) 172 return 0; 173 174 return (1); 175 } 176 177 /* 178 * Attach a found zs. 179 */ 180 static void 181 zs_attach(parent, self, aux) 182 struct device *parent; 183 struct device *self; 184 void *aux; 185 { 186 struct zsc_softc *zsc = (void *) self; 187 struct intio_attach_args *ia = aux; 188 struct zsc_attach_args zsc_args; 189 volatile struct zschan *zc; 190 struct zs_chanstate *cs; 191 int r, s, zs_unit, channel; 192 193 zs_unit = zsc->zsc_dev.dv_unit; 194 zsc->zsc_addr = (void*) ia->ia_addr; 195 196 ia->ia_size = 8; 197 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 198 #ifdef DIAGNOSTIC 199 if (r) 200 panic ("zs: intio IO map corruption"); 201 #endif 202 203 printf("\n"); 204 205 /* 206 * Initialize software state for each channel. 207 */ 208 for (channel = 0; channel < 2; channel++) { 209 struct device *child; 210 211 zsc_args.channel = channel; 212 zsc_args.hwflags = 0; 213 cs = &zsc->zsc_cs_store[channel]; 214 zsc->zsc_cs[channel] = cs; 215 216 cs->cs_channel = channel; 217 cs->cs_private = NULL; 218 cs->cs_ops = &zsops_null; 219 cs->cs_brg_clk = PCLK / 16; 220 221 if (channel == 0) 222 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 223 else 224 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 225 cs->cs_reg_csr = &zc->zc_csr; 226 cs->cs_reg_data = &zc->zc_data; 227 228 zs_init_reg[2] = ia->ia_intr; 229 bcopy(zs_init_reg, cs->cs_creg, 16); 230 bcopy(zs_init_reg, cs->cs_preg, 16); 231 232 if (zc == conschan) { 233 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 234 cs->cs_defspeed = zs_get_speed(cs); 235 cs->cs_defcflag = zscn_def_cflag; 236 } else { 237 cs->cs_defspeed = 9600; 238 cs->cs_defcflag = zs_def_cflag; 239 } 240 241 /* Make these correspond to cs_defcflag (-crtscts) */ 242 cs->cs_rr0_dcd = ZSRR0_DCD; 243 cs->cs_rr0_cts = 0; 244 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 245 cs->cs_wr5_rts = 0; 246 247 /* 248 * Clear the master interrupt enable. 249 * The INTENA is common to both channels, 250 * so just do it on the A channel. 251 */ 252 if (channel == 0) { 253 s = splzs(); 254 zs_write_reg(cs, 9, 0); 255 splx(s); 256 } 257 258 /* 259 * Look for a child driver for this channel. 260 * The child attach will setup the hardware. 261 */ 262 child = config_found(self, (void *)&zsc_args, zs_print); 263 #if ZSTTY > 0 264 if (zc == conschan && 265 ((child && strcmp (child->dv_xname, "zstty0")) || 266 child == NULL)) /* XXX */ 267 panic ("zs_attach: console device mismatch"); 268 #endif 269 if (child == NULL) { 270 /* No sub-driver. Just reset it. */ 271 u_char reset = (channel == 0) ? 272 ZSWR9_A_RESET : ZSWR9_B_RESET; 273 s = splzs(); 274 zs_write_reg(cs, 9, reset); 275 splx(s); 276 } 277 } 278 279 /* 280 * Now safe to install interrupt handlers. 281 */ 282 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 283 panic("zs_attach: interrupt vector busy"); 284 /* XXX; evcnt_attach() ? */ 285 286 /* 287 * Set the master interrupt enable and interrupt vector. 288 * (common to both channels, do it on A) 289 */ 290 cs = zsc->zsc_cs[0]; 291 s = splzs(); 292 /* interrupt vector */ 293 zs_write_reg(cs, 2, ia->ia_intr); 294 /* master interrupt control (enable) */ 295 zs_write_reg(cs, 9, zs_init_reg[9]); 296 splx(s); 297 } 298 299 static int 300 zs_print(aux, name) 301 void *aux; 302 const char *name; 303 { 304 struct zsc_attach_args *args = aux; 305 306 if (name != NULL) 307 printf("%s: ", name); 308 309 if (args->channel != -1) 310 printf(" channel %d", args->channel); 311 312 return UNCONF; 313 } 314 315 316 /* 317 * For x68k-port, we don't use autovectored interrupt. 318 * We do not need to look at all of the zs chips. 319 */ 320 static int 321 zshard(arg) 322 void *arg; 323 { 324 register struct zsc_softc *zsc = arg; 325 register int rval; 326 int s; 327 328 /* 329 * Actually, zs hardware ipl is 5. 330 * Here we disable all interrupts to shorten the zshard 331 * handling time. Otherwise, too many characters are 332 * dropped. 333 */ 334 s = splhigh(); 335 rval = zsc_intr_hard(zsc); 336 337 /* We are at splzs here, so no need to lock. */ 338 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 339 setsoftserial(); 340 341 return (rval); 342 } 343 344 /* 345 * Shared among the all chips. We have to look at all of them. 346 */ 347 int 348 zssoft(arg) 349 void *arg; 350 { 351 register struct zsc_softc *zsc; 352 register int s, unit; 353 354 /* Make sure we call the tty layer at spltty. */ 355 s = spltty(); 356 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 357 zsc = zsc_cd.cd_devs[unit]; 358 if (zsc == NULL) 359 continue; 360 (void) zsc_intr_soft(zsc); 361 } 362 splx(s); 363 364 return (1); 365 } 366 367 368 /* 369 * Compute the current baud rate given a ZS channel. 370 */ 371 static int 372 zs_get_speed(cs) 373 struct zs_chanstate *cs; 374 { 375 int tconst; 376 377 tconst = zs_read_reg(cs, 12); 378 tconst |= zs_read_reg(cs, 13) << 8; 379 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 380 } 381 382 /* 383 * MD functions for setting the baud rate and control modes. 384 */ 385 int 386 zs_set_speed(cs, bps) 387 struct zs_chanstate *cs; 388 int bps; /* bits per second */ 389 { 390 int tconst, real_bps; 391 392 if (bps == 0) 393 return (0); 394 395 #ifdef DIAGNOSTIC 396 if (cs->cs_brg_clk == 0) 397 panic("zs_set_speed"); 398 #endif 399 400 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 401 if (tconst < 0) 402 return (EINVAL); 403 404 /* Convert back to make sure we can do it. */ 405 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 406 407 #if 0 /* XXX */ 408 /* XXX - Allow some tolerance here? */ 409 if (real_bps != bps) 410 return (EINVAL); 411 #else 412 /* 413 * Since our PCLK has somewhat strange value, 414 * we have to allow tolerance here. 415 */ 416 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 417 return (EINVAL); 418 #endif 419 420 cs->cs_preg[12] = tconst; 421 cs->cs_preg[13] = tconst >> 8; 422 423 /* Caller will stuff the pending registers. */ 424 return (0); 425 } 426 427 int 428 zs_set_modes(cs, cflag) 429 struct zs_chanstate *cs; 430 int cflag; /* bits per second */ 431 { 432 int s; 433 434 /* 435 * Output hardware flow control on the chip is horrendous: 436 * if carrier detect drops, the receiver is disabled, and if 437 * CTS drops, the transmitter is stoped IN MID CHARACTER! 438 * Therefore, NEVER set the HFC bit, and instead use the 439 * status interrupt to detect CTS changes. 440 */ 441 s = splzs(); 442 cs->cs_rr0_pps = 0; 443 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 444 cs->cs_rr0_dcd = 0; 445 if ((cflag & MDMBUF) == 0) 446 cs->cs_rr0_pps = ZSRR0_DCD; 447 } else 448 cs->cs_rr0_dcd = ZSRR0_DCD; 449 if ((cflag & CRTSCTS) != 0) { 450 cs->cs_wr5_dtr = ZSWR5_DTR; 451 cs->cs_wr5_rts = ZSWR5_RTS; 452 cs->cs_rr0_cts = ZSRR0_CTS; 453 } else if ((cflag & MDMBUF) != 0) { 454 cs->cs_wr5_dtr = 0; 455 cs->cs_wr5_rts = ZSWR5_DTR; 456 cs->cs_rr0_cts = ZSRR0_DCD; 457 } else { 458 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 459 cs->cs_wr5_rts = 0; 460 cs->cs_rr0_cts = 0; 461 } 462 splx(s); 463 464 /* Caller will stuff the pending registers. */ 465 return (0); 466 } 467 468 469 /* 470 * Read or write the chip with suitable delays. 471 */ 472 473 u_char 474 zs_read_reg(cs, reg) 475 struct zs_chanstate *cs; 476 u_char reg; 477 { 478 u_char val; 479 480 *cs->cs_reg_csr = reg; 481 ZS_DELAY(); 482 val = *cs->cs_reg_csr; 483 ZS_DELAY(); 484 return val; 485 } 486 487 void 488 zs_write_reg(cs, reg, val) 489 struct zs_chanstate *cs; 490 u_char reg, val; 491 { 492 *cs->cs_reg_csr = reg; 493 ZS_DELAY(); 494 *cs->cs_reg_csr = val; 495 ZS_DELAY(); 496 } 497 498 u_char zs_read_csr(cs) 499 struct zs_chanstate *cs; 500 { 501 register u_char val; 502 503 val = *cs->cs_reg_csr; 504 ZS_DELAY(); 505 return val; 506 } 507 508 void zs_write_csr(cs, val) 509 struct zs_chanstate *cs; 510 u_char val; 511 { 512 *cs->cs_reg_csr = val; 513 ZS_DELAY(); 514 } 515 516 u_char zs_read_data(cs) 517 struct zs_chanstate *cs; 518 { 519 register u_char val; 520 521 val = *cs->cs_reg_data; 522 ZS_DELAY(); 523 return val; 524 } 525 526 void zs_write_data(cs, val) 527 struct zs_chanstate *cs; 528 u_char val; 529 { 530 *cs->cs_reg_data = val; 531 ZS_DELAY(); 532 } 533 534 535 static struct zs_chanstate zscn_cs; 536 537 /**************************************************************** 538 * Console support functions (x68k specific!) 539 * Note: this code is allowed to know about the layout of 540 * the chip registers, and uses that to keep things simple. 541 * XXX - I think I like the mvme167 code better. -gwr 542 ****************************************************************/ 543 544 /* 545 * Handle user request to enter kernel debugger. 546 */ 547 void 548 zs_abort(cs) 549 struct zs_chanstate *cs; 550 { 551 int rr0; 552 553 /* Wait for end of break to avoid PROM abort. */ 554 /* XXX - Limit the wait? */ 555 do { 556 rr0 = *cs->cs_reg_csr; 557 ZS_DELAY(); 558 } while (rr0 & ZSRR0_BREAK); 559 560 #ifdef DDB 561 Debugger(); 562 #else 563 printf ("BREAK!!\n"); 564 #endif 565 } 566 567 568 #if NZSTTY > 0 569 570 #include <dev/cons.h> 571 cons_decl(zs); 572 573 static int zs_getc __P((void)); 574 static void zs_putc __P((int)); 575 576 /* 577 * Polled input char. 578 */ 579 static int 580 zs_getc(void) 581 { 582 register int s, c, rr0; 583 584 s = splzs(); 585 /* Wait for a character to arrive. */ 586 do { 587 rr0 = zs_read_csr(&zscn_cs); 588 } while ((rr0 & ZSRR0_RX_READY) == 0); 589 590 c = zs_read_data (&zscn_cs); 591 splx(s); 592 593 /* 594 * This is used by the kd driver to read scan codes, 595 * so don't translate '\r' ==> '\n' here... 596 */ 597 return (c); 598 } 599 600 /* 601 * Polled output char. 602 */ 603 static void 604 zs_putc(c) 605 int c; 606 { 607 register int s, rr0; 608 609 s = splzs(); 610 /* Wait for transmitter to become ready. */ 611 do { 612 rr0 = zs_read_csr (&zscn_cs); 613 } while ((rr0 & ZSRR0_TX_READY) == 0); 614 615 zs_write_data(&zscn_cs, c); 616 splx(s); 617 } 618 619 void 620 zscninit(cn) 621 struct consdev *cn; 622 { 623 volatile struct zschan *cnchan = (void*) INTIO_ADDR(ZSCN_PHYSADDR); 624 int s; 625 626 bzero (&zscn_cs, sizeof (struct zs_chanstate)); 627 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 628 zscn_cs.cs_reg_data = &cnchan->zc_data; 629 zscn_cs.cs_channel = 0; 630 zscn_cs.cs_brg_clk = PCLK / 16; 631 bcopy (zs_init_reg, zscn_cs.cs_preg, 16); 632 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 633 zscn_cs.cs_preg[9] = 0; 634 zs_set_speed(&zscn_cs, ZSCN_SPEED); 635 s = splzs(); 636 zs_loadchannelregs(&zscn_cs); 637 splx(s); 638 conschan = cnchan; 639 } 640 641 /* 642 * Polled console input putchar. 643 */ 644 int 645 zscngetc(dev) 646 dev_t dev; 647 { 648 return (zs_getc()); 649 } 650 651 /* 652 * Polled console output putchar. 653 */ 654 void 655 zscnputc(dev, c) 656 dev_t dev; 657 int c; 658 { 659 zs_putc(c); 660 } 661 662 extern int zsopen(dev_t, int, int, struct proc *); 663 664 void 665 zscnprobe(cd) 666 struct consdev *cd; 667 { 668 int maj; 669 670 /* locate the major number */ 671 for (maj = 0; maj < nchrdev; maj++) 672 if (cdevsw[maj].d_open == zsopen) 673 break; 674 /* XXX: minor number is 0 */ 675 676 if (cdevsw[maj].d_open != zsopen) 677 cd->cn_pri = CN_DEAD; 678 else { 679 #ifdef ZSCONSOLE 680 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 681 #else 682 cd->cn_pri = CN_NORMAL; 683 #endif 684 cd->cn_dev = makedev(maj, 0); 685 } 686 } 687 688 void 689 zscnpollc(dev, on) 690 dev_t dev; 691 int on; 692 { 693 } 694 695 #endif 696
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