zs.c revision 1.24
1 /* $NetBSD: zs.c,v 1.24 2003/01/28 12:35:38 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/cpu.h> 62 #include <machine/bus.h> 63 #include <arch/x68k/dev/intiovar.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/ic/z8530reg.h> 67 68 #include "zsc.h" /* NZSC */ 69 #include "opt_zsc.h" 70 #ifndef ZSCN_SPEED 71 #define ZSCN_SPEED 9600 72 #endif 73 #include "zstty.h" 74 75 76 extern void Debugger __P((void)); 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 85 86 /* 87 * X68k provides a 5.0 MHz clock to the ZS chips. 88 */ 89 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 90 91 92 /* Default physical addresses. */ 93 #define ZS_MAXDEV 5 94 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 95 0x00e98000, 96 0x00eafc00, 97 0x00eafc10, 98 0x00eafc20, 99 0x00eafc30 100 }; 101 102 static u_char zs_init_reg[16] = { 103 0, /* 0: CMD (reset, etc.) */ 104 0, /* 1: No interrupts yet. */ 105 0x70, /* 2: XXX: IVECT */ 106 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 107 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 108 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 109 0, /* 6: TXSYNC/SYNCLO */ 110 0, /* 7: RXSYNC/SYNCHI */ 111 0, /* 8: alias for data port */ 112 ZSWR9_MASTER_IE, 113 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 114 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 115 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 116 0, /*13: BAUDHI (default=9600) */ 117 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 118 ZSWR15_BREAK_IE, 119 }; 120 121 static volatile struct zschan *conschan = 0; 122 123 124 /**************************************************************** 125 * Autoconfig 126 ****************************************************************/ 127 128 /* Definition of the driver for autoconfig. */ 129 static int zs_match __P((struct device *, struct cfdata *, void *)); 130 static void zs_attach __P((struct device *, struct device *, void *)); 131 static int zs_print __P((void *, const char *name)); 132 133 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 134 zs_match, zs_attach, NULL, NULL); 135 136 extern struct cfdriver zsc_cd; 137 138 static int zshard __P((void *)); 139 int zssoft __P((void *)); 140 static int zs_get_speed __P((struct zs_chanstate *)); 141 142 143 /* 144 * Is the zs chip present? 145 */ 146 static int 147 zs_match(parent, cf, aux) 148 struct device *parent; 149 struct cfdata *cf; 150 void *aux; 151 { 152 struct intio_attach_args *ia = aux; 153 struct zsdevice *zsaddr = (void*) ia->ia_addr; 154 int i; 155 156 if (strcmp (ia->ia_name, "zsc") != 0) 157 return 0; 158 159 for (i = 0; i < ZS_MAXDEV; i++) 160 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 161 break; 162 163 ia->ia_size = 8; 164 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 165 return 0; 166 167 if (zsaddr != (void*) zs_physaddr[i]) 168 return 0; 169 if (badaddr((caddr_t)INTIO_ADDR(zsaddr))) 170 return 0; 171 172 return (1); 173 } 174 175 /* 176 * Attach a found zs. 177 */ 178 static void 179 zs_attach(parent, self, aux) 180 struct device *parent; 181 struct device *self; 182 void *aux; 183 { 184 struct zsc_softc *zsc = (void *) self; 185 struct intio_attach_args *ia = aux; 186 struct zsc_attach_args zsc_args; 187 volatile struct zschan *zc; 188 struct zs_chanstate *cs; 189 int r, s, zs_unit, channel; 190 191 zs_unit = zsc->zsc_dev.dv_unit; 192 zsc->zsc_addr = (void*) ia->ia_addr; 193 194 ia->ia_size = 8; 195 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 196 #ifdef DIAGNOSTIC 197 if (r) 198 panic ("zs: intio IO map corruption"); 199 #endif 200 201 printf("\n"); 202 203 /* 204 * Initialize software state for each channel. 205 */ 206 for (channel = 0; channel < 2; channel++) { 207 struct device *child; 208 209 zsc_args.channel = channel; 210 zsc_args.hwflags = 0; 211 cs = &zsc->zsc_cs_store[channel]; 212 zsc->zsc_cs[channel] = cs; 213 214 simple_lock_init(&cs->cs_lock); 215 cs->cs_channel = channel; 216 cs->cs_private = NULL; 217 cs->cs_ops = &zsops_null; 218 cs->cs_brg_clk = PCLK / 16; 219 220 if (channel == 0) 221 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 222 else 223 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 224 cs->cs_reg_csr = &zc->zc_csr; 225 cs->cs_reg_data = &zc->zc_data; 226 227 zs_init_reg[2] = ia->ia_intr; 228 memcpy(cs->cs_creg, zs_init_reg, 16); 229 memcpy(cs->cs_preg, zs_init_reg, 16); 230 231 if (zc == conschan) { 232 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 233 cs->cs_defspeed = zs_get_speed(cs); 234 cs->cs_defcflag = zscn_def_cflag; 235 } else { 236 cs->cs_defspeed = 9600; 237 cs->cs_defcflag = zs_def_cflag; 238 } 239 240 /* Make these correspond to cs_defcflag (-crtscts) */ 241 cs->cs_rr0_dcd = ZSRR0_DCD; 242 cs->cs_rr0_cts = 0; 243 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 244 cs->cs_wr5_rts = 0; 245 246 /* 247 * Clear the master interrupt enable. 248 * The INTENA is common to both channels, 249 * so just do it on the A channel. 250 */ 251 if (channel == 0) { 252 s = splzs(); 253 zs_write_reg(cs, 9, 0); 254 splx(s); 255 } 256 257 /* 258 * Look for a child driver for this channel. 259 * The child attach will setup the hardware. 260 */ 261 child = config_found(self, (void *)&zsc_args, zs_print); 262 #if ZSTTY > 0 263 if (zc == conschan && 264 ((child && strcmp (child->dv_xname, "zstty0")) || 265 child == NULL)) /* XXX */ 266 panic ("zs_attach: console device mismatch"); 267 #endif 268 if (child == NULL) { 269 /* No sub-driver. Just reset it. */ 270 u_char reset = (channel == 0) ? 271 ZSWR9_A_RESET : ZSWR9_B_RESET; 272 s = splzs(); 273 zs_write_reg(cs, 9, reset); 274 splx(s); 275 } 276 } 277 278 /* 279 * Now safe to install interrupt handlers. 280 */ 281 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 282 panic("zs_attach: interrupt vector busy"); 283 /* XXX; evcnt_attach() ? */ 284 285 /* 286 * Set the master interrupt enable and interrupt vector. 287 * (common to both channels, do it on A) 288 */ 289 cs = zsc->zsc_cs[0]; 290 s = splzs(); 291 /* interrupt vector */ 292 zs_write_reg(cs, 2, ia->ia_intr); 293 /* master interrupt control (enable) */ 294 zs_write_reg(cs, 9, zs_init_reg[9]); 295 splx(s); 296 } 297 298 static int 299 zs_print(aux, name) 300 void *aux; 301 const char *name; 302 { 303 struct zsc_attach_args *args = aux; 304 305 if (name != NULL) 306 aprint_normal("%s: ", name); 307 308 if (args->channel != -1) 309 aprint_normal(" channel %d", args->channel); 310 311 return UNCONF; 312 } 313 314 315 /* 316 * For x68k-port, we don't use autovectored interrupt. 317 * We do not need to look at all of the zs chips. 318 */ 319 static int 320 zshard(arg) 321 void *arg; 322 { 323 register struct zsc_softc *zsc = arg; 324 register int rval; 325 int s; 326 327 /* 328 * Actually, zs hardware ipl is 5. 329 * Here we disable all interrupts to shorten the zshard 330 * handling time. Otherwise, too many characters are 331 * dropped. 332 */ 333 s = splhigh(); 334 rval = zsc_intr_hard(zsc); 335 336 /* We are at splzs here, so no need to lock. */ 337 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 338 setsoftserial(); 339 340 return (rval); 341 } 342 343 /* 344 * Shared among the all chips. We have to look at all of them. 345 */ 346 int 347 zssoft(arg) 348 void *arg; 349 { 350 register struct zsc_softc *zsc; 351 register int s, unit; 352 353 /* Make sure we call the tty layer at spltty. */ 354 s = spltty(); 355 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 356 zsc = zsc_cd.cd_devs[unit]; 357 if (zsc == NULL) 358 continue; 359 (void) zsc_intr_soft(zsc); 360 } 361 splx(s); 362 363 return (1); 364 } 365 366 367 /* 368 * Compute the current baud rate given a ZS channel. 369 */ 370 static int 371 zs_get_speed(cs) 372 struct zs_chanstate *cs; 373 { 374 int tconst; 375 376 tconst = zs_read_reg(cs, 12); 377 tconst |= zs_read_reg(cs, 13) << 8; 378 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 379 } 380 381 /* 382 * MD functions for setting the baud rate and control modes. 383 */ 384 int 385 zs_set_speed(cs, bps) 386 struct zs_chanstate *cs; 387 int bps; /* bits per second */ 388 { 389 int tconst, real_bps; 390 391 if (bps == 0) 392 return (0); 393 394 #ifdef DIAGNOSTIC 395 if (cs->cs_brg_clk == 0) 396 panic("zs_set_speed"); 397 #endif 398 399 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 400 if (tconst < 0) 401 return (EINVAL); 402 403 /* Convert back to make sure we can do it. */ 404 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 405 406 #if 0 /* XXX */ 407 /* XXX - Allow some tolerance here? */ 408 if (real_bps != bps) 409 return (EINVAL); 410 #else 411 /* 412 * Since our PCLK has somewhat strange value, 413 * we have to allow tolerance here. 414 */ 415 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 416 return (EINVAL); 417 #endif 418 419 cs->cs_preg[12] = tconst; 420 cs->cs_preg[13] = tconst >> 8; 421 422 /* Caller will stuff the pending registers. */ 423 return (0); 424 } 425 426 int 427 zs_set_modes(cs, cflag) 428 struct zs_chanstate *cs; 429 int cflag; /* bits per second */ 430 { 431 int s; 432 433 /* 434 * Output hardware flow control on the chip is horrendous: 435 * if carrier detect drops, the receiver is disabled, and if 436 * CTS drops, the transmitter is stoped IN MID CHARACTER! 437 * Therefore, NEVER set the HFC bit, and instead use the 438 * status interrupt to detect CTS changes. 439 */ 440 s = splzs(); 441 cs->cs_rr0_pps = 0; 442 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 443 cs->cs_rr0_dcd = 0; 444 if ((cflag & MDMBUF) == 0) 445 cs->cs_rr0_pps = ZSRR0_DCD; 446 } else 447 cs->cs_rr0_dcd = ZSRR0_DCD; 448 if ((cflag & CRTSCTS) != 0) { 449 cs->cs_wr5_dtr = ZSWR5_DTR; 450 cs->cs_wr5_rts = ZSWR5_RTS; 451 cs->cs_rr0_cts = ZSRR0_CTS; 452 } else if ((cflag & MDMBUF) != 0) { 453 cs->cs_wr5_dtr = 0; 454 cs->cs_wr5_rts = ZSWR5_DTR; 455 cs->cs_rr0_cts = ZSRR0_DCD; 456 } else { 457 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 458 cs->cs_wr5_rts = 0; 459 cs->cs_rr0_cts = 0; 460 } 461 splx(s); 462 463 /* Caller will stuff the pending registers. */ 464 return (0); 465 } 466 467 468 /* 469 * Read or write the chip with suitable delays. 470 */ 471 472 u_char 473 zs_read_reg(cs, reg) 474 struct zs_chanstate *cs; 475 u_char reg; 476 { 477 u_char val; 478 479 *cs->cs_reg_csr = reg; 480 ZS_DELAY(); 481 val = *cs->cs_reg_csr; 482 ZS_DELAY(); 483 return val; 484 } 485 486 void 487 zs_write_reg(cs, reg, val) 488 struct zs_chanstate *cs; 489 u_char reg, val; 490 { 491 *cs->cs_reg_csr = reg; 492 ZS_DELAY(); 493 *cs->cs_reg_csr = val; 494 ZS_DELAY(); 495 } 496 497 u_char zs_read_csr(cs) 498 struct zs_chanstate *cs; 499 { 500 register u_char val; 501 502 val = *cs->cs_reg_csr; 503 ZS_DELAY(); 504 return val; 505 } 506 507 void zs_write_csr(cs, val) 508 struct zs_chanstate *cs; 509 u_char val; 510 { 511 *cs->cs_reg_csr = val; 512 ZS_DELAY(); 513 } 514 515 u_char zs_read_data(cs) 516 struct zs_chanstate *cs; 517 { 518 register u_char val; 519 520 val = *cs->cs_reg_data; 521 ZS_DELAY(); 522 return val; 523 } 524 525 void zs_write_data(cs, val) 526 struct zs_chanstate *cs; 527 u_char val; 528 { 529 *cs->cs_reg_data = val; 530 ZS_DELAY(); 531 } 532 533 534 static struct zs_chanstate zscn_cs; 535 536 /**************************************************************** 537 * Console support functions (x68k specific!) 538 * Note: this code is allowed to know about the layout of 539 * the chip registers, and uses that to keep things simple. 540 * XXX - I think I like the mvme167 code better. -gwr 541 ****************************************************************/ 542 543 /* 544 * Handle user request to enter kernel debugger. 545 */ 546 void 547 zs_abort(cs) 548 struct zs_chanstate *cs; 549 { 550 int rr0; 551 552 /* Wait for end of break to avoid PROM abort. */ 553 /* XXX - Limit the wait? */ 554 do { 555 rr0 = *cs->cs_reg_csr; 556 ZS_DELAY(); 557 } while (rr0 & ZSRR0_BREAK); 558 559 #ifdef DDB 560 Debugger(); 561 #else 562 printf ("BREAK!!\n"); 563 #endif 564 } 565 566 567 #if NZSTTY > 0 568 569 #include <dev/cons.h> 570 cons_decl(zs); 571 572 static int zs_getc __P((void)); 573 static void zs_putc __P((int)); 574 575 /* 576 * Polled input char. 577 */ 578 static int 579 zs_getc(void) 580 { 581 register int s, c, rr0; 582 583 s = splzs(); 584 /* Wait for a character to arrive. */ 585 do { 586 rr0 = zs_read_csr(&zscn_cs); 587 } while ((rr0 & ZSRR0_RX_READY) == 0); 588 589 c = zs_read_data (&zscn_cs); 590 splx(s); 591 592 /* 593 * This is used by the kd driver to read scan codes, 594 * so don't translate '\r' ==> '\n' here... 595 */ 596 return (c); 597 } 598 599 /* 600 * Polled output char. 601 */ 602 static void 603 zs_putc(c) 604 int c; 605 { 606 register int s, rr0; 607 608 s = splzs(); 609 /* Wait for transmitter to become ready. */ 610 do { 611 rr0 = zs_read_csr (&zscn_cs); 612 } while ((rr0 & ZSRR0_TX_READY) == 0); 613 614 zs_write_data(&zscn_cs, c); 615 splx(s); 616 } 617 618 void 619 zscninit(cn) 620 struct consdev *cn; 621 { 622 volatile struct zschan *cnchan = (void*) INTIO_ADDR(ZSCN_PHYSADDR); 623 int s; 624 625 memset(&zscn_cs, 0, sizeof (struct zs_chanstate)); 626 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 627 zscn_cs.cs_reg_data = &cnchan->zc_data; 628 zscn_cs.cs_channel = 0; 629 zscn_cs.cs_brg_clk = PCLK / 16; 630 memcpy(zscn_cs.cs_preg, zs_init_reg, 16); 631 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 632 zscn_cs.cs_preg[9] = 0; 633 zs_set_speed(&zscn_cs, ZSCN_SPEED); 634 s = splzs(); 635 zs_loadchannelregs(&zscn_cs); 636 splx(s); 637 conschan = cnchan; 638 } 639 640 /* 641 * Polled console input putchar. 642 */ 643 int 644 zscngetc(dev) 645 dev_t dev; 646 { 647 return (zs_getc()); 648 } 649 650 /* 651 * Polled console output putchar. 652 */ 653 void 654 zscnputc(dev, c) 655 dev_t dev; 656 int c; 657 { 658 zs_putc(c); 659 } 660 661 void 662 zscnprobe(cd) 663 struct consdev *cd; 664 { 665 int maj; 666 extern const struct cdevsw zstty_cdevsw; 667 668 /* locate the major number */ 669 maj = cdevsw_lookup_major(&zstty_cdevsw); 670 /* XXX: minor number is 0 */ 671 672 if (maj == -1) 673 cd->cn_pri = CN_DEAD; 674 else { 675 #ifdef ZSCONSOLE 676 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 677 #else 678 cd->cn_pri = CN_NORMAL; 679 #endif 680 cd->cn_dev = makedev(maj, 0); 681 } 682 } 683 684 void 685 zscnpollc(dev, on) 686 dev_t dev; 687 int on; 688 { 689 } 690 691 #endif 692
Indexes created Sun Sep 28 16:09:52 GMT 2025