zs.c revision 1.25
1 /* $NetBSD: zs.c,v 1.25 2003/07/15 01:44:53 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.25 2003/07/15 01:44:53 lukem Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <arch/x68k/dev/intiovar.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/ic/z8530reg.h> 70 71 #include "zsc.h" /* NZSC */ 72 #include "opt_zsc.h" 73 #ifndef ZSCN_SPEED 74 #define ZSCN_SPEED 9600 75 #endif 76 #include "zstty.h" 77 78 79 extern void Debugger __P((void)); 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 88 89 /* 90 * X68k provides a 5.0 MHz clock to the ZS chips. 91 */ 92 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 93 94 95 /* Default physical addresses. */ 96 #define ZS_MAXDEV 5 97 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 98 0x00e98000, 99 0x00eafc00, 100 0x00eafc10, 101 0x00eafc20, 102 0x00eafc30 103 }; 104 105 static u_char zs_init_reg[16] = { 106 0, /* 0: CMD (reset, etc.) */ 107 0, /* 1: No interrupts yet. */ 108 0x70, /* 2: XXX: IVECT */ 109 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 110 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 111 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 112 0, /* 6: TXSYNC/SYNCLO */ 113 0, /* 7: RXSYNC/SYNCHI */ 114 0, /* 8: alias for data port */ 115 ZSWR9_MASTER_IE, 116 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 117 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 118 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 119 0, /*13: BAUDHI (default=9600) */ 120 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 121 ZSWR15_BREAK_IE, 122 }; 123 124 static volatile struct zschan *conschan = 0; 125 126 127 /**************************************************************** 128 * Autoconfig 129 ****************************************************************/ 130 131 /* Definition of the driver for autoconfig. */ 132 static int zs_match __P((struct device *, struct cfdata *, void *)); 133 static void zs_attach __P((struct device *, struct device *, void *)); 134 static int zs_print __P((void *, const char *name)); 135 136 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 137 zs_match, zs_attach, NULL, NULL); 138 139 extern struct cfdriver zsc_cd; 140 141 static int zshard __P((void *)); 142 int zssoft __P((void *)); 143 static int zs_get_speed __P((struct zs_chanstate *)); 144 145 146 /* 147 * Is the zs chip present? 148 */ 149 static int 150 zs_match(parent, cf, aux) 151 struct device *parent; 152 struct cfdata *cf; 153 void *aux; 154 { 155 struct intio_attach_args *ia = aux; 156 struct zsdevice *zsaddr = (void*) ia->ia_addr; 157 int i; 158 159 if (strcmp (ia->ia_name, "zsc") != 0) 160 return 0; 161 162 for (i = 0; i < ZS_MAXDEV; i++) 163 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 164 break; 165 166 ia->ia_size = 8; 167 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 168 return 0; 169 170 if (zsaddr != (void*) zs_physaddr[i]) 171 return 0; 172 if (badaddr((caddr_t)INTIO_ADDR(zsaddr))) 173 return 0; 174 175 return (1); 176 } 177 178 /* 179 * Attach a found zs. 180 */ 181 static void 182 zs_attach(parent, self, aux) 183 struct device *parent; 184 struct device *self; 185 void *aux; 186 { 187 struct zsc_softc *zsc = (void *) self; 188 struct intio_attach_args *ia = aux; 189 struct zsc_attach_args zsc_args; 190 volatile struct zschan *zc; 191 struct zs_chanstate *cs; 192 int r, s, zs_unit, channel; 193 194 zs_unit = zsc->zsc_dev.dv_unit; 195 zsc->zsc_addr = (void*) ia->ia_addr; 196 197 ia->ia_size = 8; 198 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 199 #ifdef DIAGNOSTIC 200 if (r) 201 panic ("zs: intio IO map corruption"); 202 #endif 203 204 printf("\n"); 205 206 /* 207 * Initialize software state for each channel. 208 */ 209 for (channel = 0; channel < 2; channel++) { 210 struct device *child; 211 212 zsc_args.channel = channel; 213 zsc_args.hwflags = 0; 214 cs = &zsc->zsc_cs_store[channel]; 215 zsc->zsc_cs[channel] = cs; 216 217 simple_lock_init(&cs->cs_lock); 218 cs->cs_channel = channel; 219 cs->cs_private = NULL; 220 cs->cs_ops = &zsops_null; 221 cs->cs_brg_clk = PCLK / 16; 222 223 if (channel == 0) 224 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 225 else 226 zc = (void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 227 cs->cs_reg_csr = &zc->zc_csr; 228 cs->cs_reg_data = &zc->zc_data; 229 230 zs_init_reg[2] = ia->ia_intr; 231 memcpy(cs->cs_creg, zs_init_reg, 16); 232 memcpy(cs->cs_preg, zs_init_reg, 16); 233 234 if (zc == conschan) { 235 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 236 cs->cs_defspeed = zs_get_speed(cs); 237 cs->cs_defcflag = zscn_def_cflag; 238 } else { 239 cs->cs_defspeed = 9600; 240 cs->cs_defcflag = zs_def_cflag; 241 } 242 243 /* Make these correspond to cs_defcflag (-crtscts) */ 244 cs->cs_rr0_dcd = ZSRR0_DCD; 245 cs->cs_rr0_cts = 0; 246 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 247 cs->cs_wr5_rts = 0; 248 249 /* 250 * Clear the master interrupt enable. 251 * The INTENA is common to both channels, 252 * so just do it on the A channel. 253 */ 254 if (channel == 0) { 255 s = splzs(); 256 zs_write_reg(cs, 9, 0); 257 splx(s); 258 } 259 260 /* 261 * Look for a child driver for this channel. 262 * The child attach will setup the hardware. 263 */ 264 child = config_found(self, (void *)&zsc_args, zs_print); 265 #if ZSTTY > 0 266 if (zc == conschan && 267 ((child && strcmp (child->dv_xname, "zstty0")) || 268 child == NULL)) /* XXX */ 269 panic ("zs_attach: console device mismatch"); 270 #endif 271 if (child == NULL) { 272 /* No sub-driver. Just reset it. */ 273 u_char reset = (channel == 0) ? 274 ZSWR9_A_RESET : ZSWR9_B_RESET; 275 s = splzs(); 276 zs_write_reg(cs, 9, reset); 277 splx(s); 278 } 279 } 280 281 /* 282 * Now safe to install interrupt handlers. 283 */ 284 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 285 panic("zs_attach: interrupt vector busy"); 286 /* XXX; evcnt_attach() ? */ 287 288 /* 289 * Set the master interrupt enable and interrupt vector. 290 * (common to both channels, do it on A) 291 */ 292 cs = zsc->zsc_cs[0]; 293 s = splzs(); 294 /* interrupt vector */ 295 zs_write_reg(cs, 2, ia->ia_intr); 296 /* master interrupt control (enable) */ 297 zs_write_reg(cs, 9, zs_init_reg[9]); 298 splx(s); 299 } 300 301 static int 302 zs_print(aux, name) 303 void *aux; 304 const char *name; 305 { 306 struct zsc_attach_args *args = aux; 307 308 if (name != NULL) 309 aprint_normal("%s: ", name); 310 311 if (args->channel != -1) 312 aprint_normal(" channel %d", args->channel); 313 314 return UNCONF; 315 } 316 317 318 /* 319 * For x68k-port, we don't use autovectored interrupt. 320 * We do not need to look at all of the zs chips. 321 */ 322 static int 323 zshard(arg) 324 void *arg; 325 { 326 register struct zsc_softc *zsc = arg; 327 register int rval; 328 int s; 329 330 /* 331 * Actually, zs hardware ipl is 5. 332 * Here we disable all interrupts to shorten the zshard 333 * handling time. Otherwise, too many characters are 334 * dropped. 335 */ 336 s = splhigh(); 337 rval = zsc_intr_hard(zsc); 338 339 /* We are at splzs here, so no need to lock. */ 340 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 341 setsoftserial(); 342 343 return (rval); 344 } 345 346 /* 347 * Shared among the all chips. We have to look at all of them. 348 */ 349 int 350 zssoft(arg) 351 void *arg; 352 { 353 register struct zsc_softc *zsc; 354 register int s, unit; 355 356 /* Make sure we call the tty layer at spltty. */ 357 s = spltty(); 358 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 359 zsc = zsc_cd.cd_devs[unit]; 360 if (zsc == NULL) 361 continue; 362 (void) zsc_intr_soft(zsc); 363 } 364 splx(s); 365 366 return (1); 367 } 368 369 370 /* 371 * Compute the current baud rate given a ZS channel. 372 */ 373 static int 374 zs_get_speed(cs) 375 struct zs_chanstate *cs; 376 { 377 int tconst; 378 379 tconst = zs_read_reg(cs, 12); 380 tconst |= zs_read_reg(cs, 13) << 8; 381 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 382 } 383 384 /* 385 * MD functions for setting the baud rate and control modes. 386 */ 387 int 388 zs_set_speed(cs, bps) 389 struct zs_chanstate *cs; 390 int bps; /* bits per second */ 391 { 392 int tconst, real_bps; 393 394 if (bps == 0) 395 return (0); 396 397 #ifdef DIAGNOSTIC 398 if (cs->cs_brg_clk == 0) 399 panic("zs_set_speed"); 400 #endif 401 402 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 403 if (tconst < 0) 404 return (EINVAL); 405 406 /* Convert back to make sure we can do it. */ 407 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 408 409 #if 0 /* XXX */ 410 /* XXX - Allow some tolerance here? */ 411 if (real_bps != bps) 412 return (EINVAL); 413 #else 414 /* 415 * Since our PCLK has somewhat strange value, 416 * we have to allow tolerance here. 417 */ 418 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 419 return (EINVAL); 420 #endif 421 422 cs->cs_preg[12] = tconst; 423 cs->cs_preg[13] = tconst >> 8; 424 425 /* Caller will stuff the pending registers. */ 426 return (0); 427 } 428 429 int 430 zs_set_modes(cs, cflag) 431 struct zs_chanstate *cs; 432 int cflag; /* bits per second */ 433 { 434 int s; 435 436 /* 437 * Output hardware flow control on the chip is horrendous: 438 * if carrier detect drops, the receiver is disabled, and if 439 * CTS drops, the transmitter is stoped IN MID CHARACTER! 440 * Therefore, NEVER set the HFC bit, and instead use the 441 * status interrupt to detect CTS changes. 442 */ 443 s = splzs(); 444 cs->cs_rr0_pps = 0; 445 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 446 cs->cs_rr0_dcd = 0; 447 if ((cflag & MDMBUF) == 0) 448 cs->cs_rr0_pps = ZSRR0_DCD; 449 } else 450 cs->cs_rr0_dcd = ZSRR0_DCD; 451 if ((cflag & CRTSCTS) != 0) { 452 cs->cs_wr5_dtr = ZSWR5_DTR; 453 cs->cs_wr5_rts = ZSWR5_RTS; 454 cs->cs_rr0_cts = ZSRR0_CTS; 455 } else if ((cflag & MDMBUF) != 0) { 456 cs->cs_wr5_dtr = 0; 457 cs->cs_wr5_rts = ZSWR5_DTR; 458 cs->cs_rr0_cts = ZSRR0_DCD; 459 } else { 460 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 461 cs->cs_wr5_rts = 0; 462 cs->cs_rr0_cts = 0; 463 } 464 splx(s); 465 466 /* Caller will stuff the pending registers. */ 467 return (0); 468 } 469 470 471 /* 472 * Read or write the chip with suitable delays. 473 */ 474 475 u_char 476 zs_read_reg(cs, reg) 477 struct zs_chanstate *cs; 478 u_char reg; 479 { 480 u_char val; 481 482 *cs->cs_reg_csr = reg; 483 ZS_DELAY(); 484 val = *cs->cs_reg_csr; 485 ZS_DELAY(); 486 return val; 487 } 488 489 void 490 zs_write_reg(cs, reg, val) 491 struct zs_chanstate *cs; 492 u_char reg, val; 493 { 494 *cs->cs_reg_csr = reg; 495 ZS_DELAY(); 496 *cs->cs_reg_csr = val; 497 ZS_DELAY(); 498 } 499 500 u_char zs_read_csr(cs) 501 struct zs_chanstate *cs; 502 { 503 register u_char val; 504 505 val = *cs->cs_reg_csr; 506 ZS_DELAY(); 507 return val; 508 } 509 510 void zs_write_csr(cs, val) 511 struct zs_chanstate *cs; 512 u_char val; 513 { 514 *cs->cs_reg_csr = val; 515 ZS_DELAY(); 516 } 517 518 u_char zs_read_data(cs) 519 struct zs_chanstate *cs; 520 { 521 register u_char val; 522 523 val = *cs->cs_reg_data; 524 ZS_DELAY(); 525 return val; 526 } 527 528 void zs_write_data(cs, val) 529 struct zs_chanstate *cs; 530 u_char val; 531 { 532 *cs->cs_reg_data = val; 533 ZS_DELAY(); 534 } 535 536 537 static struct zs_chanstate zscn_cs; 538 539 /**************************************************************** 540 * Console support functions (x68k specific!) 541 * Note: this code is allowed to know about the layout of 542 * the chip registers, and uses that to keep things simple. 543 * XXX - I think I like the mvme167 code better. -gwr 544 ****************************************************************/ 545 546 /* 547 * Handle user request to enter kernel debugger. 548 */ 549 void 550 zs_abort(cs) 551 struct zs_chanstate *cs; 552 { 553 int rr0; 554 555 /* Wait for end of break to avoid PROM abort. */ 556 /* XXX - Limit the wait? */ 557 do { 558 rr0 = *cs->cs_reg_csr; 559 ZS_DELAY(); 560 } while (rr0 & ZSRR0_BREAK); 561 562 #ifdef DDB 563 Debugger(); 564 #else 565 printf ("BREAK!!\n"); 566 #endif 567 } 568 569 570 #if NZSTTY > 0 571 572 #include <dev/cons.h> 573 cons_decl(zs); 574 575 static int zs_getc __P((void)); 576 static void zs_putc __P((int)); 577 578 /* 579 * Polled input char. 580 */ 581 static int 582 zs_getc(void) 583 { 584 register int s, c, rr0; 585 586 s = splzs(); 587 /* Wait for a character to arrive. */ 588 do { 589 rr0 = zs_read_csr(&zscn_cs); 590 } while ((rr0 & ZSRR0_RX_READY) == 0); 591 592 c = zs_read_data (&zscn_cs); 593 splx(s); 594 595 /* 596 * This is used by the kd driver to read scan codes, 597 * so don't translate '\r' ==> '\n' here... 598 */ 599 return (c); 600 } 601 602 /* 603 * Polled output char. 604 */ 605 static void 606 zs_putc(c) 607 int c; 608 { 609 register int s, rr0; 610 611 s = splzs(); 612 /* Wait for transmitter to become ready. */ 613 do { 614 rr0 = zs_read_csr (&zscn_cs); 615 } while ((rr0 & ZSRR0_TX_READY) == 0); 616 617 zs_write_data(&zscn_cs, c); 618 splx(s); 619 } 620 621 void 622 zscninit(cn) 623 struct consdev *cn; 624 { 625 volatile struct zschan *cnchan = (void*) INTIO_ADDR(ZSCN_PHYSADDR); 626 int s; 627 628 memset(&zscn_cs, 0, sizeof (struct zs_chanstate)); 629 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 630 zscn_cs.cs_reg_data = &cnchan->zc_data; 631 zscn_cs.cs_channel = 0; 632 zscn_cs.cs_brg_clk = PCLK / 16; 633 memcpy(zscn_cs.cs_preg, zs_init_reg, 16); 634 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 635 zscn_cs.cs_preg[9] = 0; 636 zs_set_speed(&zscn_cs, ZSCN_SPEED); 637 s = splzs(); 638 zs_loadchannelregs(&zscn_cs); 639 splx(s); 640 conschan = cnchan; 641 } 642 643 /* 644 * Polled console input putchar. 645 */ 646 int 647 zscngetc(dev) 648 dev_t dev; 649 { 650 return (zs_getc()); 651 } 652 653 /* 654 * Polled console output putchar. 655 */ 656 void 657 zscnputc(dev, c) 658 dev_t dev; 659 int c; 660 { 661 zs_putc(c); 662 } 663 664 void 665 zscnprobe(cd) 666 struct consdev *cd; 667 { 668 int maj; 669 extern const struct cdevsw zstty_cdevsw; 670 671 /* locate the major number */ 672 maj = cdevsw_lookup_major(&zstty_cdevsw); 673 /* XXX: minor number is 0 */ 674 675 if (maj == -1) 676 cd->cn_pri = CN_DEAD; 677 else { 678 #ifdef ZSCONSOLE 679 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 680 #else 681 cd->cn_pri = CN_NORMAL; 682 #endif 683 cd->cn_dev = makedev(maj, 0); 684 } 685 } 686 687 void 688 zscnpollc(dev, on) 689 dev_t dev; 690 int on; 691 { 692 } 693 694 #endif 695
Indexes created Sun Sep 28 16:09:52 GMT 2025