zs.c revision 1.29
1 /* $NetBSD: zs.c,v 1.29 2006/03/28 17:38:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.29 2006/03/28 17:38:28 thorpej Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <arch/x68k/dev/intiovar.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/ic/z8530reg.h> 70 71 #include "zsc.h" /* NZSC */ 72 #include "opt_zsc.h" 73 #ifndef ZSCN_SPEED 74 #define ZSCN_SPEED 9600 75 #endif 76 #include "zstty.h" 77 78 79 extern void Debugger(void); 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 88 89 /* 90 * X68k provides a 5.0 MHz clock to the ZS chips. 91 */ 92 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 93 94 95 /* Default physical addresses. */ 96 #define ZS_MAXDEV 5 97 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 98 0x00e98000, 99 0x00eafc00, 100 0x00eafc10, 101 0x00eafc20, 102 0x00eafc30 103 }; 104 105 static u_char zs_init_reg[16] = { 106 0, /* 0: CMD (reset, etc.) */ 107 0, /* 1: No interrupts yet. */ 108 0x70, /* 2: XXX: IVECT */ 109 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 110 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 111 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 112 0, /* 6: TXSYNC/SYNCLO */ 113 0, /* 7: RXSYNC/SYNCHI */ 114 0, /* 8: alias for data port */ 115 ZSWR9_MASTER_IE, 116 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 117 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 118 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 119 0, /*13: BAUDHI (default=9600) */ 120 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 121 ZSWR15_BREAK_IE, 122 }; 123 124 static volatile struct zschan *conschan = 0; 125 126 127 /**************************************************************** 128 * Autoconfig 129 ****************************************************************/ 130 131 /* Definition of the driver for autoconfig. */ 132 static int zs_match(struct device *, struct cfdata *, void *); 133 static void zs_attach(struct device *, struct device *, void *); 134 static int zs_print(void *, const char *name); 135 136 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 137 zs_match, zs_attach, NULL, NULL); 138 139 extern struct cfdriver zsc_cd; 140 141 static int zshard(void *); 142 int zssoft(void *); 143 static int zs_get_speed(struct zs_chanstate *); 144 145 146 /* 147 * Is the zs chip present? 148 */ 149 static int 150 zs_match(struct device *parent, struct cfdata *cf, void *aux) 151 { 152 struct intio_attach_args *ia = aux; 153 struct zsdevice *zsaddr = (void*) ia->ia_addr; 154 int i; 155 156 if (strcmp (ia->ia_name, "zsc") != 0) 157 return 0; 158 159 for (i = 0; i < ZS_MAXDEV; i++) 160 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 161 break; 162 163 ia->ia_size = 8; 164 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 165 return 0; 166 167 if (zsaddr != (void*) zs_physaddr[i]) 168 return 0; 169 if (badaddr(INTIO_ADDR(zsaddr))) 170 return 0; 171 172 return (1); 173 } 174 175 /* 176 * Attach a found zs. 177 */ 178 static void 179 zs_attach(struct device *parent, struct device *self, void *aux) 180 { 181 struct zsc_softc *zsc = (void *) self; 182 struct intio_attach_args *ia = aux; 183 struct zsc_attach_args zsc_args; 184 volatile struct zschan *zc; 185 struct zs_chanstate *cs; 186 int r, s, zs_unit, channel; 187 188 zs_unit = device_unit(&zsc->zsc_dev); 189 zsc->zsc_addr = (void*) ia->ia_addr; 190 191 ia->ia_size = 8; 192 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 193 #ifdef DIAGNOSTIC 194 if (r) 195 panic ("zs: intio IO map corruption"); 196 #endif 197 198 printf("\n"); 199 200 /* 201 * Initialize software state for each channel. 202 */ 203 for (channel = 0; channel < 2; channel++) { 204 struct device *child; 205 206 zsc_args.channel = channel; 207 zsc_args.hwflags = 0; 208 cs = &zsc->zsc_cs_store[channel]; 209 zsc->zsc_cs[channel] = cs; 210 211 simple_lock_init(&cs->cs_lock); 212 cs->cs_channel = channel; 213 cs->cs_private = NULL; 214 cs->cs_ops = &zsops_null; 215 cs->cs_brg_clk = PCLK / 16; 216 217 if (channel == 0) 218 zc = (volatile void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 219 else 220 zc = (volatile void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 221 cs->cs_reg_csr = &zc->zc_csr; 222 cs->cs_reg_data = &zc->zc_data; 223 224 zs_init_reg[2] = ia->ia_intr; 225 memcpy(cs->cs_creg, zs_init_reg, 16); 226 memcpy(cs->cs_preg, zs_init_reg, 16); 227 228 if (zc == conschan) { 229 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 230 cs->cs_defspeed = zs_get_speed(cs); 231 cs->cs_defcflag = zscn_def_cflag; 232 } else { 233 cs->cs_defspeed = 9600; 234 cs->cs_defcflag = zs_def_cflag; 235 } 236 237 /* Make these correspond to cs_defcflag (-crtscts) */ 238 cs->cs_rr0_dcd = ZSRR0_DCD; 239 cs->cs_rr0_cts = 0; 240 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 241 cs->cs_wr5_rts = 0; 242 243 /* 244 * Clear the master interrupt enable. 245 * The INTENA is common to both channels, 246 * so just do it on the A channel. 247 */ 248 if (channel == 0) { 249 s = splzs(); 250 zs_write_reg(cs, 9, 0); 251 splx(s); 252 } 253 254 /* 255 * Look for a child driver for this channel. 256 * The child attach will setup the hardware. 257 */ 258 child = config_found(self, (void *)&zsc_args, zs_print); 259 #if ZSTTY > 0 260 if (zc == conschan && 261 ((child && strcmp (child->dv_xname, "zstty0")) || 262 child == NULL)) /* XXX */ 263 panic ("zs_attach: console device mismatch"); 264 #endif 265 if (child == NULL) { 266 /* No sub-driver. Just reset it. */ 267 u_char reset = (channel == 0) ? 268 ZSWR9_A_RESET : ZSWR9_B_RESET; 269 s = splzs(); 270 zs_write_reg(cs, 9, reset); 271 splx(s); 272 } 273 } 274 275 /* 276 * Now safe to install interrupt handlers. 277 */ 278 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 279 panic("zs_attach: interrupt vector busy"); 280 /* XXX; evcnt_attach() ? */ 281 282 /* 283 * Set the master interrupt enable and interrupt vector. 284 * (common to both channels, do it on A) 285 */ 286 cs = zsc->zsc_cs[0]; 287 s = splzs(); 288 /* interrupt vector */ 289 zs_write_reg(cs, 2, ia->ia_intr); 290 /* master interrupt control (enable) */ 291 zs_write_reg(cs, 9, zs_init_reg[9]); 292 splx(s); 293 } 294 295 static int 296 zs_print(void *aux, const char *name) 297 { 298 struct zsc_attach_args *args = aux; 299 300 if (name != NULL) 301 aprint_normal("%s: ", name); 302 303 if (args->channel != -1) 304 aprint_normal(" channel %d", args->channel); 305 306 return UNCONF; 307 } 308 309 310 /* 311 * For x68k-port, we don't use autovectored interrupt. 312 * We do not need to look at all of the zs chips. 313 */ 314 static int 315 zshard(void *arg) 316 { 317 struct zsc_softc *zsc = arg; 318 int rval; 319 int s; 320 321 /* 322 * Actually, zs hardware ipl is 5. 323 * Here we disable all interrupts to shorten the zshard 324 * handling time. Otherwise, too many characters are 325 * dropped. 326 */ 327 s = splhigh(); 328 rval = zsc_intr_hard(zsc); 329 330 /* We are at splzs here, so no need to lock. */ 331 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 332 setsoftserial(); 333 334 return (rval); 335 } 336 337 /* 338 * Shared among the all chips. We have to look at all of them. 339 */ 340 int 341 zssoft(void *arg) 342 { 343 struct zsc_softc *zsc; 344 int s, unit; 345 346 /* Make sure we call the tty layer at spltty. */ 347 s = spltty(); 348 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 349 zsc = zsc_cd.cd_devs[unit]; 350 if (zsc == NULL) 351 continue; 352 (void) zsc_intr_soft(zsc); 353 } 354 splx(s); 355 356 return (1); 357 } 358 359 360 /* 361 * Compute the current baud rate given a ZS channel. 362 */ 363 static int 364 zs_get_speed(struct zs_chanstate *cs) 365 { 366 int tconst; 367 368 tconst = zs_read_reg(cs, 12); 369 tconst |= zs_read_reg(cs, 13) << 8; 370 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 371 } 372 373 /* 374 * MD functions for setting the baud rate and control modes. 375 */ 376 int 377 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */) 378 { 379 int tconst, real_bps; 380 381 if (bps == 0) 382 return (0); 383 384 #ifdef DIAGNOSTIC 385 if (cs->cs_brg_clk == 0) 386 panic("zs_set_speed"); 387 #endif 388 389 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 390 if (tconst < 0) 391 return (EINVAL); 392 393 /* Convert back to make sure we can do it. */ 394 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 395 396 #if 0 /* XXX */ 397 /* XXX - Allow some tolerance here? */ 398 if (real_bps != bps) 399 return (EINVAL); 400 #else 401 /* 402 * Since our PCLK has somewhat strange value, 403 * we have to allow tolerance here. 404 */ 405 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 406 return (EINVAL); 407 #endif 408 409 cs->cs_preg[12] = tconst; 410 cs->cs_preg[13] = tconst >> 8; 411 412 /* Caller will stuff the pending registers. */ 413 return (0); 414 } 415 416 int 417 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */) 418 { 419 int s; 420 421 /* 422 * Output hardware flow control on the chip is horrendous: 423 * if carrier detect drops, the receiver is disabled, and if 424 * CTS drops, the transmitter is stoped IN MID CHARACTER! 425 * Therefore, NEVER set the HFC bit, and instead use the 426 * status interrupt to detect CTS changes. 427 */ 428 s = splzs(); 429 cs->cs_rr0_pps = 0; 430 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 431 cs->cs_rr0_dcd = 0; 432 if ((cflag & MDMBUF) == 0) 433 cs->cs_rr0_pps = ZSRR0_DCD; 434 } else 435 cs->cs_rr0_dcd = ZSRR0_DCD; 436 if ((cflag & CRTSCTS) != 0) { 437 cs->cs_wr5_dtr = ZSWR5_DTR; 438 cs->cs_wr5_rts = ZSWR5_RTS; 439 cs->cs_rr0_cts = ZSRR0_CTS; 440 } else if ((cflag & MDMBUF) != 0) { 441 cs->cs_wr5_dtr = 0; 442 cs->cs_wr5_rts = ZSWR5_DTR; 443 cs->cs_rr0_cts = ZSRR0_DCD; 444 } else { 445 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 446 cs->cs_wr5_rts = 0; 447 cs->cs_rr0_cts = 0; 448 } 449 splx(s); 450 451 /* Caller will stuff the pending registers. */ 452 return (0); 453 } 454 455 456 /* 457 * Read or write the chip with suitable delays. 458 */ 459 460 u_char 461 zs_read_reg(cs, reg) 462 struct zs_chanstate *cs; 463 u_char reg; 464 { 465 u_char val; 466 467 *cs->cs_reg_csr = reg; 468 ZS_DELAY(); 469 val = *cs->cs_reg_csr; 470 ZS_DELAY(); 471 return val; 472 } 473 474 void 475 zs_write_reg(cs, reg, val) 476 struct zs_chanstate *cs; 477 u_char reg, val; 478 { 479 *cs->cs_reg_csr = reg; 480 ZS_DELAY(); 481 *cs->cs_reg_csr = val; 482 ZS_DELAY(); 483 } 484 485 u_char zs_read_csr(cs) 486 struct zs_chanstate *cs; 487 { 488 u_char val; 489 490 val = *cs->cs_reg_csr; 491 ZS_DELAY(); 492 return val; 493 } 494 495 void zs_write_csr(cs, val) 496 struct zs_chanstate *cs; 497 u_char val; 498 { 499 *cs->cs_reg_csr = val; 500 ZS_DELAY(); 501 } 502 503 u_char zs_read_data(cs) 504 struct zs_chanstate *cs; 505 { 506 u_char val; 507 508 val = *cs->cs_reg_data; 509 ZS_DELAY(); 510 return val; 511 } 512 513 void zs_write_data(cs, val) 514 struct zs_chanstate *cs; 515 u_char val; 516 { 517 *cs->cs_reg_data = val; 518 ZS_DELAY(); 519 } 520 521 522 static struct zs_chanstate zscn_cs; 523 524 /**************************************************************** 525 * Console support functions (x68k specific!) 526 * Note: this code is allowed to know about the layout of 527 * the chip registers, and uses that to keep things simple. 528 * XXX - I think I like the mvme167 code better. -gwr 529 ****************************************************************/ 530 531 /* 532 * Handle user request to enter kernel debugger. 533 */ 534 void 535 zs_abort(struct zs_chanstate *cs) 536 { 537 int rr0; 538 539 /* Wait for end of break to avoid PROM abort. */ 540 /* XXX - Limit the wait? */ 541 do { 542 rr0 = *cs->cs_reg_csr; 543 ZS_DELAY(); 544 } while (rr0 & ZSRR0_BREAK); 545 546 #ifdef DDB 547 Debugger(); 548 #else 549 printf ("BREAK!!\n"); 550 #endif 551 } 552 553 554 #if NZSTTY > 0 555 556 #include <dev/cons.h> 557 cons_decl(zs); 558 559 static int zs_getc(void); 560 static void zs_putc(int); 561 562 /* 563 * Polled input char. 564 */ 565 static int 566 zs_getc(void) 567 { 568 int s, c, rr0; 569 570 s = splzs(); 571 /* Wait for a character to arrive. */ 572 do { 573 rr0 = zs_read_csr(&zscn_cs); 574 } while ((rr0 & ZSRR0_RX_READY) == 0); 575 576 c = zs_read_data (&zscn_cs); 577 splx(s); 578 579 /* 580 * This is used by the kd driver to read scan codes, 581 * so don't translate '\r' ==> '\n' here... 582 */ 583 return (c); 584 } 585 586 /* 587 * Polled output char. 588 */ 589 static void 590 zs_putc(int c) 591 { 592 int s, rr0; 593 594 s = splzs(); 595 /* Wait for transmitter to become ready. */ 596 do { 597 rr0 = zs_read_csr (&zscn_cs); 598 } while ((rr0 & ZSRR0_TX_READY) == 0); 599 600 zs_write_data(&zscn_cs, c); 601 splx(s); 602 } 603 604 void 605 zscninit(struct consdev *cn) 606 { 607 volatile struct zschan *cnchan = (volatile void*) INTIO_ADDR(ZSCN_PHYSADDR); 608 int s; 609 610 memset(&zscn_cs, 0, sizeof (struct zs_chanstate)); 611 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 612 zscn_cs.cs_reg_data = &cnchan->zc_data; 613 zscn_cs.cs_channel = 0; 614 zscn_cs.cs_brg_clk = PCLK / 16; 615 memcpy(zscn_cs.cs_preg, zs_init_reg, 16); 616 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 617 zscn_cs.cs_preg[9] = 0; 618 zs_set_speed(&zscn_cs, ZSCN_SPEED); 619 s = splzs(); 620 zs_loadchannelregs(&zscn_cs); 621 splx(s); 622 conschan = cnchan; 623 } 624 625 /* 626 * Polled console input putchar. 627 */ 628 int 629 zscngetc(dev_t dev) 630 { 631 return (zs_getc()); 632 } 633 634 /* 635 * Polled console output putchar. 636 */ 637 void 638 zscnputc(dev_t dev, int c) 639 { 640 zs_putc(c); 641 } 642 643 void 644 zscnprobe(struct consdev *cd) 645 { 646 int maj; 647 extern const struct cdevsw zstty_cdevsw; 648 649 /* locate the major number */ 650 maj = cdevsw_lookup_major(&zstty_cdevsw); 651 /* XXX: minor number is 0 */ 652 653 if (maj == -1) 654 cd->cn_pri = CN_DEAD; 655 else { 656 #ifdef ZSCONSOLE 657 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 658 #else 659 cd->cn_pri = CN_NORMAL; 660 #endif 661 cd->cn_dev = makedev(maj, 0); 662 } 663 } 664 665 void 666 zscnpollc(dev_t dev, int on) 667 { 668 } 669 670 #endif 671
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