zs.c revision 1.30
1 /* $NetBSD: zs.c,v 1.30 2007/03/04 02:08:08 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 Minoura Makoto 5 * Copyright (c) 1996 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Gordon W. Ross. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part) 42 * 43 * X68k uses one Z8530 built-in. Channel A is for RS-232C serial port; 44 * while channel B is dedicated to the mouse. 45 * Extra Z8530's can be installed for serial ports. This driver 46 * supports up to 5 chips including the built-in one. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.30 2007/03/04 02:08:08 tsutsui Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/cpu.h> 65 #include <machine/bus.h> 66 #include <arch/x68k/dev/intiovar.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/ic/z8530reg.h> 70 71 #include "zsc.h" /* NZSC */ 72 #include "opt_zsc.h" 73 #ifndef ZSCN_SPEED 74 #define ZSCN_SPEED 9600 75 #endif 76 #include "zstty.h" 77 78 79 extern void Debugger(void); 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 int zscn_def_cflag = (CREAD | CS8 | HUPCL); 88 89 /* 90 * X68k provides a 5.0 MHz clock to the ZS chips. 91 */ 92 #define PCLK (5 * 1000 * 1000) /* PCLK pin input clock rate */ 93 94 95 /* Default physical addresses. */ 96 #define ZS_MAXDEV 5 97 static bus_addr_t zs_physaddr[ZS_MAXDEV] = { 98 0x00e98000, 99 0x00eafc00, 100 0x00eafc10, 101 0x00eafc20, 102 0x00eafc30 103 }; 104 105 static u_char zs_init_reg[16] = { 106 0, /* 0: CMD (reset, etc.) */ 107 0, /* 1: No interrupts yet. */ 108 0x70, /* 2: XXX: IVECT */ 109 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 110 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 111 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 112 0, /* 6: TXSYNC/SYNCLO */ 113 0, /* 7: RXSYNC/SYNCHI */ 114 0, /* 8: alias for data port */ 115 ZSWR9_MASTER_IE, 116 ZSWR10_NRZ, /*10: Misc. TX/RX control bits */ 117 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 118 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 119 0, /*13: BAUDHI (default=9600) */ 120 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 121 ZSWR15_BREAK_IE, 122 }; 123 124 static volatile struct zschan *conschan = 0; 125 126 127 /**************************************************************** 128 * Autoconfig 129 ****************************************************************/ 130 131 /* Definition of the driver for autoconfig. */ 132 static int zs_match(struct device *, struct cfdata *, void *); 133 static void zs_attach(struct device *, struct device *, void *); 134 static int zs_print(void *, const char *name); 135 136 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 137 zs_match, zs_attach, NULL, NULL); 138 139 extern struct cfdriver zsc_cd; 140 141 static int zshard(void *); 142 static int zs_get_speed(struct zs_chanstate *); 143 144 145 /* 146 * Is the zs chip present? 147 */ 148 static int 149 zs_match(struct device *parent, struct cfdata *cf, void *aux) 150 { 151 struct intio_attach_args *ia = aux; 152 struct zsdevice *zsaddr = (void*) ia->ia_addr; 153 int i; 154 155 if (strcmp (ia->ia_name, "zsc") != 0) 156 return 0; 157 158 for (i = 0; i < ZS_MAXDEV; i++) 159 if (zsaddr == (void*) zs_physaddr[i]) /* XXX */ 160 break; 161 162 ia->ia_size = 8; 163 if (intio_map_allocate_region (parent, ia, INTIO_MAP_TESTONLY)) 164 return 0; 165 166 if (zsaddr != (void*) zs_physaddr[i]) 167 return 0; 168 if (badaddr(INTIO_ADDR(zsaddr))) 169 return 0; 170 171 return (1); 172 } 173 174 /* 175 * Attach a found zs. 176 */ 177 static void 178 zs_attach(struct device *parent, struct device *self, void *aux) 179 { 180 struct zsc_softc *zsc = (void *) self; 181 struct intio_attach_args *ia = aux; 182 struct zsc_attach_args zsc_args; 183 volatile struct zschan *zc; 184 struct zs_chanstate *cs; 185 int r, s, zs_unit, channel; 186 187 zs_unit = device_unit(&zsc->zsc_dev); 188 zsc->zsc_addr = (void*) ia->ia_addr; 189 190 ia->ia_size = 8; 191 r = intio_map_allocate_region (parent, ia, INTIO_MAP_ALLOCATE); 192 #ifdef DIAGNOSTIC 193 if (r) 194 panic ("zs: intio IO map corruption"); 195 #endif 196 197 printf("\n"); 198 199 /* 200 * Initialize software state for each channel. 201 */ 202 for (channel = 0; channel < 2; channel++) { 203 struct device *child; 204 205 zsc_args.channel = channel; 206 zsc_args.hwflags = 0; 207 cs = &zsc->zsc_cs_store[channel]; 208 zsc->zsc_cs[channel] = cs; 209 210 simple_lock_init(&cs->cs_lock); 211 cs->cs_channel = channel; 212 cs->cs_private = NULL; 213 cs->cs_ops = &zsops_null; 214 cs->cs_brg_clk = PCLK / 16; 215 216 if (channel == 0) 217 zc = (volatile void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_a); 218 else 219 zc = (volatile void*) INTIO_ADDR(&zsc->zsc_addr->zs_chan_b); 220 cs->cs_reg_csr = &zc->zc_csr; 221 cs->cs_reg_data = &zc->zc_data; 222 223 zs_init_reg[2] = ia->ia_intr; 224 memcpy(cs->cs_creg, zs_init_reg, 16); 225 memcpy(cs->cs_preg, zs_init_reg, 16); 226 227 if (zc == conschan) { 228 zsc_args.hwflags |= ZS_HWFLAG_CONSOLE; 229 cs->cs_defspeed = zs_get_speed(cs); 230 cs->cs_defcflag = zscn_def_cflag; 231 } else { 232 cs->cs_defspeed = 9600; 233 cs->cs_defcflag = zs_def_cflag; 234 } 235 236 /* Make these correspond to cs_defcflag (-crtscts) */ 237 cs->cs_rr0_dcd = ZSRR0_DCD; 238 cs->cs_rr0_cts = 0; 239 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 240 cs->cs_wr5_rts = 0; 241 242 /* 243 * Clear the master interrupt enable. 244 * The INTENA is common to both channels, 245 * so just do it on the A channel. 246 */ 247 if (channel == 0) { 248 s = splzs(); 249 zs_write_reg(cs, 9, 0); 250 splx(s); 251 } 252 253 /* 254 * Look for a child driver for this channel. 255 * The child attach will setup the hardware. 256 */ 257 child = config_found(self, (void *)&zsc_args, zs_print); 258 #if ZSTTY > 0 259 if (zc == conschan && 260 ((child && strcmp (child->dv_xname, "zstty0")) || 261 child == NULL)) /* XXX */ 262 panic ("zs_attach: console device mismatch"); 263 #endif 264 if (child == NULL) { 265 /* No sub-driver. Just reset it. */ 266 u_char reset = (channel == 0) ? 267 ZSWR9_A_RESET : ZSWR9_B_RESET; 268 s = splzs(); 269 zs_write_reg(cs, 9, reset); 270 splx(s); 271 } 272 } 273 274 /* 275 * Now safe to install interrupt handlers. 276 */ 277 if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc)) 278 panic("zs_attach: interrupt vector busy"); 279 zsc->zsc_softintr_cookie = softintr_establish(IPL_SOFTSERIAL, 280 (void (*)(void *))zsc_intr_soft, zsc); 281 /* XXX; evcnt_attach() ? */ 282 283 /* 284 * Set the master interrupt enable and interrupt vector. 285 * (common to both channels, do it on A) 286 */ 287 cs = zsc->zsc_cs[0]; 288 s = splzs(); 289 /* interrupt vector */ 290 zs_write_reg(cs, 2, ia->ia_intr); 291 /* master interrupt control (enable) */ 292 zs_write_reg(cs, 9, zs_init_reg[9]); 293 splx(s); 294 } 295 296 static int 297 zs_print(void *aux, const char *name) 298 { 299 struct zsc_attach_args *args = aux; 300 301 if (name != NULL) 302 aprint_normal("%s: ", name); 303 304 if (args->channel != -1) 305 aprint_normal(" channel %d", args->channel); 306 307 return UNCONF; 308 } 309 310 311 /* 312 * For x68k-port, we don't use autovectored interrupt. 313 * We do not need to look at all of the zs chips. 314 */ 315 static int 316 zshard(void *arg) 317 { 318 struct zsc_softc *zsc = arg; 319 int rval; 320 int s; 321 322 /* 323 * Actually, zs hardware ipl is 5. 324 * Here we disable all interrupts to shorten the zshard 325 * handling time. Otherwise, too many characters are 326 * dropped. 327 */ 328 s = splhigh(); 329 rval = zsc_intr_hard(zsc); 330 331 /* We are at splzs here, so no need to lock. */ 332 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 333 softintr_schedule(zsc->zsc_softintr_cookie); 334 335 return (rval); 336 } 337 338 /* 339 * Compute the current baud rate given a ZS channel. 340 */ 341 static int 342 zs_get_speed(struct zs_chanstate *cs) 343 { 344 int tconst; 345 346 tconst = zs_read_reg(cs, 12); 347 tconst |= zs_read_reg(cs, 13) << 8; 348 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 349 } 350 351 /* 352 * MD functions for setting the baud rate and control modes. 353 */ 354 int 355 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */) 356 { 357 int tconst, real_bps; 358 359 if (bps == 0) 360 return (0); 361 362 #ifdef DIAGNOSTIC 363 if (cs->cs_brg_clk == 0) 364 panic("zs_set_speed"); 365 #endif 366 367 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 368 if (tconst < 0) 369 return (EINVAL); 370 371 /* Convert back to make sure we can do it. */ 372 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 373 374 #if 0 /* XXX */ 375 /* XXX - Allow some tolerance here? */ 376 if (real_bps != bps) 377 return (EINVAL); 378 #else 379 /* 380 * Since our PCLK has somewhat strange value, 381 * we have to allow tolerance here. 382 */ 383 if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst) 384 return (EINVAL); 385 #endif 386 387 cs->cs_preg[12] = tconst; 388 cs->cs_preg[13] = tconst >> 8; 389 390 /* Caller will stuff the pending registers. */ 391 return (0); 392 } 393 394 int 395 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */) 396 { 397 int s; 398 399 /* 400 * Output hardware flow control on the chip is horrendous: 401 * if carrier detect drops, the receiver is disabled, and if 402 * CTS drops, the transmitter is stoped IN MID CHARACTER! 403 * Therefore, NEVER set the HFC bit, and instead use the 404 * status interrupt to detect CTS changes. 405 */ 406 s = splzs(); 407 cs->cs_rr0_pps = 0; 408 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 409 cs->cs_rr0_dcd = 0; 410 if ((cflag & MDMBUF) == 0) 411 cs->cs_rr0_pps = ZSRR0_DCD; 412 } else 413 cs->cs_rr0_dcd = ZSRR0_DCD; 414 if ((cflag & CRTSCTS) != 0) { 415 cs->cs_wr5_dtr = ZSWR5_DTR; 416 cs->cs_wr5_rts = ZSWR5_RTS; 417 cs->cs_rr0_cts = ZSRR0_CTS; 418 } else if ((cflag & MDMBUF) != 0) { 419 cs->cs_wr5_dtr = 0; 420 cs->cs_wr5_rts = ZSWR5_DTR; 421 cs->cs_rr0_cts = ZSRR0_DCD; 422 } else { 423 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 424 cs->cs_wr5_rts = 0; 425 cs->cs_rr0_cts = 0; 426 } 427 splx(s); 428 429 /* Caller will stuff the pending registers. */ 430 return (0); 431 } 432 433 434 /* 435 * Read or write the chip with suitable delays. 436 */ 437 438 u_char 439 zs_read_reg(cs, reg) 440 struct zs_chanstate *cs; 441 u_char reg; 442 { 443 u_char val; 444 445 *cs->cs_reg_csr = reg; 446 ZS_DELAY(); 447 val = *cs->cs_reg_csr; 448 ZS_DELAY(); 449 return val; 450 } 451 452 void 453 zs_write_reg(cs, reg, val) 454 struct zs_chanstate *cs; 455 u_char reg, val; 456 { 457 *cs->cs_reg_csr = reg; 458 ZS_DELAY(); 459 *cs->cs_reg_csr = val; 460 ZS_DELAY(); 461 } 462 463 u_char zs_read_csr(cs) 464 struct zs_chanstate *cs; 465 { 466 u_char val; 467 468 val = *cs->cs_reg_csr; 469 ZS_DELAY(); 470 return val; 471 } 472 473 void zs_write_csr(cs, val) 474 struct zs_chanstate *cs; 475 u_char val; 476 { 477 *cs->cs_reg_csr = val; 478 ZS_DELAY(); 479 } 480 481 u_char zs_read_data(cs) 482 struct zs_chanstate *cs; 483 { 484 u_char val; 485 486 val = *cs->cs_reg_data; 487 ZS_DELAY(); 488 return val; 489 } 490 491 void zs_write_data(cs, val) 492 struct zs_chanstate *cs; 493 u_char val; 494 { 495 *cs->cs_reg_data = val; 496 ZS_DELAY(); 497 } 498 499 500 static struct zs_chanstate zscn_cs; 501 502 /**************************************************************** 503 * Console support functions (x68k specific!) 504 * Note: this code is allowed to know about the layout of 505 * the chip registers, and uses that to keep things simple. 506 * XXX - I think I like the mvme167 code better. -gwr 507 ****************************************************************/ 508 509 /* 510 * Handle user request to enter kernel debugger. 511 */ 512 void 513 zs_abort(struct zs_chanstate *cs) 514 { 515 int rr0; 516 517 /* Wait for end of break to avoid PROM abort. */ 518 /* XXX - Limit the wait? */ 519 do { 520 rr0 = *cs->cs_reg_csr; 521 ZS_DELAY(); 522 } while (rr0 & ZSRR0_BREAK); 523 524 #ifdef DDB 525 Debugger(); 526 #else 527 printf ("BREAK!!\n"); 528 #endif 529 } 530 531 532 #if NZSTTY > 0 533 534 #include <dev/cons.h> 535 cons_decl(zs); 536 537 static int zs_getc(void); 538 static void zs_putc(int); 539 540 /* 541 * Polled input char. 542 */ 543 static int 544 zs_getc(void) 545 { 546 int s, c, rr0; 547 548 s = splzs(); 549 /* Wait for a character to arrive. */ 550 do { 551 rr0 = zs_read_csr(&zscn_cs); 552 } while ((rr0 & ZSRR0_RX_READY) == 0); 553 554 c = zs_read_data (&zscn_cs); 555 splx(s); 556 557 /* 558 * This is used by the kd driver to read scan codes, 559 * so don't translate '\r' ==> '\n' here... 560 */ 561 return (c); 562 } 563 564 /* 565 * Polled output char. 566 */ 567 static void 568 zs_putc(int c) 569 { 570 int s, rr0; 571 572 s = splzs(); 573 /* Wait for transmitter to become ready. */ 574 do { 575 rr0 = zs_read_csr (&zscn_cs); 576 } while ((rr0 & ZSRR0_TX_READY) == 0); 577 578 zs_write_data(&zscn_cs, c); 579 splx(s); 580 } 581 582 void 583 zscninit(struct consdev *cn) 584 { 585 volatile struct zschan *cnchan = (volatile void*) INTIO_ADDR(ZSCN_PHYSADDR); 586 int s; 587 588 memset(&zscn_cs, 0, sizeof (struct zs_chanstate)); 589 zscn_cs.cs_reg_csr = &cnchan->zc_csr; 590 zscn_cs.cs_reg_data = &cnchan->zc_data; 591 zscn_cs.cs_channel = 0; 592 zscn_cs.cs_brg_clk = PCLK / 16; 593 memcpy(zscn_cs.cs_preg, zs_init_reg, 16); 594 zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */ 595 zscn_cs.cs_preg[9] = 0; 596 zs_set_speed(&zscn_cs, ZSCN_SPEED); 597 s = splzs(); 598 zs_loadchannelregs(&zscn_cs); 599 splx(s); 600 conschan = cnchan; 601 } 602 603 /* 604 * Polled console input putchar. 605 */ 606 int 607 zscngetc(dev_t dev) 608 { 609 return (zs_getc()); 610 } 611 612 /* 613 * Polled console output putchar. 614 */ 615 void 616 zscnputc(dev_t dev, int c) 617 { 618 zs_putc(c); 619 } 620 621 void 622 zscnprobe(struct consdev *cd) 623 { 624 int maj; 625 extern const struct cdevsw zstty_cdevsw; 626 627 /* locate the major number */ 628 maj = cdevsw_lookup_major(&zstty_cdevsw); 629 /* XXX: minor number is 0 */ 630 631 if (maj == -1) 632 cd->cn_pri = CN_DEAD; 633 else { 634 #ifdef ZSCONSOLE 635 cd->cn_pri = CN_REMOTE; /* higher than ITE (CN_INTERNAL) */ 636 #else 637 cd->cn_pri = CN_NORMAL; 638 #endif 639 cd->cn_dev = makedev(maj, 0); 640 } 641 } 642 643 void 644 zscnpollc(dev_t dev, int on) 645 { 646 } 647 648 #endif 649
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