bus.h revision 1.21 1 1.21 tsutsui /* $NetBSD: bus.h,v 1.21 2010/03/19 10:54:00 tsutsui Exp $ */
2 1.2 minoura
3 1.2 minoura /*-
4 1.7 thorpej * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
5 1.2 minoura * All rights reserved.
6 1.2 minoura *
7 1.2 minoura * This code is derived from software contributed to The NetBSD Foundation
8 1.2 minoura * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.2 minoura * NASA Ames Research Center.
10 1.2 minoura *
11 1.2 minoura * Redistribution and use in source and binary forms, with or without
12 1.2 minoura * modification, are permitted provided that the following conditions
13 1.2 minoura * are met:
14 1.2 minoura * 1. Redistributions of source code must retain the above copyright
15 1.2 minoura * notice, this list of conditions and the following disclaimer.
16 1.2 minoura * 2. Redistributions in binary form must reproduce the above copyright
17 1.2 minoura * notice, this list of conditions and the following disclaimer in the
18 1.2 minoura * documentation and/or other materials provided with the distribution.
19 1.2 minoura *
20 1.2 minoura * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.2 minoura * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.2 minoura * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.2 minoura * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.2 minoura * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.2 minoura * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.2 minoura * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.2 minoura * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.2 minoura * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.2 minoura * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.2 minoura * POSSIBILITY OF SUCH DAMAGE.
31 1.2 minoura */
32 1.2 minoura
33 1.2 minoura /*
34 1.2 minoura * bus_space(9) and bus_dma(9) interface for NetBSD/x68k.
35 1.2 minoura */
36 1.2 minoura
37 1.2 minoura #ifndef _X68K_BUS_H_
38 1.2 minoura #define _X68K_BUS_H_
39 1.2 minoura
40 1.6 itohy #ifndef X68K_BUS_PERFORMANCE_HACK
41 1.6 itohy #if defined(__GNUC__) && defined(__STDC__)
42 1.6 itohy #define X68K_BUS_PERFORMANCE_HACK 1
43 1.6 itohy #else
44 1.6 itohy #define X68K_BUS_PERFORMANCE_HACK 0
45 1.6 itohy #endif
46 1.6 itohy #endif
47 1.6 itohy
48 1.2 minoura /*
49 1.2 minoura * Bus address and size types
50 1.2 minoura */
51 1.2 minoura typedef u_long bus_addr_t;
52 1.2 minoura typedef u_long bus_size_t;
53 1.2 minoura typedef u_long bus_space_handle_t;
54 1.2 minoura
55 1.2 minoura /*
56 1.2 minoura * Bus space descripter
57 1.2 minoura */
58 1.2 minoura typedef struct x68k_bus_space *bus_space_tag_t;
59 1.2 minoura
60 1.2 minoura struct x68k_bus_space {
61 1.2 minoura #if 0
62 1.2 minoura enum {
63 1.2 minoura X68K_INTIO_BUS,
64 1.2 minoura X68K_PCI_BUS,
65 1.2 minoura X68K_NEPTUNE_BUS
66 1.2 minoura } x68k_bus_type;
67 1.2 minoura #endif
68 1.2 minoura
69 1.12 chs int (*x68k_bus_space_map)(
70 1.2 minoura bus_space_tag_t,
71 1.2 minoura bus_addr_t,
72 1.2 minoura bus_size_t,
73 1.2 minoura int, /* flags */
74 1.12 chs bus_space_handle_t *);
75 1.12 chs void (*x68k_bus_space_unmap)(
76 1.2 minoura bus_space_tag_t,
77 1.2 minoura bus_space_handle_t,
78 1.12 chs bus_size_t);
79 1.12 chs int (*x68k_bus_space_subregion)(
80 1.2 minoura bus_space_tag_t,
81 1.2 minoura bus_space_handle_t,
82 1.2 minoura bus_size_t, /* offset */
83 1.2 minoura bus_size_t, /* size */
84 1.12 chs bus_space_handle_t *);
85 1.2 minoura
86 1.12 chs int (*x68k_bus_space_alloc)(
87 1.2 minoura bus_space_tag_t,
88 1.2 minoura bus_addr_t, /* reg_start */
89 1.2 minoura bus_addr_t, /* reg_end */
90 1.2 minoura bus_size_t,
91 1.2 minoura bus_size_t, /* alignment */
92 1.2 minoura bus_size_t, /* boundary */
93 1.2 minoura int, /* flags */
94 1.2 minoura bus_addr_t *,
95 1.12 chs bus_space_handle_t *);
96 1.12 chs void (*x68k_bus_space_free)(
97 1.2 minoura bus_space_tag_t,
98 1.2 minoura bus_space_handle_t,
99 1.12 chs bus_size_t);
100 1.2 minoura
101 1.2 minoura #if 0
102 1.12 chs void (*x68k_bus_space_barrier)(
103 1.2 minoura bus_space_tag_t,
104 1.2 minoura bus_space_handle_t,
105 1.2 minoura bus_size_t, /* offset */
106 1.2 minoura bus_size_t, /* length */
107 1.12 chs int); /* flags */
108 1.2 minoura #endif
109 1.2 minoura
110 1.2 minoura struct device *x68k_bus_device;
111 1.2 minoura };
112 1.2 minoura
113 1.12 chs int x68k_bus_space_alloc(bus_space_tag_t, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
114 1.12 chs void x68k_bus_space_free(bus_space_tag_t, bus_space_handle_t, bus_size_t);
115 1.2 minoura
116 1.2 minoura /*
117 1.2 minoura * bus_space(9) interface
118 1.2 minoura */
119 1.2 minoura
120 1.2 minoura #define bus_space_map(t,a,s,f,h) \
121 1.2 minoura ((*((t)->x68k_bus_space_map)) ((t),(a),(s),(f),(h)))
122 1.2 minoura #define bus_space_unmap(t,h,s) \
123 1.2 minoura ((*((t)->x68k_bus_space_unmap)) ((t),(h),(s)))
124 1.2 minoura #define bus_space_subregion(t,h,o,s,p) \
125 1.2 minoura ((*((t)->x68k_bus_space_subregion)) ((t),(h),(o),(s),(p)))
126 1.4 drochner #define BUS_SPACE_MAP_CACHEABLE 0x0001
127 1.4 drochner #define BUS_SPACE_MAP_LINEAR 0x0002
128 1.4 drochner #define BUS_SPACE_MAP_PREFETCHABLE 0x0004
129 1.2 minoura /*
130 1.2 minoura * For simpler hadware, many x68k devices are mapped with shifted address
131 1.2 minoura * i.e. only on even or odd addresses.
132 1.2 minoura */
133 1.9 isaki #define BUS_SPACE_MAP_SHIFTED_MASK 0x1001
134 1.9 isaki #define BUS_SPACE_MAP_SHIFTED_ODD 0x1001
135 1.9 isaki #define BUS_SPACE_MAP_SHIFTED_EVEN 0x1000
136 1.9 isaki #define BUS_SPACE_MAP_SHIFTED BUS_SPACE_MAP_SHIFTED_ODD
137 1.2 minoura
138 1.2 minoura #define bus_space_alloc(t,rs,re,s,a,b,f,r,h) \
139 1.2 minoura ((*((t)->x68k_bus_space_alloc)) ((t),(rs),(re),(s),(a),(b),(f),(r),(h)))
140 1.2 minoura #define bus_space_free(t,h,s) \
141 1.2 minoura ((*((t)->x68k_bus_space_free)) ((t),(h),(s)))
142 1.2 minoura
143 1.2 minoura /*
144 1.2 minoura * Note: the 680x0 does not currently require barriers, but we must
145 1.2 minoura * provide the flags to MI code.
146 1.2 minoura */
147 1.2 minoura #define bus_space_barrier(t, h, o, l, f) \
148 1.2 minoura ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
149 1.2 minoura #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
150 1.2 minoura #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
151 1.2 minoura
152 1.2 minoura #define bus_space_read_1(t,h,o) _bus_space_read_1(t,h,o)
153 1.2 minoura #define bus_space_read_2(t,h,o) _bus_space_read_2(t,h,o)
154 1.2 minoura #define bus_space_read_4(t,h,o) _bus_space_read_4(t,h,o)
155 1.2 minoura
156 1.2 minoura #define bus_space_read_multi_1(t,h,o,p,c) _bus_space_read_multi_1(t,h,o,p,c)
157 1.2 minoura #define bus_space_read_multi_2(t,h,o,p,c) _bus_space_read_multi_2(t,h,o,p,c)
158 1.2 minoura #define bus_space_read_multi_4(t,h,o,p,c) _bus_space_read_multi_4(t,h,o,p,c)
159 1.2 minoura
160 1.2 minoura #define bus_space_read_region_1(t,h,o,p,c) _bus_space_read_region_1(t,h,o,p,c)
161 1.2 minoura #define bus_space_read_region_2(t,h,o,p,c) _bus_space_read_region_2(t,h,o,p,c)
162 1.2 minoura #define bus_space_read_region_4(t,h,o,p,c) _bus_space_read_region_4(t,h,o,p,c)
163 1.2 minoura
164 1.2 minoura #define bus_space_write_1(t,h,o,v) _bus_space_write_1(t,h,o,v)
165 1.2 minoura #define bus_space_write_2(t,h,o,v) _bus_space_write_2(t,h,o,v)
166 1.2 minoura #define bus_space_write_4(t,h,o,v) _bus_space_write_4(t,h,o,v)
167 1.2 minoura
168 1.2 minoura #define bus_space_write_multi_1(t,h,o,p,c) _bus_space_write_multi_1(t,h,o,p,c)
169 1.2 minoura #define bus_space_write_multi_2(t,h,o,p,c) _bus_space_write_multi_2(t,h,o,p,c)
170 1.2 minoura #define bus_space_write_multi_4(t,h,o,p,c) _bus_space_write_multi_4(t,h,o,p,c)
171 1.2 minoura
172 1.2 minoura #define bus_space_write_region_1(t,h,o,p,c) \
173 1.2 minoura _bus_space_write_region_1(t,h,o,p,c)
174 1.2 minoura #define bus_space_write_region_2(t,h,o,p,c) \
175 1.2 minoura _bus_space_write_region_2(t,h,o,p,c)
176 1.2 minoura #define bus_space_write_region_4(t,h,o,p,c) \
177 1.2 minoura _bus_space_write_region_4(t,h,o,p,c)
178 1.2 minoura
179 1.2 minoura #define bus_space_set_region_1(t,h,o,v,c) _bus_space_set_region_1(t,h,o,v,c)
180 1.2 minoura #define bus_space_set_region_2(t,h,o,v,c) _bus_space_set_region_2(t,h,o,v,c)
181 1.2 minoura #define bus_space_set_region_4(t,h,o,v,c) _bus_space_set_region_4(t,h,o,v,c)
182 1.2 minoura
183 1.2 minoura #define bus_space_copy_region_1(t,sh,so,dh,do,c) \
184 1.2 minoura _bus_space_copy_region_1(t,sh,so,dh,do,c)
185 1.2 minoura #define bus_space_copy_region_2(t,sh,so,dh,do,c) \
186 1.2 minoura _bus_space_copy_region_2(t,sh,so,dh,do,c)
187 1.2 minoura #define bus_space_copy_region_4(t,sh,so,dh,do,c) \
188 1.2 minoura _bus_space_copy_region_4(t,sh,so,dh,do,c)
189 1.2 minoura
190 1.21 tsutsui static __inline uint8_t _bus_space_read_1
191 1.12 chs (bus_space_tag_t, bus_space_handle_t bsh, bus_size_t offset);
192 1.21 tsutsui static __inline uint16_t _bus_space_read_2
193 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t);
194 1.21 tsutsui static __inline uint32_t _bus_space_read_4
195 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t);
196 1.2 minoura
197 1.15 perry static __inline void _bus_space_read_multi_1
198 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
199 1.21 tsutsui uint8_t *, bus_size_t);
200 1.15 perry static __inline void _bus_space_read_multi_2
201 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
202 1.21 tsutsui uint16_t *, bus_size_t);
203 1.15 perry static __inline void _bus_space_read_multi_4
204 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
205 1.21 tsutsui uint32_t *, bus_size_t);
206 1.2 minoura
207 1.15 perry static __inline void _bus_space_read_region_1
208 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
209 1.21 tsutsui uint8_t *, bus_size_t);
210 1.15 perry static __inline void _bus_space_read_region_2
211 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
212 1.21 tsutsui uint16_t *, bus_size_t);
213 1.15 perry static __inline void _bus_space_read_region_4
214 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
215 1.21 tsutsui uint32_t *, bus_size_t);
216 1.2 minoura
217 1.15 perry static __inline void _bus_space_write_1
218 1.21 tsutsui (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t);
219 1.15 perry static __inline void _bus_space_write_2
220 1.21 tsutsui (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t);
221 1.15 perry static __inline void _bus_space_write_4
222 1.21 tsutsui (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t);
223 1.2 minoura
224 1.15 perry static __inline void _bus_space_write_multi_1
225 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
226 1.21 tsutsui const uint8_t *, bus_size_t);
227 1.15 perry static __inline void _bus_space_write_multi_2
228 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
229 1.21 tsutsui const uint16_t *, bus_size_t);
230 1.15 perry static __inline void _bus_space_write_multi_4
231 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
232 1.21 tsutsui const uint32_t *, bus_size_t);
233 1.2 minoura
234 1.15 perry static __inline void _bus_space_write_region_1
235 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
236 1.21 tsutsui const uint8_t *, bus_size_t);
237 1.15 perry static __inline void _bus_space_write_region_2
238 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
239 1.21 tsutsui const uint16_t *, bus_size_t);
240 1.15 perry static __inline void _bus_space_write_region_4
241 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
242 1.21 tsutsui const uint32_t *, bus_size_t);
243 1.2 minoura
244 1.15 perry static __inline void _bus_space_set_region_1
245 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
246 1.21 tsutsui uint8_t, bus_size_t);
247 1.15 perry static __inline void _bus_space_set_region_2
248 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
249 1.21 tsutsui uint16_t, bus_size_t);
250 1.15 perry static __inline void _bus_space_set_region_4
251 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
252 1.21 tsutsui uint32_t, bus_size_t);
253 1.2 minoura
254 1.15 perry static __inline void _bus_space_copy_region_1
255 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
256 1.12 chs bus_space_handle_t, bus_size_t, bus_size_t);
257 1.15 perry static __inline void _bus_space_copy_region_2
258 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
259 1.12 chs bus_space_handle_t, bus_size_t, bus_size_t);
260 1.15 perry static __inline void _bus_space_copy_region_4
261 1.12 chs (bus_space_tag_t, bus_space_handle_t, bus_size_t,
262 1.12 chs bus_space_handle_t, bus_size_t, bus_size_t);
263 1.2 minoura
264 1.2 minoura
265 1.6 itohy #define __X68K_BUS_ADDR(tag, handle, offset) \
266 1.6 itohy (((long)(handle) < 0 ? (offset) * 2 : (offset)) \
267 1.6 itohy + ((handle) & 0x7fffffff))
268 1.6 itohy
269 1.21 tsutsui static __inline uint8_t
270 1.2 minoura _bus_space_read_1(t, bsh, offset)
271 1.2 minoura bus_space_tag_t t;
272 1.2 minoura bus_space_handle_t bsh;
273 1.2 minoura bus_size_t offset;
274 1.2 minoura {
275 1.21 tsutsui return (*((volatile uint8_t *) __X68K_BUS_ADDR(t, bsh, offset)));
276 1.2 minoura }
277 1.2 minoura
278 1.21 tsutsui static __inline uint16_t
279 1.2 minoura _bus_space_read_2(t, bsh, offset)
280 1.2 minoura bus_space_tag_t t;
281 1.2 minoura bus_space_handle_t bsh;
282 1.2 minoura bus_size_t offset;
283 1.2 minoura {
284 1.21 tsutsui return (*((volatile uint16_t *) __X68K_BUS_ADDR(t, bsh, offset)));
285 1.2 minoura }
286 1.2 minoura
287 1.21 tsutsui static __inline uint32_t
288 1.2 minoura _bus_space_read_4(t, bsh, offset)
289 1.2 minoura bus_space_tag_t t;
290 1.2 minoura bus_space_handle_t bsh;
291 1.2 minoura bus_size_t offset;
292 1.2 minoura {
293 1.21 tsutsui return (*((volatile uint32_t *) __X68K_BUS_ADDR(t, bsh, offset)));
294 1.2 minoura }
295 1.2 minoura
296 1.15 perry static __inline void
297 1.2 minoura _bus_space_read_multi_1(t, bsh, offset, datap, count)
298 1.2 minoura bus_space_tag_t t;
299 1.2 minoura bus_space_handle_t bsh;
300 1.2 minoura bus_size_t offset;
301 1.21 tsutsui uint8_t *datap;
302 1.2 minoura bus_size_t count;
303 1.2 minoura {
304 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
305 1.21 tsutsui uint8_t *regadr = (uint8_t *) __X68K_BUS_ADDR(t, bsh, offset);
306 1.6 itohy for (; count; count--) {
307 1.6 itohy __asm("| avoid optim. _bus_space_read_multi_1" : : : "memory");
308 1.6 itohy *datap++ = *regadr;
309 1.6 itohy }
310 1.6 itohy #else
311 1.2 minoura while (count-- > 0) {
312 1.21 tsutsui *datap++ = *(volatile uint8_t *)
313 1.6 itohy __X68K_BUS_ADDR(t, bsh, offset);
314 1.2 minoura }
315 1.6 itohy #endif
316 1.2 minoura }
317 1.2 minoura
318 1.15 perry static __inline void
319 1.2 minoura _bus_space_read_multi_2(t, bsh, offset, datap, count)
320 1.2 minoura bus_space_tag_t t;
321 1.2 minoura bus_space_handle_t bsh;
322 1.2 minoura bus_size_t offset;
323 1.21 tsutsui uint16_t *datap;
324 1.2 minoura bus_size_t count;
325 1.2 minoura {
326 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
327 1.21 tsutsui uint16_t *regadr = (uint16_t *) __X68K_BUS_ADDR(t, bsh, offset);
328 1.6 itohy for (; count; count--) {
329 1.6 itohy __asm("| avoid optim. _bus_space_read_multi_2" : : : "memory");
330 1.6 itohy *datap++ = *regadr;
331 1.6 itohy }
332 1.6 itohy #else
333 1.2 minoura while (count-- > 0) {
334 1.21 tsutsui *datap++ = *(volatile uint16_t *)
335 1.6 itohy __X68K_BUS_ADDR(t, bsh, offset);
336 1.2 minoura }
337 1.6 itohy #endif
338 1.2 minoura }
339 1.2 minoura
340 1.15 perry static __inline void
341 1.2 minoura _bus_space_read_multi_4(t, bsh, offset, datap, count)
342 1.2 minoura bus_space_tag_t t;
343 1.2 minoura bus_space_handle_t bsh;
344 1.2 minoura bus_size_t offset;
345 1.21 tsutsui uint32_t *datap;
346 1.2 minoura bus_size_t count;
347 1.2 minoura {
348 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
349 1.21 tsutsui uint32_t *regadr = (uint32_t *) __X68K_BUS_ADDR(t, bsh, offset);
350 1.6 itohy for (; count; count--) {
351 1.6 itohy __asm("| avoid optim. _bus_space_read_multi_4" : : : "memory");
352 1.6 itohy *datap++ = *regadr;
353 1.6 itohy }
354 1.6 itohy #else
355 1.2 minoura while (count-- > 0) {
356 1.21 tsutsui *datap++ = *(volatile uint32_t *)
357 1.6 itohy __X68K_BUS_ADDR(t, bsh, offset);
358 1.2 minoura }
359 1.6 itohy #endif
360 1.2 minoura }
361 1.2 minoura
362 1.15 perry static __inline void
363 1.2 minoura _bus_space_read_region_1(t, bsh, offset, datap, count)
364 1.2 minoura bus_space_tag_t t;
365 1.2 minoura bus_space_handle_t bsh;
366 1.2 minoura bus_size_t offset;
367 1.21 tsutsui uint8_t *datap;
368 1.2 minoura bus_size_t count;
369 1.2 minoura {
370 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
371 1.21 tsutsui uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
372 1.6 itohy
373 1.6 itohy for (; count; count--) {
374 1.6 itohy __asm("| avoid optim. _bus_space_read_region_1" : : : "memory");
375 1.6 itohy *datap++ = *addr++;
376 1.6 itohy }
377 1.6 itohy #else
378 1.21 tsutsui volatile uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
379 1.2 minoura
380 1.2 minoura while (count-- > 0) {
381 1.2 minoura *datap++ = *addr++;
382 1.2 minoura }
383 1.6 itohy #endif
384 1.2 minoura }
385 1.2 minoura
386 1.15 perry static __inline void
387 1.2 minoura _bus_space_read_region_2(t, bsh, offset, datap, count)
388 1.2 minoura bus_space_tag_t t;
389 1.2 minoura bus_space_handle_t bsh;
390 1.2 minoura bus_size_t offset;
391 1.21 tsutsui uint16_t *datap;
392 1.2 minoura bus_size_t count;
393 1.2 minoura {
394 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
395 1.21 tsutsui uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
396 1.6 itohy
397 1.6 itohy for (; count; count--) {
398 1.6 itohy __asm("| avoid optim. _bus_space_read_region_2" : : : "memory");
399 1.6 itohy *datap++ = *addr++;
400 1.6 itohy }
401 1.6 itohy #else
402 1.21 tsutsui volatile uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
403 1.2 minoura
404 1.2 minoura while (count-- > 0) {
405 1.2 minoura *datap++ = *addr++;
406 1.2 minoura }
407 1.6 itohy #endif
408 1.2 minoura }
409 1.2 minoura
410 1.15 perry static __inline void
411 1.2 minoura _bus_space_read_region_4(t, bsh, offset, datap, count)
412 1.2 minoura bus_space_tag_t t;
413 1.2 minoura bus_space_handle_t bsh;
414 1.2 minoura bus_size_t offset;
415 1.21 tsutsui uint32_t *datap;
416 1.2 minoura bus_size_t count;
417 1.2 minoura {
418 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
419 1.21 tsutsui uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
420 1.6 itohy
421 1.6 itohy for (; count; count--) {
422 1.6 itohy __asm("| avoid optim. _bus_space_read_region_4" : : : "memory");
423 1.6 itohy *datap++ = *addr++;
424 1.6 itohy }
425 1.6 itohy #else
426 1.21 tsutsui volatile uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
427 1.2 minoura
428 1.2 minoura while (count-- > 0) {
429 1.2 minoura *datap++ = *addr++;
430 1.2 minoura }
431 1.6 itohy #endif
432 1.2 minoura }
433 1.2 minoura
434 1.15 perry static __inline void
435 1.2 minoura _bus_space_write_1(t, bsh, offset, value)
436 1.2 minoura bus_space_tag_t t;
437 1.2 minoura bus_space_handle_t bsh;
438 1.2 minoura bus_size_t offset;
439 1.21 tsutsui uint8_t value;
440 1.2 minoura {
441 1.21 tsutsui *(volatile uint8_t *) __X68K_BUS_ADDR(t, bsh, offset) = value;
442 1.2 minoura }
443 1.2 minoura
444 1.15 perry static __inline void
445 1.2 minoura _bus_space_write_2(t, bsh, offset, value)
446 1.2 minoura bus_space_tag_t t;
447 1.2 minoura bus_space_handle_t bsh;
448 1.2 minoura bus_size_t offset;
449 1.21 tsutsui uint16_t value;
450 1.2 minoura {
451 1.21 tsutsui *(volatile uint16_t *) __X68K_BUS_ADDR(t, bsh, offset) = value;
452 1.2 minoura }
453 1.2 minoura
454 1.15 perry static __inline void
455 1.2 minoura _bus_space_write_4(t, bsh, offset, value)
456 1.2 minoura bus_space_tag_t t;
457 1.2 minoura bus_space_handle_t bsh;
458 1.2 minoura bus_size_t offset;
459 1.21 tsutsui uint32_t value;
460 1.2 minoura {
461 1.21 tsutsui *(volatile uint32_t *) __X68K_BUS_ADDR(t, bsh, offset) = value;
462 1.2 minoura }
463 1.2 minoura
464 1.15 perry static __inline void
465 1.2 minoura _bus_space_write_multi_1(t, bsh, offset, datap, count)
466 1.2 minoura bus_space_tag_t t;
467 1.2 minoura bus_space_handle_t bsh;
468 1.2 minoura bus_size_t offset;
469 1.21 tsutsui const uint8_t *datap;
470 1.2 minoura bus_size_t count;
471 1.2 minoura {
472 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
473 1.21 tsutsui uint8_t *regadr = (uint8_t *) __X68K_BUS_ADDR(t, bsh, offset);
474 1.6 itohy for (; count; count--) {
475 1.6 itohy __asm("| avoid optim. _bus_space_write_multi_1" : : : "memory");
476 1.6 itohy *regadr = *datap++;
477 1.6 itohy }
478 1.6 itohy #else
479 1.2 minoura while (count-- > 0) {
480 1.21 tsutsui *(volatile uint8_t *) __X68K_BUS_ADDR(t, bsh, offset)
481 1.6 itohy = *datap++;
482 1.2 minoura }
483 1.6 itohy #endif
484 1.2 minoura }
485 1.2 minoura
486 1.15 perry static __inline void
487 1.2 minoura _bus_space_write_multi_2(t, bsh, offset, datap, count)
488 1.2 minoura bus_space_tag_t t;
489 1.2 minoura bus_space_handle_t bsh;
490 1.2 minoura bus_size_t offset;
491 1.21 tsutsui const uint16_t *datap;
492 1.2 minoura bus_size_t count;
493 1.2 minoura {
494 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
495 1.21 tsutsui uint16_t *regadr = (uint16_t *) __X68K_BUS_ADDR(t, bsh, offset);
496 1.6 itohy for (; count; count--) {
497 1.6 itohy __asm("| avoid optim. _bus_space_write_multi_2" : : : "memory");
498 1.6 itohy *regadr = *datap++;
499 1.6 itohy }
500 1.6 itohy #else
501 1.2 minoura while (count-- > 0) {
502 1.21 tsutsui *(volatile uint16_t *) __X68K_BUS_ADDR(t, bsh, offset)
503 1.6 itohy = *datap++;
504 1.2 minoura }
505 1.6 itohy #endif
506 1.2 minoura }
507 1.2 minoura
508 1.15 perry static __inline void
509 1.2 minoura _bus_space_write_multi_4(t, bsh, offset, datap, count)
510 1.2 minoura bus_space_tag_t t;
511 1.2 minoura bus_space_handle_t bsh;
512 1.2 minoura bus_size_t offset;
513 1.21 tsutsui const uint32_t *datap;
514 1.2 minoura bus_size_t count;
515 1.2 minoura {
516 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
517 1.21 tsutsui uint32_t *regadr = (uint32_t *) __X68K_BUS_ADDR(t, bsh, offset);
518 1.6 itohy for (; count; count--) {
519 1.6 itohy __asm("| avoid optim. _bus_space_write_multi_4" : : : "memory");
520 1.6 itohy *regadr = *datap++;
521 1.6 itohy }
522 1.6 itohy #else
523 1.2 minoura while (count-- > 0) {
524 1.21 tsutsui *(volatile uint32_t *) __X68K_BUS_ADDR(t, bsh, offset)
525 1.6 itohy = *datap++;
526 1.2 minoura }
527 1.6 itohy #endif
528 1.2 minoura }
529 1.2 minoura
530 1.15 perry static __inline void
531 1.2 minoura _bus_space_write_region_1(t, bsh, offset, datap, count)
532 1.2 minoura bus_space_tag_t t;
533 1.2 minoura bus_space_handle_t bsh;
534 1.2 minoura bus_size_t offset;
535 1.21 tsutsui const uint8_t *datap;
536 1.2 minoura bus_size_t count;
537 1.2 minoura {
538 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
539 1.21 tsutsui uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
540 1.6 itohy
541 1.6 itohy for (; count; count--) {
542 1.6 itohy __asm("| avoid optim. _bus_space_write_region_1": : : "memory");
543 1.6 itohy *addr++ = *datap++;
544 1.6 itohy }
545 1.6 itohy #else
546 1.21 tsutsui volatile uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
547 1.2 minoura
548 1.2 minoura while (count-- > 0) {
549 1.2 minoura *addr++ = *datap++;
550 1.2 minoura }
551 1.6 itohy #endif
552 1.2 minoura }
553 1.2 minoura
554 1.15 perry static __inline void
555 1.2 minoura _bus_space_write_region_2(t, bsh, offset, datap, count)
556 1.2 minoura bus_space_tag_t t;
557 1.2 minoura bus_space_handle_t bsh;
558 1.2 minoura bus_size_t offset;
559 1.21 tsutsui const uint16_t *datap;
560 1.2 minoura bus_size_t count;
561 1.2 minoura {
562 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
563 1.21 tsutsui uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
564 1.6 itohy
565 1.6 itohy for (; count; count--) {
566 1.6 itohy __asm("| avoid optim. _bus_space_write_region_2": : : "memory");
567 1.6 itohy *addr++ = *datap++;
568 1.6 itohy }
569 1.6 itohy #else
570 1.21 tsutsui volatile uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
571 1.2 minoura
572 1.2 minoura while (count-- > 0) {
573 1.2 minoura *addr++ = *datap++;
574 1.2 minoura }
575 1.6 itohy #endif
576 1.2 minoura }
577 1.2 minoura
578 1.15 perry static __inline void
579 1.2 minoura _bus_space_write_region_4(t, bsh, offset, datap, count)
580 1.2 minoura bus_space_tag_t t;
581 1.2 minoura bus_space_handle_t bsh;
582 1.2 minoura bus_size_t offset;
583 1.21 tsutsui const uint32_t *datap;
584 1.2 minoura bus_size_t count;
585 1.2 minoura {
586 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
587 1.21 tsutsui uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
588 1.6 itohy
589 1.6 itohy for (; count; count--) {
590 1.6 itohy __asm("| avoid optim. _bus_space_write_region_4": : : "memory");
591 1.6 itohy *addr++ = *datap++;
592 1.6 itohy }
593 1.6 itohy #else
594 1.21 tsutsui volatile uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
595 1.2 minoura
596 1.2 minoura while (count-- > 0) {
597 1.2 minoura *addr++ = *datap++;
598 1.2 minoura }
599 1.6 itohy #endif
600 1.2 minoura }
601 1.2 minoura
602 1.15 perry static __inline void
603 1.2 minoura _bus_space_set_region_1(t, bsh, offset, value, count)
604 1.2 minoura bus_space_tag_t t;
605 1.2 minoura bus_space_handle_t bsh;
606 1.2 minoura bus_size_t offset;
607 1.21 tsutsui uint8_t value;
608 1.2 minoura bus_size_t count;
609 1.2 minoura {
610 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
611 1.21 tsutsui uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
612 1.6 itohy
613 1.6 itohy for (; count; count--) {
614 1.6 itohy __asm("| avoid optim. _bus_space_set_region_1" : : : "memory");
615 1.6 itohy *addr++ = value;
616 1.6 itohy }
617 1.6 itohy #else
618 1.21 tsutsui volatile uint8_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
619 1.2 minoura
620 1.2 minoura while (count-- > 0) {
621 1.2 minoura *addr++ = value;
622 1.2 minoura }
623 1.6 itohy #endif
624 1.2 minoura }
625 1.2 minoura
626 1.15 perry static __inline void
627 1.2 minoura _bus_space_set_region_2(t, bsh, offset, value, count)
628 1.2 minoura bus_space_tag_t t;
629 1.2 minoura bus_space_handle_t bsh;
630 1.2 minoura bus_size_t offset;
631 1.21 tsutsui uint16_t value;
632 1.2 minoura bus_size_t count;
633 1.2 minoura {
634 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
635 1.21 tsutsui uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
636 1.6 itohy
637 1.6 itohy for (; count; count--) {
638 1.6 itohy __asm("| avoid optim. _bus_space_set_region_2" : : : "memory");
639 1.6 itohy *addr++ = value;
640 1.6 itohy }
641 1.6 itohy #else
642 1.21 tsutsui volatile uint16_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
643 1.2 minoura
644 1.2 minoura while (count-- > 0) {
645 1.2 minoura *addr++ = value;
646 1.2 minoura }
647 1.6 itohy #endif
648 1.2 minoura }
649 1.2 minoura
650 1.15 perry static __inline void
651 1.2 minoura _bus_space_set_region_4(t, bsh, offset, value, count)
652 1.2 minoura bus_space_tag_t t;
653 1.2 minoura bus_space_handle_t bsh;
654 1.2 minoura bus_size_t offset;
655 1.21 tsutsui uint32_t value;
656 1.2 minoura bus_size_t count;
657 1.2 minoura {
658 1.6 itohy #if X68K_BUS_PERFORMANCE_HACK
659 1.21 tsutsui uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
660 1.6 itohy
661 1.6 itohy for (; count; count--) {
662 1.6 itohy __asm("| avoid optim. _bus_space_set_region_4" : : : "memory");
663 1.6 itohy *addr++ = value;
664 1.6 itohy }
665 1.6 itohy #else
666 1.21 tsutsui volatile uint32_t *addr = (void *) __X68K_BUS_ADDR(t, bsh, offset);
667 1.2 minoura
668 1.2 minoura while (count-- > 0) {
669 1.2 minoura *addr++ = value;
670 1.2 minoura }
671 1.6 itohy #endif
672 1.2 minoura }
673 1.2 minoura
674 1.15 perry static __inline void
675 1.2 minoura _bus_space_copy_region_1(t, sbsh, soffset, dbsh, doffset, count)
676 1.2 minoura bus_space_tag_t t;
677 1.2 minoura bus_space_handle_t sbsh;
678 1.2 minoura bus_size_t soffset;
679 1.2 minoura bus_space_handle_t dbsh;
680 1.2 minoura bus_size_t doffset;
681 1.2 minoura bus_size_t count;
682 1.2 minoura {
683 1.21 tsutsui volatile uint8_t *saddr = (void *) (sbsh + soffset);
684 1.21 tsutsui volatile uint8_t *daddr = (void *) (dbsh + doffset);
685 1.2 minoura
686 1.21 tsutsui if ((uint32_t) saddr >= (uint32_t) daddr)
687 1.2 minoura while (count-- > 0)
688 1.2 minoura *daddr++ = *saddr++;
689 1.2 minoura else {
690 1.2 minoura saddr += count;
691 1.2 minoura daddr += count;
692 1.2 minoura while (count-- > 0)
693 1.2 minoura *--daddr = *--saddr;
694 1.2 minoura }
695 1.2 minoura }
696 1.2 minoura
697 1.15 perry static __inline void
698 1.2 minoura _bus_space_copy_region_2(t, sbsh, soffset, dbsh, doffset, count)
699 1.2 minoura bus_space_tag_t t;
700 1.2 minoura bus_space_handle_t sbsh;
701 1.2 minoura bus_size_t soffset;
702 1.2 minoura bus_space_handle_t dbsh;
703 1.2 minoura bus_size_t doffset;
704 1.2 minoura bus_size_t count;
705 1.2 minoura {
706 1.21 tsutsui volatile uint16_t *saddr = (void *) (sbsh + soffset);
707 1.21 tsutsui volatile uint16_t *daddr = (void *) (dbsh + doffset);
708 1.2 minoura
709 1.21 tsutsui if ((uint32_t) saddr >= (uint32_t) daddr)
710 1.2 minoura while (count-- > 0)
711 1.2 minoura *daddr++ = *saddr++;
712 1.2 minoura else {
713 1.2 minoura saddr += count;
714 1.2 minoura daddr += count;
715 1.2 minoura while (count-- > 0)
716 1.2 minoura *--daddr = *--saddr;
717 1.2 minoura }
718 1.2 minoura }
719 1.2 minoura
720 1.15 perry static __inline void
721 1.2 minoura _bus_space_copy_region_4(t, sbsh, soffset, dbsh, doffset, count)
722 1.2 minoura bus_space_tag_t t;
723 1.2 minoura bus_space_handle_t sbsh;
724 1.2 minoura bus_size_t soffset;
725 1.2 minoura bus_space_handle_t dbsh;
726 1.2 minoura bus_size_t doffset;
727 1.2 minoura bus_size_t count;
728 1.2 minoura {
729 1.21 tsutsui volatile uint32_t *saddr = (void *) (sbsh + soffset);
730 1.21 tsutsui volatile uint32_t *daddr = (void *) (dbsh + doffset);
731 1.2 minoura
732 1.21 tsutsui if ((uint32_t) saddr >= (uint32_t) daddr)
733 1.2 minoura while (count-- > 0)
734 1.2 minoura *daddr++ = *saddr++;
735 1.2 minoura else {
736 1.2 minoura saddr += count;
737 1.2 minoura daddr += count;
738 1.2 minoura while (count-- > 0)
739 1.2 minoura *--daddr = *--saddr;
740 1.2 minoura }
741 1.2 minoura }
742 1.2 minoura
743 1.3 drochner #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
744 1.2 minoura
745 1.2 minoura /*
746 1.2 minoura * DMA segment
747 1.2 minoura */
748 1.2 minoura struct x68k_bus_dma_segment {
749 1.2 minoura bus_addr_t ds_addr;
750 1.2 minoura bus_size_t ds_len;
751 1.2 minoura };
752 1.2 minoura typedef struct x68k_bus_dma_segment bus_dma_segment_t;
753 1.2 minoura
754 1.2 minoura /*
755 1.2 minoura * DMA descriptor
756 1.2 minoura */
757 1.2 minoura /* Forwards needed by prototypes below. */
758 1.2 minoura struct mbuf;
759 1.2 minoura struct uio;
760 1.2 minoura
761 1.2 minoura typedef struct x68k_bus_dma *bus_dma_tag_t;
762 1.2 minoura typedef struct x68k_bus_dmamap *bus_dmamap_t;
763 1.11 fvdl
764 1.11 fvdl #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
765 1.11 fvdl
766 1.2 minoura struct x68k_bus_dma {
767 1.2 minoura /*
768 1.2 minoura * The `bounce threshold' is checked while we are loading
769 1.2 minoura * the DMA map. If the physical address of the segment
770 1.2 minoura * exceeds the threshold, an error will be returned. The
771 1.2 minoura * caller can then take whatever action is necessary to
772 1.2 minoura * bounce the transfer. If this value is 0, it will be
773 1.2 minoura * ignored.
774 1.2 minoura */
775 1.2 minoura bus_addr_t _bounce_thresh;
776 1.2 minoura
777 1.2 minoura /*
778 1.2 minoura * DMA mapping methods.
779 1.2 minoura */
780 1.12 chs int (*x68k_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
781 1.12 chs bus_size_t, bus_size_t, int, bus_dmamap_t *);
782 1.12 chs void (*x68k_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
783 1.12 chs int (*x68k_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
784 1.12 chs bus_size_t, struct proc *, int);
785 1.12 chs int (*x68k_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
786 1.12 chs struct mbuf *, int);
787 1.12 chs int (*x68k_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
788 1.12 chs struct uio *, int);
789 1.12 chs int (*x68k_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
790 1.12 chs bus_dma_segment_t *, int, bus_size_t, int);
791 1.12 chs void (*x68k_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
792 1.12 chs void (*x68k_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
793 1.12 chs bus_addr_t, bus_size_t, int);
794 1.2 minoura
795 1.2 minoura /*
796 1.2 minoura * DMA memory utility functions.
797 1.2 minoura */
798 1.12 chs int (*x68k_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
799 1.12 chs bus_size_t, bus_dma_segment_t *, int, int *, int);
800 1.12 chs void (*x68k_dmamem_free)(bus_dma_tag_t,
801 1.12 chs bus_dma_segment_t *, int);
802 1.12 chs int (*x68k_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
803 1.17 christos int, size_t, void **, int);
804 1.17 christos void (*x68k_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
805 1.12 chs paddr_t (*x68k_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
806 1.12 chs int, off_t, int, int);
807 1.2 minoura };
808 1.2 minoura
809 1.2 minoura /*
810 1.2 minoura * bus_dmamap_t
811 1.2 minoura *
812 1.2 minoura * Describes a DMA mapping.
813 1.2 minoura */
814 1.2 minoura struct x68k_bus_dmamap {
815 1.2 minoura /*
816 1.2 minoura * PRIVATE MEMBERS: not for use my machine-independent code.
817 1.2 minoura */
818 1.2 minoura bus_size_t x68k_dm_size; /* largest DMA transfer mappable */
819 1.2 minoura int x68k_dm_segcnt; /* number of segs this map can map */
820 1.13 matt bus_size_t x68k_dm_maxmaxsegsz; /* fixed largest possible segment*/
821 1.2 minoura bus_size_t x68k_dm_boundary; /* don't cross this */
822 1.2 minoura bus_addr_t x68k_dm_bounce_thresh; /* bounce threshold */
823 1.2 minoura int x68k_dm_flags; /* misc. flags */
824 1.2 minoura
825 1.2 minoura void *x68k_dm_cookie; /* cookie for bus-specific functions */
826 1.2 minoura
827 1.2 minoura /*
828 1.2 minoura * PUBLIC MEMBERS: these are used by machine-independent code.
829 1.2 minoura */
830 1.13 matt bus_size_t dm_maxsegsz; /* largest possible segment */
831 1.2 minoura bus_size_t dm_mapsize; /* size of the mapping */
832 1.2 minoura int dm_nsegs; /* # valid segments in mapping */
833 1.2 minoura bus_dma_segment_t dm_segs[1]; /* segments; variable length */
834 1.2 minoura };
835 1.2 minoura
836 1.12 chs int x68k_bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
837 1.12 chs bus_size_t, int, bus_dmamap_t *);
838 1.12 chs void x68k_bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
839 1.12 chs int x68k_bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
840 1.12 chs bus_size_t, struct proc *, int);
841 1.12 chs int x68k_bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
842 1.12 chs struct mbuf *, int);
843 1.12 chs int x68k_bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
844 1.12 chs struct uio *, int);
845 1.12 chs int x68k_bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
846 1.12 chs bus_dma_segment_t *, int, bus_size_t, int);
847 1.12 chs void x68k_bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
848 1.12 chs void x68k_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
849 1.12 chs bus_size_t, int);
850 1.2 minoura
851 1.12 chs int x68k_bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
852 1.2 minoura bus_size_t alignment, bus_size_t boundary,
853 1.12 chs bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
854 1.12 chs void x68k_bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
855 1.12 chs int nsegs);
856 1.12 chs int x68k_bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
857 1.17 christos int nsegs, size_t size, void **kvap, int flags);
858 1.17 christos void x68k_bus_dmamem_unmap(bus_dma_tag_t tag, void *kva,
859 1.12 chs size_t size);
860 1.12 chs paddr_t x68k_bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
861 1.12 chs int nsegs, off_t off, int prot, int flags);
862 1.12 chs
863 1.12 chs int x68k_bus_dmamap_load_buffer(bus_dmamap_t, void *,
864 1.12 chs bus_size_t buflen, struct proc *, int, paddr_t *, int *, int);
865 1.12 chs int x68k_bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
866 1.2 minoura bus_size_t alignment, bus_size_t boundary,
867 1.2 minoura bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
868 1.12 chs paddr_t low, paddr_t high);
869 1.2 minoura
870 1.2 minoura #define bus_dmamap_create(t,s,n,m,b,f,p) \
871 1.2 minoura ((*((t)->x68k_dmamap_create)) ((t),(s),(n),(m),(b),(f),(p)))
872 1.2 minoura #define bus_dmamap_destroy(t,p) \
873 1.2 minoura ((*((t)->x68k_dmamap_destroy)) ((t),(p)))
874 1.2 minoura #define bus_dmamap_load(t,m,b,s,p,f) \
875 1.2 minoura ((*((t)->x68k_dmamap_load)) ((t),(m),(b),(s),(p),(f)))
876 1.2 minoura #define bus_dmamap_load_mbuf(t,m,b,f) \
877 1.2 minoura ((*((t)->x68k_dmamap_load_mbuf)) ((t),(m),(b),(f)))
878 1.2 minoura #define bus_dmamap_load_uio(t,m,u,f) \
879 1.2 minoura ((*((t)->x68k_dmamap_load_uio)) ((t),(m),(u),(f)))
880 1.2 minoura #define bus_dmamap_load_raw(t,m,sg,n,s,f) \
881 1.2 minoura ((*((t)->x68k_dmamap_load_raw)) ((t),(m),(sg),(n),(s),(f)))
882 1.2 minoura #define bus_dmamap_unload(t,p) \
883 1.2 minoura ((*((t)->x68k_dmamap_unload)) ((t),(p)))
884 1.2 minoura #define bus_dmamap_sync(t,p,o,l,ops) \
885 1.2 minoura ((*((t)->x68k_dmamap_sync)) ((t),(p),(o),(l),(ops)))
886 1.2 minoura
887 1.2 minoura #define bus_dmamem_alloc(t,s,a,b,sg,n,r,f) \
888 1.2 minoura ((*((t)->x68k_dmamem_alloc)) ((t),(s),(a),(b),(sg),(n),(r),(f)))
889 1.2 minoura #define bus_dmamem_free(t,sg,n) \
890 1.2 minoura ((*((t)->x68k_dmamem_free)) ((t),(sg),(n)))
891 1.2 minoura #define bus_dmamem_map(t,sg,n,s,k,f) \
892 1.2 minoura ((*((t)->x68k_dmamem_map)) ((t),(sg),(n),(s),(k),(f)))
893 1.2 minoura #define bus_dmamem_unmap(t,k,s) \
894 1.2 minoura ((*((t)->x68k_dmamem_unmap)) ((t),(k),(s)))
895 1.2 minoura #define bus_dmamem_mmap(t,sg,n,o,p,f) \
896 1.2 minoura ((*((t)->x68k_dmamem_mmap)) ((t),(sg),(n),(o),(p),(f)))
897 1.2 minoura
898 1.16 mrg #define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP
899 1.16 mrg #define bus_dmatag_destroy(t)
900 1.16 mrg
901 1.2 minoura /*
902 1.2 minoura * Flags used in various bus DMA methods.
903 1.2 minoura */
904 1.8 thorpej #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
905 1.8 thorpej #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
906 1.8 thorpej #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
907 1.8 thorpej #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
908 1.8 thorpej #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
909 1.8 thorpej #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
910 1.8 thorpej #define BUS_DMA_BUS2 0x020
911 1.8 thorpej #define BUS_DMA_BUS3 0x040
912 1.8 thorpej #define BUS_DMA_BUS4 0x080
913 1.8 thorpej #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
914 1.8 thorpej #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
915 1.10 kent #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
916 1.2 minoura
917 1.2 minoura /*
918 1.2 minoura * Operations performed by bus_dmamap_sync().
919 1.2 minoura */
920 1.2 minoura #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
921 1.2 minoura #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
922 1.2 minoura #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
923 1.2 minoura #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
924 1.2 minoura
925 1.2 minoura #endif /* _X68K_BUS_H_ */
926