cpu.h revision 1.2
1 /* $NetBSD: cpu.h,v 1.2 1996/05/21 15:32:53 oki Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 #ifndef _X68K_CPU_H_ 46 #define _X68K_CPU_H_ 47 48 /* 49 * Exported definitions unique to x68k/68k cpu support. 50 */ 51 52 /* 53 * definitions of cpu-dependent requirements 54 * referenced in generic code 55 */ 56 #define cpu_swapin(p) /* nothing */ 57 #define cpu_wait(p) /* nothing */ 58 #define cpu_swapout(p) /* nothing */ 59 60 /* 61 * Arguments to hardclock and gatherstats encapsulate the previous 62 * machine state in an opaque clockframe. One the x68k, we use 63 * what the hardware pushes on an interrupt (frame format 0). 64 */ 65 struct clockframe { 66 u_short sr; /* sr at time of interrupt */ 67 u_long pc; /* pc at time of interrupt */ 68 u_short vo; /* vector offset (4-word frame) */ 69 }; 70 71 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 72 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 73 #define CLKF_PC(framep) ((framep)->pc) 74 #if 0 75 /* We would like to do it this way... */ 76 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 77 #else 78 /* but until we start using PSL_M, we have to do this instead */ 79 #define CLKF_INTR(framep) (0) /* XXX */ 80 #endif 81 82 83 /* 84 * Preempt the current process if in interrupt from user mode, 85 * or after the current trap/syscall if in system mode. 86 */ 87 #define need_resched() { want_resched++; aston(); } 88 89 /* 90 * Give a profiling tick to the current process when the user profiling 91 * buffer pages are invalid. On the x68k, request an ast to send us 92 * through trap, marking the proc as needing a profiling tick. 93 */ 94 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 95 96 /* 97 * Notify the current process (p) that it has a signal pending, 98 * process as soon as possible. 99 */ 100 #define signotify(p) aston() 101 102 #define aston() (astpending++) 103 104 int astpending; /* need to trap before returning to user mode */ 105 int want_resched; /* resched() was called */ 106 107 108 /* 109 * simulated software interrupt register 110 */ 111 extern unsigned char ssir; 112 113 #define SIR_NET 0x1 114 #define SIR_CLOCK 0x2 115 #define SIR_SERIAL 0x4 116 #define SIR_KBD 0x8 117 118 #define siroff(x) ssir &= ~(x) 119 #define setsoftnet() ssir |= SIR_NET 120 #define setsoftclock() ssir |= SIR_CLOCK 121 #define setsoftserial() ssir |= SIR_SERIAL 122 #define setsoftkbd() ssir |= SIR_KBD 123 124 /* 125 * CTL_MACHDEP definitions. 126 */ 127 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 128 #define CPU_MAXID 2 /* number of valid machdep ids */ 129 130 #define CTL_MACHDEP_NAMES { \ 131 { 0, 0 }, \ 132 { "console_device", CTLTYPE_STRUCT }, \ 133 } 134 135 /* 136 * The rest of this should probably be moved to ../x68k/x68kcpu.h, 137 * although some of it could probably be put into generic 68k headers. 138 */ 139 140 /* values for machineid */ 141 142 /* values for mmutype (assigned for quick testing) */ 143 #define MMU_68040 -2 /* 68040 on-chip MMU */ 144 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 145 #define MMU_68851 1 /* Motorola 68851 */ 146 147 /* values for ectype */ 148 #define EC_PHYS -1 /* external physical address cache */ 149 #define EC_NONE 0 /* no external cache */ 150 #define EC_VIRT 1 /* external virtual address cache */ 151 152 /* values for cpuspeed (not really related to clock speed due to caches) */ 153 #define MHZ_8 1 154 #define MHZ_16 2 155 #define MHZ_25 3 156 #define MHZ_33 4 157 #define MHZ_50 6 158 159 #ifdef _KERNEL 160 extern int machineid, mmutype; 161 extern char *intiolimit; 162 163 /* autoconf.c */ 164 void configure __P((void)); 165 166 /* machdep.c */ 167 void dumpconf __P((void)); 168 void dumpsys __P((void)); 169 170 /* locore.s */ 171 struct pcb; 172 struct fpframe; 173 void savectx __P((struct pcb *)); 174 void switch_exit __P((struct proc *)); 175 void proc_trampoline __P((void)); 176 u_long getdfc __P((void)); 177 u_long getsfc __P((void)); 178 void loadustp __P((int)); 179 void m68881_save __P((struct fpframe *)); 180 void m68881_restore __P((struct fpframe *)); 181 void DCIS __P((void)); 182 void DCIU __P((void)); 183 void ICIA __P((void)); 184 void ICPA __P((void)); 185 void PCIA __P((void)); 186 void TBIA __P((void)); 187 void TBIS __P((vm_offset_t)); 188 void TBIAS __P((void)); 189 void TBIAU __P((void)); 190 #if defined(M68040) || defined(M68060) 191 void DCFA __P((void)); 192 void DCFP __P((vm_offset_t)); 193 void DCFL __P((vm_offset_t)); 194 void DCPL __P((vm_offset_t)); 195 void DCPP __P((vm_offset_t)); 196 void ICPL __P((vm_offset_t)); 197 void ICPP __P((vm_offset_t)); 198 #endif 199 200 /* sys_machdep.c */ 201 int cachectl __P((int, caddr_t, int)); 202 int dma_cachectl __P((caddr_t, int)); 203 204 /* vm_machdep.c */ 205 int kvtop __P((caddr_t)); 206 207 #ifdef GENERIC 208 /* swapgeneric.c */ 209 void setconf __P((void)); 210 #endif /* GENERIC */ 211 212 #endif 213 214 /* physical memory sections */ 215 #define INTIOBASE (0x00C00000) 216 #define INTIOTOP (0x01000000) 217 218 /* 219 * Internal IO space: 220 * 221 * Ranges from 0xC00000 to 0x1000000 (IIOMAPSIZE). 222 * 223 * Internal IO space is mapped in the kernel from ``IODEVbase'' to 224 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 225 * conversion between physical and kernel virtual addresses is easy. 226 */ 227 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 228 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 4mb */ 229 230 /* 231 * External IO space: 232 */ 233 234 /* 235 * 68851 and 68030 MMU 236 */ 237 #define PMMU_LVLMASK 0x0007 238 #define PMMU_INV 0x0400 239 #define PMMU_WP 0x0800 240 #define PMMU_ALV 0x1000 241 #define PMMU_SO 0x2000 242 #define PMMU_LV 0x4000 243 #define PMMU_BE 0x8000 244 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 245 246 /* 247 * 68040 MMU 248 */ 249 #define MMU4_RES 0x001 250 #define MMU4_TTR 0x002 251 #define MMU4_WP 0x004 252 #define MMU4_MOD 0x010 253 #define MMU4_CMMASK 0x060 254 #define MMU4_SUP 0x080 255 #define MMU4_U0 0x100 256 #define MMU4_U1 0x200 257 #define MMU4_GLB 0x400 258 #define MMU4_BE 0x800 259 260 /* 680X0 function codes */ 261 #define FC_USERD 1 /* user data space */ 262 #define FC_USERP 2 /* user program space */ 263 #define FC_SUPERD 5 /* supervisor data space */ 264 #define FC_SUPERP 6 /* supervisor program space */ 265 #define FC_CPU 7 /* CPU space */ 266 267 /* fields in the 68020 cache control register */ 268 #define IC_ENABLE 0x0001 /* enable instruction cache */ 269 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 270 #define IC_CE 0x0004 /* clear instruction cache entry */ 271 #define IC_CLR 0x0008 /* clear entire instruction cache */ 272 273 /* additional fields in the 68030 cache control register */ 274 #define IC_BE 0x0010 /* instruction burst enable */ 275 #define DC_ENABLE 0x0100 /* data cache enable */ 276 #define DC_FREEZE 0x0200 /* data cache freeze */ 277 #define DC_CE 0x0400 /* clear data cache entry */ 278 #define DC_CLR 0x0800 /* clear entire data cache */ 279 #define DC_BE 0x1000 /* data burst enable */ 280 #define DC_WA 0x2000 /* write allocate */ 281 282 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 283 #define CACHE_OFF (DC_CLR|IC_CLR) 284 #define CACHE_CLR (CACHE_ON) 285 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 286 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 287 288 /* 68040 cache control register */ 289 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 290 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 291 292 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 293 #define CACHE4_OFF (0) 294 295 #endif /* _X68K_CPU_H_ */ 296
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