acpi_cpu_md.c revision 1.55.2.2
1 1.55.2.2 rmind /* $NetBSD: acpi_cpu_md.c,v 1.55.2.2 2011/03/05 20:52:27 rmind Exp $ */ 2 1.55.2.2 rmind 3 1.55.2.2 rmind /*- 4 1.55.2.2 rmind * Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen (at) iki.fi> 5 1.55.2.2 rmind * All rights reserved. 6 1.55.2.2 rmind * 7 1.55.2.2 rmind * Redistribution and use in source and binary forms, with or without 8 1.55.2.2 rmind * modification, are permitted provided that the following conditions 9 1.55.2.2 rmind * are met: 10 1.55.2.2 rmind * 11 1.55.2.2 rmind * 1. Redistributions of source code must retain the above copyright 12 1.55.2.2 rmind * notice, this list of conditions and the following disclaimer. 13 1.55.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 14 1.55.2.2 rmind * notice, this list of conditions and the following disclaimer in the 15 1.55.2.2 rmind * documentation and/or other materials provided with the distribution. 16 1.55.2.2 rmind * 17 1.55.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 1.55.2.2 rmind * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 1.55.2.2 rmind * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 1.55.2.2 rmind * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 1.55.2.2 rmind * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 1.55.2.2 rmind * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 1.55.2.2 rmind * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.55.2.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 1.55.2.2 rmind * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.55.2.2 rmind * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.55.2.2 rmind * SUCH DAMAGE. 28 1.55.2.2 rmind */ 29 1.55.2.2 rmind #include <sys/cdefs.h> 30 1.55.2.2 rmind __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.55.2.2 2011/03/05 20:52:27 rmind Exp $"); 31 1.55.2.2 rmind 32 1.55.2.2 rmind #include <sys/param.h> 33 1.55.2.2 rmind #include <sys/bus.h> 34 1.55.2.2 rmind #include <sys/device.h> 35 1.55.2.2 rmind #include <sys/kcore.h> 36 1.55.2.2 rmind #include <sys/sysctl.h> 37 1.55.2.2 rmind #include <sys/xcall.h> 38 1.55.2.2 rmind 39 1.55.2.2 rmind #include <x86/cpu.h> 40 1.55.2.2 rmind #include <x86/cpufunc.h> 41 1.55.2.2 rmind #include <x86/cputypes.h> 42 1.55.2.2 rmind #include <x86/cpuvar.h> 43 1.55.2.2 rmind #include <x86/cpu_msr.h> 44 1.55.2.2 rmind #include <x86/machdep.h> 45 1.55.2.2 rmind 46 1.55.2.2 rmind #include <dev/acpi/acpica.h> 47 1.55.2.2 rmind #include <dev/acpi/acpi_cpu.h> 48 1.55.2.2 rmind 49 1.55.2.2 rmind #include <dev/pci/pcivar.h> 50 1.55.2.2 rmind #include <dev/pci/pcidevs.h> 51 1.55.2.2 rmind 52 1.55.2.2 rmind #include <machine/acpi_machdep.h> 53 1.55.2.2 rmind 54 1.55.2.2 rmind /* 55 1.55.2.2 rmind * AMD C1E. 56 1.55.2.2 rmind */ 57 1.55.2.2 rmind #define MSR_CMPHALT 0xc0010055 58 1.55.2.2 rmind 59 1.55.2.2 rmind #define MSR_CMPHALT_SMI __BIT(27) 60 1.55.2.2 rmind #define MSR_CMPHALT_C1E __BIT(28) 61 1.55.2.2 rmind #define MSR_CMPHALT_BMSTS __BIT(29) 62 1.55.2.2 rmind 63 1.55.2.2 rmind /* 64 1.55.2.2 rmind * AMD families 10h, 11h, and 14h 65 1.55.2.2 rmind */ 66 1.55.2.2 rmind #define MSR_10H_LIMIT 0xc0010061 67 1.55.2.2 rmind #define MSR_10H_CONTROL 0xc0010062 68 1.55.2.2 rmind #define MSR_10H_STATUS 0xc0010063 69 1.55.2.2 rmind #define MSR_10H_CONFIG 0xc0010064 70 1.55.2.2 rmind 71 1.55.2.2 rmind /* 72 1.55.2.2 rmind * AMD family 0Fh. 73 1.55.2.2 rmind */ 74 1.55.2.2 rmind #define MSR_0FH_CONTROL 0xc0010041 75 1.55.2.2 rmind #define MSR_0FH_STATUS 0xc0010042 76 1.55.2.2 rmind 77 1.55.2.2 rmind #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 78 1.55.2.2 rmind #define MSR_0FH_STATUS_CVID __BITS(32, 36) 79 1.55.2.2 rmind #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 80 1.55.2.2 rmind 81 1.55.2.2 rmind #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 82 1.55.2.2 rmind #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 83 1.55.2.2 rmind #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 84 1.55.2.2 rmind #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 85 1.55.2.2 rmind 86 1.55.2.2 rmind #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 87 1.55.2.2 rmind #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 88 1.55.2.2 rmind 89 1.55.2.2 rmind #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 90 1.55.2.2 rmind #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 91 1.55.2.2 rmind #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 92 1.55.2.2 rmind #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 93 1.55.2.2 rmind #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 94 1.55.2.2 rmind #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 95 1.55.2.2 rmind #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 96 1.55.2.2 rmind 97 1.55.2.2 rmind #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 98 1.55.2.2 rmind 99 1.55.2.2 rmind static char native_idle_text[16]; 100 1.55.2.2 rmind void (*native_idle)(void) = NULL; 101 1.55.2.2 rmind 102 1.55.2.2 rmind static int acpicpu_md_quirk_piix4(struct pci_attach_args *); 103 1.55.2.2 rmind static void acpicpu_md_pstate_percent_reset(struct acpicpu_softc *); 104 1.55.2.2 rmind static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 105 1.55.2.2 rmind uint32_t *); 106 1.55.2.2 rmind static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 107 1.55.2.2 rmind static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 108 1.55.2.2 rmind static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 109 1.55.2.2 rmind uint32_t, uint32_t); 110 1.55.2.2 rmind static int acpicpu_md_pstate_sysctl_init(void); 111 1.55.2.2 rmind static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 112 1.55.2.2 rmind static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 113 1.55.2.2 rmind static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 114 1.55.2.2 rmind 115 1.55.2.2 rmind extern struct acpicpu_softc **acpicpu_sc; 116 1.55.2.2 rmind static struct sysctllog *acpicpu_log = NULL; 117 1.55.2.2 rmind 118 1.55.2.2 rmind struct cpu_info * 119 1.55.2.2 rmind acpicpu_md_match(device_t parent, cfdata_t match, void *aux) 120 1.55.2.2 rmind { 121 1.55.2.2 rmind struct cpufeature_attach_args *cfaa = aux; 122 1.55.2.2 rmind 123 1.55.2.2 rmind if (strcmp(cfaa->name, "frequency") != 0) 124 1.55.2.2 rmind return NULL; 125 1.55.2.2 rmind 126 1.55.2.2 rmind return cfaa->ci; 127 1.55.2.2 rmind } 128 1.55.2.2 rmind 129 1.55.2.2 rmind struct cpu_info * 130 1.55.2.2 rmind acpicpu_md_attach(device_t parent, device_t self, void *aux) 131 1.55.2.2 rmind { 132 1.55.2.2 rmind struct cpufeature_attach_args *cfaa = aux; 133 1.55.2.2 rmind 134 1.55.2.2 rmind return cfaa->ci; 135 1.55.2.2 rmind } 136 1.55.2.2 rmind 137 1.55.2.2 rmind uint32_t 138 1.55.2.2 rmind acpicpu_md_cap(void) 139 1.55.2.2 rmind { 140 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 141 1.55.2.2 rmind uint32_t regs[4]; 142 1.55.2.2 rmind uint32_t val = 0; 143 1.55.2.2 rmind 144 1.55.2.2 rmind if (cpu_vendor != CPUVENDOR_IDT && 145 1.55.2.2 rmind cpu_vendor != CPUVENDOR_INTEL) 146 1.55.2.2 rmind return val; 147 1.55.2.2 rmind 148 1.55.2.2 rmind /* 149 1.55.2.2 rmind * Basic SMP C-states (required for e.g. _CST). 150 1.55.2.2 rmind */ 151 1.55.2.2 rmind val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 152 1.55.2.2 rmind 153 1.55.2.2 rmind /* 154 1.55.2.2 rmind * Claim to support dependency coordination. 155 1.55.2.2 rmind */ 156 1.55.2.2 rmind val |= ACPICPU_PDC_P_SW | ACPICPU_PDC_C_SW | ACPICPU_PDC_T_SW; 157 1.55.2.2 rmind 158 1.55.2.2 rmind /* 159 1.55.2.2 rmind * If MONITOR/MWAIT is available, announce 160 1.55.2.2 rmind * support for native instructions in all C-states. 161 1.55.2.2 rmind */ 162 1.55.2.2 rmind if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 163 1.55.2.2 rmind val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 164 1.55.2.2 rmind 165 1.55.2.2 rmind /* 166 1.55.2.2 rmind * Set native P- and T-states, if available. 167 1.55.2.2 rmind */ 168 1.55.2.2 rmind if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 169 1.55.2.2 rmind val |= ACPICPU_PDC_P_FFH; 170 1.55.2.2 rmind 171 1.55.2.2 rmind if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 172 1.55.2.2 rmind val |= ACPICPU_PDC_T_FFH; 173 1.55.2.2 rmind 174 1.55.2.2 rmind /* 175 1.55.2.2 rmind * Declare support for APERF and MPERF. 176 1.55.2.2 rmind */ 177 1.55.2.2 rmind if (cpuid_level >= 0x06) { 178 1.55.2.2 rmind 179 1.55.2.2 rmind x86_cpuid(0x00000006, regs); 180 1.55.2.2 rmind 181 1.55.2.2 rmind if ((regs[2] & CPUID_DSPM_HWF) != 0) 182 1.55.2.2 rmind val |= ACPICPU_PDC_P_HWF; 183 1.55.2.2 rmind } 184 1.55.2.2 rmind 185 1.55.2.2 rmind return val; 186 1.55.2.2 rmind } 187 1.55.2.2 rmind 188 1.55.2.2 rmind uint32_t 189 1.55.2.2 rmind acpicpu_md_flags(void) 190 1.55.2.2 rmind { 191 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 192 1.55.2.2 rmind struct pci_attach_args pa; 193 1.55.2.2 rmind uint32_t family, val = 0; 194 1.55.2.2 rmind uint32_t regs[4]; 195 1.55.2.2 rmind 196 1.55.2.2 rmind if (acpi_md_ncpus() == 1) 197 1.55.2.2 rmind val |= ACPICPU_FLAG_C_BM; 198 1.55.2.2 rmind 199 1.55.2.2 rmind if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 200 1.55.2.2 rmind val |= ACPICPU_FLAG_C_FFH; 201 1.55.2.2 rmind 202 1.55.2.2 rmind /* 203 1.55.2.2 rmind * By default, assume that the local APIC timer 204 1.55.2.2 rmind * as well as TSC are stalled during C3 sleep. 205 1.55.2.2 rmind */ 206 1.55.2.2 rmind val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 207 1.55.2.2 rmind 208 1.55.2.2 rmind switch (cpu_vendor) { 209 1.55.2.2 rmind 210 1.55.2.2 rmind case CPUVENDOR_IDT: 211 1.55.2.2 rmind 212 1.55.2.2 rmind if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 213 1.55.2.2 rmind val |= ACPICPU_FLAG_P_FFH; 214 1.55.2.2 rmind 215 1.55.2.2 rmind if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 216 1.55.2.2 rmind val |= ACPICPU_FLAG_T_FFH; 217 1.55.2.2 rmind 218 1.55.2.2 rmind break; 219 1.55.2.2 rmind 220 1.55.2.2 rmind case CPUVENDOR_INTEL: 221 1.55.2.2 rmind 222 1.55.2.2 rmind /* 223 1.55.2.2 rmind * Bus master control and arbitration should be 224 1.55.2.2 rmind * available on all supported Intel CPUs (to be 225 1.55.2.2 rmind * sure, this is double-checked later from the 226 1.55.2.2 rmind * firmware data). These flags imply that it is 227 1.55.2.2 rmind * not necessary to flush caches before C3 state. 228 1.55.2.2 rmind */ 229 1.55.2.2 rmind val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 230 1.55.2.2 rmind 231 1.55.2.2 rmind /* 232 1.55.2.2 rmind * Check if we can use "native", MSR-based, 233 1.55.2.2 rmind * access. If not, we have to resort to I/O. 234 1.55.2.2 rmind */ 235 1.55.2.2 rmind if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 236 1.55.2.2 rmind val |= ACPICPU_FLAG_P_FFH; 237 1.55.2.2 rmind 238 1.55.2.2 rmind if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 239 1.55.2.2 rmind val |= ACPICPU_FLAG_T_FFH; 240 1.55.2.2 rmind 241 1.55.2.2 rmind /* 242 1.55.2.2 rmind * Check whether MSR_APERF, MSR_MPERF, and Turbo 243 1.55.2.2 rmind * Boost are available. Also see if we might have 244 1.55.2.2 rmind * an invariant local APIC timer ("ARAT"). 245 1.55.2.2 rmind */ 246 1.55.2.2 rmind if (cpuid_level >= 0x06) { 247 1.55.2.2 rmind 248 1.55.2.2 rmind x86_cpuid(0x00000006, regs); 249 1.55.2.2 rmind 250 1.55.2.2 rmind if ((regs[2] & CPUID_DSPM_HWF) != 0) 251 1.55.2.2 rmind val |= ACPICPU_FLAG_P_HWF; 252 1.55.2.2 rmind 253 1.55.2.2 rmind if ((regs[0] & CPUID_DSPM_IDA) != 0) 254 1.55.2.2 rmind val |= ACPICPU_FLAG_P_TURBO; 255 1.55.2.2 rmind 256 1.55.2.2 rmind if ((regs[0] & CPUID_DSPM_ARAT) != 0) 257 1.55.2.2 rmind val &= ~ACPICPU_FLAG_C_APIC; 258 1.55.2.2 rmind } 259 1.55.2.2 rmind 260 1.55.2.2 rmind /* 261 1.55.2.2 rmind * Detect whether TSC is invariant. If it is not, 262 1.55.2.2 rmind * we keep the flag to note that TSC will not run 263 1.55.2.2 rmind * at constant rate. Depending on the CPU, this may 264 1.55.2.2 rmind * affect P- and T-state changes, but especially 265 1.55.2.2 rmind * relevant are C-states; with variant TSC, states 266 1.55.2.2 rmind * larger than C1 may completely stop the counter. 267 1.55.2.2 rmind */ 268 1.55.2.2 rmind x86_cpuid(0x80000000, regs); 269 1.55.2.2 rmind 270 1.55.2.2 rmind if (regs[0] >= 0x80000007) { 271 1.55.2.2 rmind 272 1.55.2.2 rmind x86_cpuid(0x80000007, regs); 273 1.55.2.2 rmind 274 1.55.2.2 rmind if ((regs[3] & __BIT(8)) != 0) 275 1.55.2.2 rmind val &= ~ACPICPU_FLAG_C_TSC; 276 1.55.2.2 rmind } 277 1.55.2.2 rmind 278 1.55.2.2 rmind break; 279 1.55.2.2 rmind 280 1.55.2.2 rmind case CPUVENDOR_AMD: 281 1.55.2.2 rmind 282 1.55.2.2 rmind x86_cpuid(0x80000000, regs); 283 1.55.2.2 rmind 284 1.55.2.2 rmind if (regs[0] < 0x80000007) 285 1.55.2.2 rmind break; 286 1.55.2.2 rmind 287 1.55.2.2 rmind x86_cpuid(0x80000007, regs); 288 1.55.2.2 rmind 289 1.55.2.2 rmind family = CPUID2FAMILY(ci->ci_signature); 290 1.55.2.2 rmind 291 1.55.2.2 rmind if (family == 0xf) 292 1.55.2.2 rmind family += CPUID2EXTFAMILY(ci->ci_signature); 293 1.55.2.2 rmind 294 1.55.2.2 rmind switch (family) { 295 1.55.2.2 rmind 296 1.55.2.2 rmind case 0x0f: 297 1.55.2.2 rmind 298 1.55.2.2 rmind /* 299 1.55.2.2 rmind * Evaluate support for the "FID/VID 300 1.55.2.2 rmind * algorithm" also used by powernow(4). 301 1.55.2.2 rmind */ 302 1.55.2.2 rmind if ((regs[3] & CPUID_APM_FID) == 0) 303 1.55.2.2 rmind break; 304 1.55.2.2 rmind 305 1.55.2.2 rmind if ((regs[3] & CPUID_APM_VID) == 0) 306 1.55.2.2 rmind break; 307 1.55.2.2 rmind 308 1.55.2.2 rmind val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 309 1.55.2.2 rmind break; 310 1.55.2.2 rmind 311 1.55.2.2 rmind case 0x10: 312 1.55.2.2 rmind case 0x11: 313 1.55.2.2 rmind val |= ACPICPU_FLAG_C_C1E; 314 1.55.2.2 rmind /* FALLTHROUGH */ 315 1.55.2.2 rmind 316 1.55.2.2 rmind case 0x14: /* AMD Fusion */ 317 1.55.2.2 rmind 318 1.55.2.2 rmind /* 319 1.55.2.2 rmind * Like with Intel, detect invariant TSC, 320 1.55.2.2 rmind * MSR-based P-states, and AMD's "turbo" 321 1.55.2.2 rmind * (Core Performance Boost), respectively. 322 1.55.2.2 rmind */ 323 1.55.2.2 rmind if ((regs[3] & CPUID_APM_TSC) != 0) 324 1.55.2.2 rmind val &= ~ACPICPU_FLAG_C_TSC; 325 1.55.2.2 rmind 326 1.55.2.2 rmind if ((regs[3] & CPUID_APM_HWP) != 0) 327 1.55.2.2 rmind val |= ACPICPU_FLAG_P_FFH; 328 1.55.2.2 rmind 329 1.55.2.2 rmind if ((regs[3] & CPUID_APM_CPB) != 0) 330 1.55.2.2 rmind val |= ACPICPU_FLAG_P_TURBO; 331 1.55.2.2 rmind 332 1.55.2.2 rmind /* 333 1.55.2.2 rmind * Also check for APERF and MPERF, 334 1.55.2.2 rmind * first available in the family 10h. 335 1.55.2.2 rmind */ 336 1.55.2.2 rmind if (cpuid_level >= 0x06) { 337 1.55.2.2 rmind 338 1.55.2.2 rmind x86_cpuid(0x00000006, regs); 339 1.55.2.2 rmind 340 1.55.2.2 rmind if ((regs[2] & CPUID_DSPM_HWF) != 0) 341 1.55.2.2 rmind val |= ACPICPU_FLAG_P_HWF; 342 1.55.2.2 rmind } 343 1.55.2.2 rmind 344 1.55.2.2 rmind break; 345 1.55.2.2 rmind } 346 1.55.2.2 rmind 347 1.55.2.2 rmind break; 348 1.55.2.2 rmind } 349 1.55.2.2 rmind 350 1.55.2.2 rmind /* 351 1.55.2.2 rmind * There are several erratums for PIIX4. 352 1.55.2.2 rmind */ 353 1.55.2.2 rmind if (pci_find_device(&pa, acpicpu_md_quirk_piix4) != 0) 354 1.55.2.2 rmind val |= ACPICPU_FLAG_PIIX4; 355 1.55.2.2 rmind 356 1.55.2.2 rmind return val; 357 1.55.2.2 rmind } 358 1.55.2.2 rmind 359 1.55.2.2 rmind static int 360 1.55.2.2 rmind acpicpu_md_quirk_piix4(struct pci_attach_args *pa) 361 1.55.2.2 rmind { 362 1.55.2.2 rmind 363 1.55.2.2 rmind /* 364 1.55.2.2 rmind * XXX: The pci_find_device(9) function only 365 1.55.2.2 rmind * deals with attached devices. Change this 366 1.55.2.2 rmind * to use something like pci_device_foreach(). 367 1.55.2.2 rmind */ 368 1.55.2.2 rmind if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 369 1.55.2.2 rmind return 0; 370 1.55.2.2 rmind 371 1.55.2.2 rmind if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 372 1.55.2.2 rmind PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 373 1.55.2.2 rmind return 1; 374 1.55.2.2 rmind 375 1.55.2.2 rmind return 0; 376 1.55.2.2 rmind } 377 1.55.2.2 rmind 378 1.55.2.2 rmind void 379 1.55.2.2 rmind acpicpu_md_quirk_c1e(void) 380 1.55.2.2 rmind { 381 1.55.2.2 rmind const uint64_t c1e = MSR_CMPHALT_SMI | MSR_CMPHALT_C1E; 382 1.55.2.2 rmind uint64_t val; 383 1.55.2.2 rmind 384 1.55.2.2 rmind val = rdmsr(MSR_CMPHALT); 385 1.55.2.2 rmind 386 1.55.2.2 rmind if ((val & c1e) != 0) 387 1.55.2.2 rmind wrmsr(MSR_CMPHALT, val & ~c1e); 388 1.55.2.2 rmind } 389 1.55.2.2 rmind 390 1.55.2.2 rmind int 391 1.55.2.2 rmind acpicpu_md_cstate_start(struct acpicpu_softc *sc) 392 1.55.2.2 rmind { 393 1.55.2.2 rmind const size_t size = sizeof(native_idle_text); 394 1.55.2.2 rmind struct acpicpu_cstate *cs; 395 1.55.2.2 rmind bool ipi = false; 396 1.55.2.2 rmind int i; 397 1.55.2.2 rmind 398 1.55.2.2 rmind /* 399 1.55.2.2 rmind * Save the cpu_idle(9) loop used by default. 400 1.55.2.2 rmind */ 401 1.55.2.2 rmind x86_cpu_idle_get(&native_idle, native_idle_text, size); 402 1.55.2.2 rmind 403 1.55.2.2 rmind for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 404 1.55.2.2 rmind 405 1.55.2.2 rmind cs = &sc->sc_cstate[i]; 406 1.55.2.2 rmind 407 1.55.2.2 rmind if (cs->cs_method == ACPICPU_C_STATE_HALT) { 408 1.55.2.2 rmind ipi = true; 409 1.55.2.2 rmind break; 410 1.55.2.2 rmind } 411 1.55.2.2 rmind } 412 1.55.2.2 rmind 413 1.55.2.2 rmind x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 414 1.55.2.2 rmind 415 1.55.2.2 rmind return 0; 416 1.55.2.2 rmind } 417 1.55.2.2 rmind 418 1.55.2.2 rmind int 419 1.55.2.2 rmind acpicpu_md_cstate_stop(void) 420 1.55.2.2 rmind { 421 1.55.2.2 rmind uint64_t xc; 422 1.55.2.2 rmind bool ipi; 423 1.55.2.2 rmind 424 1.55.2.2 rmind ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 425 1.55.2.2 rmind x86_cpu_idle_set(native_idle, native_idle_text, ipi); 426 1.55.2.2 rmind 427 1.55.2.2 rmind /* 428 1.55.2.2 rmind * Run a cross-call to ensure that all CPUs are 429 1.55.2.2 rmind * out from the ACPI idle-loop before detachment. 430 1.55.2.2 rmind */ 431 1.55.2.2 rmind xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 432 1.55.2.2 rmind xc_wait(xc); 433 1.55.2.2 rmind 434 1.55.2.2 rmind return 0; 435 1.55.2.2 rmind } 436 1.55.2.2 rmind 437 1.55.2.2 rmind /* 438 1.55.2.2 rmind * Called with interrupts disabled. 439 1.55.2.2 rmind * Caller should enable interrupts after return. 440 1.55.2.2 rmind */ 441 1.55.2.2 rmind void 442 1.55.2.2 rmind acpicpu_md_cstate_enter(int method, int state) 443 1.55.2.2 rmind { 444 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 445 1.55.2.2 rmind 446 1.55.2.2 rmind switch (method) { 447 1.55.2.2 rmind 448 1.55.2.2 rmind case ACPICPU_C_STATE_FFH: 449 1.55.2.2 rmind 450 1.55.2.2 rmind x86_enable_intr(); 451 1.55.2.2 rmind x86_monitor(&ci->ci_want_resched, 0, 0); 452 1.55.2.2 rmind 453 1.55.2.2 rmind if (__predict_false(ci->ci_want_resched != 0)) 454 1.55.2.2 rmind return; 455 1.55.2.2 rmind 456 1.55.2.2 rmind x86_mwait((state - 1) << 4, 0); 457 1.55.2.2 rmind break; 458 1.55.2.2 rmind 459 1.55.2.2 rmind case ACPICPU_C_STATE_HALT: 460 1.55.2.2 rmind 461 1.55.2.2 rmind if (__predict_false(ci->ci_want_resched != 0)) 462 1.55.2.2 rmind return; 463 1.55.2.2 rmind 464 1.55.2.2 rmind x86_stihlt(); 465 1.55.2.2 rmind break; 466 1.55.2.2 rmind } 467 1.55.2.2 rmind } 468 1.55.2.2 rmind 469 1.55.2.2 rmind int 470 1.55.2.2 rmind acpicpu_md_pstate_start(struct acpicpu_softc *sc) 471 1.55.2.2 rmind { 472 1.55.2.2 rmind const uint64_t est = __BIT(16); 473 1.55.2.2 rmind uint64_t val; 474 1.55.2.2 rmind 475 1.55.2.2 rmind if ((sc->sc_flags & ACPICPU_FLAG_P) == 0) 476 1.55.2.2 rmind return ENODEV; 477 1.55.2.2 rmind 478 1.55.2.2 rmind switch (cpu_vendor) { 479 1.55.2.2 rmind 480 1.55.2.2 rmind case CPUVENDOR_IDT: 481 1.55.2.2 rmind case CPUVENDOR_INTEL: 482 1.55.2.2 rmind 483 1.55.2.2 rmind /* 484 1.55.2.2 rmind * Make sure EST is enabled. 485 1.55.2.2 rmind */ 486 1.55.2.2 rmind val = rdmsr(MSR_MISC_ENABLE); 487 1.55.2.2 rmind 488 1.55.2.2 rmind if ((val & est) == 0) { 489 1.55.2.2 rmind 490 1.55.2.2 rmind val |= est; 491 1.55.2.2 rmind 492 1.55.2.2 rmind wrmsr(MSR_MISC_ENABLE, val); 493 1.55.2.2 rmind val = rdmsr(MSR_MISC_ENABLE); 494 1.55.2.2 rmind 495 1.55.2.2 rmind if ((val & est) == 0) 496 1.55.2.2 rmind return ENOTTY; 497 1.55.2.2 rmind } 498 1.55.2.2 rmind } 499 1.55.2.2 rmind 500 1.55.2.2 rmind /* 501 1.55.2.2 rmind * Reset the APERF and MPERF counters. 502 1.55.2.2 rmind */ 503 1.55.2.2 rmind if ((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0) 504 1.55.2.2 rmind acpicpu_md_pstate_percent_reset(sc); 505 1.55.2.2 rmind 506 1.55.2.2 rmind return acpicpu_md_pstate_sysctl_init(); 507 1.55.2.2 rmind } 508 1.55.2.2 rmind 509 1.55.2.2 rmind int 510 1.55.2.2 rmind acpicpu_md_pstate_stop(void) 511 1.55.2.2 rmind { 512 1.55.2.2 rmind 513 1.55.2.2 rmind if (acpicpu_log != NULL) 514 1.55.2.2 rmind sysctl_teardown(&acpicpu_log); 515 1.55.2.2 rmind 516 1.55.2.2 rmind return 0; 517 1.55.2.2 rmind } 518 1.55.2.2 rmind 519 1.55.2.2 rmind int 520 1.55.2.2 rmind acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 521 1.55.2.2 rmind { 522 1.55.2.2 rmind struct acpicpu_pstate *ps, msr; 523 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 524 1.55.2.2 rmind uint32_t family, i = 0; 525 1.55.2.2 rmind 526 1.55.2.2 rmind (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 527 1.55.2.2 rmind 528 1.55.2.2 rmind switch (cpu_vendor) { 529 1.55.2.2 rmind 530 1.55.2.2 rmind case CPUVENDOR_IDT: 531 1.55.2.2 rmind case CPUVENDOR_INTEL: 532 1.55.2.2 rmind 533 1.55.2.2 rmind /* 534 1.55.2.2 rmind * If the so-called Turbo Boost is present, 535 1.55.2.2 rmind * the P0-state is always the "turbo state". 536 1.55.2.2 rmind * It is shown as the P1 frequency + 1 MHz. 537 1.55.2.2 rmind * 538 1.55.2.2 rmind * For discussion, see: 539 1.55.2.2 rmind * 540 1.55.2.2 rmind * Intel Corporation: Intel Turbo Boost Technology 541 1.55.2.2 rmind * in Intel Core(tm) Microarchitectures (Nehalem) 542 1.55.2.2 rmind * Based Processors. White Paper, November 2008. 543 1.55.2.2 rmind */ 544 1.55.2.2 rmind if (sc->sc_pstate_count > 2 && 545 1.55.2.2 rmind (sc->sc_flags & ACPICPU_FLAG_P_TURBO) != 0) { 546 1.55.2.2 rmind 547 1.55.2.2 rmind ps = &sc->sc_pstate[0]; 548 1.55.2.2 rmind 549 1.55.2.2 rmind if (ps->ps_freq == sc->sc_pstate[1].ps_freq + 1) 550 1.55.2.2 rmind ps->ps_flags |= ACPICPU_FLAG_P_TURBO; 551 1.55.2.2 rmind } 552 1.55.2.2 rmind 553 1.55.2.2 rmind msr.ps_control_addr = MSR_PERF_CTL; 554 1.55.2.2 rmind msr.ps_control_mask = __BITS(0, 15); 555 1.55.2.2 rmind 556 1.55.2.2 rmind msr.ps_status_addr = MSR_PERF_STATUS; 557 1.55.2.2 rmind msr.ps_status_mask = __BITS(0, 15); 558 1.55.2.2 rmind break; 559 1.55.2.2 rmind 560 1.55.2.2 rmind case CPUVENDOR_AMD: 561 1.55.2.2 rmind 562 1.55.2.2 rmind if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 563 1.55.2.2 rmind msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; 564 1.55.2.2 rmind 565 1.55.2.2 rmind family = CPUID2FAMILY(ci->ci_signature); 566 1.55.2.2 rmind 567 1.55.2.2 rmind if (family == 0xf) 568 1.55.2.2 rmind family += CPUID2EXTFAMILY(ci->ci_signature); 569 1.55.2.2 rmind 570 1.55.2.2 rmind switch (family) { 571 1.55.2.2 rmind 572 1.55.2.2 rmind case 0x0f: 573 1.55.2.2 rmind msr.ps_control_addr = MSR_0FH_CONTROL; 574 1.55.2.2 rmind msr.ps_status_addr = MSR_0FH_STATUS; 575 1.55.2.2 rmind break; 576 1.55.2.2 rmind 577 1.55.2.2 rmind case 0x10: 578 1.55.2.2 rmind case 0x11: 579 1.55.2.2 rmind case 0x14: /* AMD Fusion */ 580 1.55.2.2 rmind msr.ps_control_addr = MSR_10H_CONTROL; 581 1.55.2.2 rmind msr.ps_control_mask = __BITS(0, 2); 582 1.55.2.2 rmind 583 1.55.2.2 rmind msr.ps_status_addr = MSR_10H_STATUS; 584 1.55.2.2 rmind msr.ps_status_mask = __BITS(0, 2); 585 1.55.2.2 rmind break; 586 1.55.2.2 rmind 587 1.55.2.2 rmind default: 588 1.55.2.2 rmind 589 1.55.2.2 rmind if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 590 1.55.2.2 rmind return EOPNOTSUPP; 591 1.55.2.2 rmind } 592 1.55.2.2 rmind 593 1.55.2.2 rmind break; 594 1.55.2.2 rmind 595 1.55.2.2 rmind default: 596 1.55.2.2 rmind return ENODEV; 597 1.55.2.2 rmind } 598 1.55.2.2 rmind 599 1.55.2.2 rmind /* 600 1.55.2.2 rmind * Fill the P-state structures with MSR addresses that are 601 1.55.2.2 rmind * known to be correct. If we do not know the addresses, 602 1.55.2.2 rmind * leave the values intact. If a vendor uses XPSS, we do 603 1.55.2.2 rmind * not necessarily need to do anything to support new CPUs. 604 1.55.2.2 rmind */ 605 1.55.2.2 rmind while (i < sc->sc_pstate_count) { 606 1.55.2.2 rmind 607 1.55.2.2 rmind ps = &sc->sc_pstate[i]; 608 1.55.2.2 rmind 609 1.55.2.2 rmind if (msr.ps_flags != 0) 610 1.55.2.2 rmind ps->ps_flags |= msr.ps_flags; 611 1.55.2.2 rmind 612 1.55.2.2 rmind if (msr.ps_status_addr != 0) 613 1.55.2.2 rmind ps->ps_status_addr = msr.ps_status_addr; 614 1.55.2.2 rmind 615 1.55.2.2 rmind if (msr.ps_status_mask != 0) 616 1.55.2.2 rmind ps->ps_status_mask = msr.ps_status_mask; 617 1.55.2.2 rmind 618 1.55.2.2 rmind if (msr.ps_control_addr != 0) 619 1.55.2.2 rmind ps->ps_control_addr = msr.ps_control_addr; 620 1.55.2.2 rmind 621 1.55.2.2 rmind if (msr.ps_control_mask != 0) 622 1.55.2.2 rmind ps->ps_control_mask = msr.ps_control_mask; 623 1.55.2.2 rmind 624 1.55.2.2 rmind i++; 625 1.55.2.2 rmind } 626 1.55.2.2 rmind 627 1.55.2.2 rmind return 0; 628 1.55.2.2 rmind } 629 1.55.2.2 rmind 630 1.55.2.2 rmind uint8_t 631 1.55.2.2 rmind acpicpu_md_pstate_percent(struct acpicpu_softc *sc) 632 1.55.2.2 rmind { 633 1.55.2.2 rmind uint64_t aperf, mperf; 634 1.55.2.2 rmind uint64_t rv = 0; 635 1.55.2.2 rmind 636 1.55.2.2 rmind /* 637 1.55.2.2 rmind * Read the IA32_APERF and IA32_MPERF counters. The first 638 1.55.2.2 rmind * increments at the rate of the fixed maximum frequency 639 1.55.2.2 rmind * configured during the boot, whereas APERF counts at the 640 1.55.2.2 rmind * rate of the actual frequency. Note that the MSRs must be 641 1.55.2.2 rmind * read without delay, and that only the ratio between 642 1.55.2.2 rmind * IA32_APERF and IA32_MPERF is architecturally defined. 643 1.55.2.2 rmind * 644 1.55.2.2 rmind * The function thus returns the percentage of the actual 645 1.55.2.2 rmind * frequency in terms of the maximum frequency of the calling 646 1.55.2.2 rmind * CPU since the last call. A value zero implies an error. 647 1.55.2.2 rmind * 648 1.55.2.2 rmind * For further details, refer to: 649 1.55.2.2 rmind * 650 1.55.2.2 rmind * Intel Corporation: Intel 64 and IA-32 Architectures 651 1.55.2.2 rmind * Software Developer's Manual. Section 13.2, Volume 3A: 652 1.55.2.2 rmind * System Programming Guide, Part 1. July, 2008. 653 1.55.2.2 rmind * 654 1.55.2.2 rmind * Advanced Micro Devices: BIOS and Kernel Developer's 655 1.55.2.2 rmind * Guide (BKDG) for AMD Family 10h Processors. Section 656 1.55.2.2 rmind * 2.4.5, Revision 3.48, April 2010. 657 1.55.2.2 rmind */ 658 1.55.2.2 rmind if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P) == 0)) 659 1.55.2.2 rmind return 0; 660 1.55.2.2 rmind 661 1.55.2.2 rmind if (__predict_false((sc->sc_flags & ACPICPU_FLAG_P_HWF) == 0)) 662 1.55.2.2 rmind return 0; 663 1.55.2.2 rmind 664 1.55.2.2 rmind aperf = sc->sc_pstate_aperf; 665 1.55.2.2 rmind mperf = sc->sc_pstate_mperf; 666 1.55.2.2 rmind 667 1.55.2.2 rmind x86_disable_intr(); 668 1.55.2.2 rmind 669 1.55.2.2 rmind sc->sc_pstate_aperf = rdmsr(MSR_APERF); 670 1.55.2.2 rmind sc->sc_pstate_mperf = rdmsr(MSR_MPERF); 671 1.55.2.2 rmind 672 1.55.2.2 rmind x86_enable_intr(); 673 1.55.2.2 rmind 674 1.55.2.2 rmind aperf = sc->sc_pstate_aperf - aperf; 675 1.55.2.2 rmind mperf = sc->sc_pstate_mperf - mperf; 676 1.55.2.2 rmind 677 1.55.2.2 rmind if (__predict_true(mperf != 0)) 678 1.55.2.2 rmind rv = (aperf * 100) / mperf; 679 1.55.2.2 rmind 680 1.55.2.2 rmind return rv; 681 1.55.2.2 rmind } 682 1.55.2.2 rmind 683 1.55.2.2 rmind static void 684 1.55.2.2 rmind acpicpu_md_pstate_percent_reset(struct acpicpu_softc *sc) 685 1.55.2.2 rmind { 686 1.55.2.2 rmind struct msr_rw_info msr; 687 1.55.2.2 rmind uint64_t xc; 688 1.55.2.2 rmind 689 1.55.2.2 rmind KASSERT((sc->sc_flags & ACPICPU_FLAG_P) != 0); 690 1.55.2.2 rmind KASSERT((sc->sc_flags & ACPICPU_FLAG_P_HWF) != 0); 691 1.55.2.2 rmind 692 1.55.2.2 rmind msr.msr_value = 0; 693 1.55.2.2 rmind msr.msr_read = false; 694 1.55.2.2 rmind msr.msr_type = MSR_APERF; 695 1.55.2.2 rmind 696 1.55.2.2 rmind xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 697 1.55.2.2 rmind xc_wait(xc); 698 1.55.2.2 rmind 699 1.55.2.2 rmind msr.msr_value = 0; 700 1.55.2.2 rmind msr.msr_read = false; 701 1.55.2.2 rmind msr.msr_type = MSR_MPERF; 702 1.55.2.2 rmind 703 1.55.2.2 rmind xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 704 1.55.2.2 rmind xc_wait(xc); 705 1.55.2.2 rmind 706 1.55.2.2 rmind sc->sc_pstate_aperf = 0; 707 1.55.2.2 rmind sc->sc_pstate_mperf = 0; 708 1.55.2.2 rmind } 709 1.55.2.2 rmind 710 1.55.2.2 rmind int 711 1.55.2.2 rmind acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 712 1.55.2.2 rmind { 713 1.55.2.2 rmind struct acpicpu_pstate *ps = NULL; 714 1.55.2.2 rmind uint64_t val; 715 1.55.2.2 rmind uint32_t i; 716 1.55.2.2 rmind 717 1.55.2.2 rmind if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 718 1.55.2.2 rmind return acpicpu_md_pstate_fidvid_get(sc, freq); 719 1.55.2.2 rmind 720 1.55.2.2 rmind /* 721 1.55.2.2 rmind * Pick any P-state for the status address. 722 1.55.2.2 rmind */ 723 1.55.2.2 rmind for (i = 0; i < sc->sc_pstate_count; i++) { 724 1.55.2.2 rmind 725 1.55.2.2 rmind ps = &sc->sc_pstate[i]; 726 1.55.2.2 rmind 727 1.55.2.2 rmind if (__predict_true(ps->ps_freq != 0)) 728 1.55.2.2 rmind break; 729 1.55.2.2 rmind } 730 1.55.2.2 rmind 731 1.55.2.2 rmind if (__predict_false(ps == NULL)) 732 1.55.2.2 rmind return ENODEV; 733 1.55.2.2 rmind 734 1.55.2.2 rmind if (__predict_false(ps->ps_status_addr == 0)) 735 1.55.2.2 rmind return EINVAL; 736 1.55.2.2 rmind 737 1.55.2.2 rmind val = rdmsr(ps->ps_status_addr); 738 1.55.2.2 rmind 739 1.55.2.2 rmind if (__predict_true(ps->ps_status_mask != 0)) 740 1.55.2.2 rmind val = val & ps->ps_status_mask; 741 1.55.2.2 rmind 742 1.55.2.2 rmind /* 743 1.55.2.2 rmind * Search for the value from known P-states. 744 1.55.2.2 rmind */ 745 1.55.2.2 rmind for (i = 0; i < sc->sc_pstate_count; i++) { 746 1.55.2.2 rmind 747 1.55.2.2 rmind ps = &sc->sc_pstate[i]; 748 1.55.2.2 rmind 749 1.55.2.2 rmind if (__predict_false(ps->ps_freq == 0)) 750 1.55.2.2 rmind continue; 751 1.55.2.2 rmind 752 1.55.2.2 rmind if (val == ps->ps_status) { 753 1.55.2.2 rmind *freq = ps->ps_freq; 754 1.55.2.2 rmind return 0; 755 1.55.2.2 rmind } 756 1.55.2.2 rmind } 757 1.55.2.2 rmind 758 1.55.2.2 rmind return EIO; 759 1.55.2.2 rmind } 760 1.55.2.2 rmind 761 1.55.2.2 rmind int 762 1.55.2.2 rmind acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 763 1.55.2.2 rmind { 764 1.55.2.2 rmind uint64_t val; 765 1.55.2.2 rmind 766 1.55.2.2 rmind if (__predict_false(ps->ps_control_addr == 0)) 767 1.55.2.2 rmind return EINVAL; 768 1.55.2.2 rmind 769 1.55.2.2 rmind if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 770 1.55.2.2 rmind return acpicpu_md_pstate_fidvid_set(ps); 771 1.55.2.2 rmind 772 1.55.2.2 rmind val = ps->ps_control; 773 1.55.2.2 rmind 774 1.55.2.2 rmind if (__predict_true(ps->ps_control_mask != 0)) 775 1.55.2.2 rmind val = val & ps->ps_control_mask; 776 1.55.2.2 rmind 777 1.55.2.2 rmind wrmsr(ps->ps_control_addr, val); 778 1.55.2.2 rmind DELAY(ps->ps_latency); 779 1.55.2.2 rmind 780 1.55.2.2 rmind return 0; 781 1.55.2.2 rmind } 782 1.55.2.2 rmind 783 1.55.2.2 rmind static int 784 1.55.2.2 rmind acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 785 1.55.2.2 rmind { 786 1.55.2.2 rmind struct acpicpu_pstate *ps; 787 1.55.2.2 rmind uint32_t fid, i, vid; 788 1.55.2.2 rmind uint32_t cfid, cvid; 789 1.55.2.2 rmind int rv; 790 1.55.2.2 rmind 791 1.55.2.2 rmind /* 792 1.55.2.2 rmind * AMD family 0Fh needs special treatment. 793 1.55.2.2 rmind * While it wants to use ACPI, it does not 794 1.55.2.2 rmind * comply with the ACPI specifications. 795 1.55.2.2 rmind */ 796 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 797 1.55.2.2 rmind 798 1.55.2.2 rmind if (rv != 0) 799 1.55.2.2 rmind return rv; 800 1.55.2.2 rmind 801 1.55.2.2 rmind for (i = 0; i < sc->sc_pstate_count; i++) { 802 1.55.2.2 rmind 803 1.55.2.2 rmind ps = &sc->sc_pstate[i]; 804 1.55.2.2 rmind 805 1.55.2.2 rmind if (__predict_false(ps->ps_freq == 0)) 806 1.55.2.2 rmind continue; 807 1.55.2.2 rmind 808 1.55.2.2 rmind fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 809 1.55.2.2 rmind vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 810 1.55.2.2 rmind 811 1.55.2.2 rmind if (cfid == fid && cvid == vid) { 812 1.55.2.2 rmind *freq = ps->ps_freq; 813 1.55.2.2 rmind return 0; 814 1.55.2.2 rmind } 815 1.55.2.2 rmind } 816 1.55.2.2 rmind 817 1.55.2.2 rmind return EIO; 818 1.55.2.2 rmind } 819 1.55.2.2 rmind 820 1.55.2.2 rmind static int 821 1.55.2.2 rmind acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 822 1.55.2.2 rmind { 823 1.55.2.2 rmind const uint64_t ctrl = ps->ps_control; 824 1.55.2.2 rmind uint32_t cfid, cvid, fid, i, irt; 825 1.55.2.2 rmind uint32_t pll, vco_cfid, vco_fid; 826 1.55.2.2 rmind uint32_t val, vid, vst; 827 1.55.2.2 rmind int rv; 828 1.55.2.2 rmind 829 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 830 1.55.2.2 rmind 831 1.55.2.2 rmind if (rv != 0) 832 1.55.2.2 rmind return rv; 833 1.55.2.2 rmind 834 1.55.2.2 rmind fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 835 1.55.2.2 rmind vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 836 1.55.2.2 rmind irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 837 1.55.2.2 rmind vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 838 1.55.2.2 rmind pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 839 1.55.2.2 rmind 840 1.55.2.2 rmind vst = vst * 20; 841 1.55.2.2 rmind pll = pll * 1000 / 5; 842 1.55.2.2 rmind irt = 10 * __BIT(irt); 843 1.55.2.2 rmind 844 1.55.2.2 rmind /* 845 1.55.2.2 rmind * Phase 1. 846 1.55.2.2 rmind */ 847 1.55.2.2 rmind while (cvid > vid) { 848 1.55.2.2 rmind 849 1.55.2.2 rmind val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 850 1.55.2.2 rmind val = (val > cvid) ? 0 : cvid - val; 851 1.55.2.2 rmind 852 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 853 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 854 1.55.2.2 rmind 855 1.55.2.2 rmind if (rv != 0) 856 1.55.2.2 rmind return rv; 857 1.55.2.2 rmind } 858 1.55.2.2 rmind 859 1.55.2.2 rmind i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 860 1.55.2.2 rmind 861 1.55.2.2 rmind for (; i > 0 && cvid > 0; --i) { 862 1.55.2.2 rmind 863 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 864 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 865 1.55.2.2 rmind 866 1.55.2.2 rmind if (rv != 0) 867 1.55.2.2 rmind return rv; 868 1.55.2.2 rmind } 869 1.55.2.2 rmind 870 1.55.2.2 rmind /* 871 1.55.2.2 rmind * Phase 2. 872 1.55.2.2 rmind */ 873 1.55.2.2 rmind if (cfid != fid) { 874 1.55.2.2 rmind 875 1.55.2.2 rmind vco_fid = FID_TO_VCO_FID(fid); 876 1.55.2.2 rmind vco_cfid = FID_TO_VCO_FID(cfid); 877 1.55.2.2 rmind 878 1.55.2.2 rmind while (abs(vco_fid - vco_cfid) > 2) { 879 1.55.2.2 rmind 880 1.55.2.2 rmind if (fid <= cfid) 881 1.55.2.2 rmind val = cfid - 2; 882 1.55.2.2 rmind else { 883 1.55.2.2 rmind val = (cfid > 6) ? cfid + 2 : 884 1.55.2.2 rmind FID_TO_VCO_FID(cfid) + 2; 885 1.55.2.2 rmind } 886 1.55.2.2 rmind 887 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 888 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 889 1.55.2.2 rmind 890 1.55.2.2 rmind if (rv != 0) 891 1.55.2.2 rmind return rv; 892 1.55.2.2 rmind 893 1.55.2.2 rmind vco_cfid = FID_TO_VCO_FID(cfid); 894 1.55.2.2 rmind } 895 1.55.2.2 rmind 896 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 897 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 898 1.55.2.2 rmind 899 1.55.2.2 rmind if (rv != 0) 900 1.55.2.2 rmind return rv; 901 1.55.2.2 rmind } 902 1.55.2.2 rmind 903 1.55.2.2 rmind /* 904 1.55.2.2 rmind * Phase 3. 905 1.55.2.2 rmind */ 906 1.55.2.2 rmind if (cvid != vid) { 907 1.55.2.2 rmind 908 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 909 1.55.2.2 rmind rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 910 1.55.2.2 rmind 911 1.55.2.2 rmind if (rv != 0) 912 1.55.2.2 rmind return rv; 913 1.55.2.2 rmind } 914 1.55.2.2 rmind 915 1.55.2.2 rmind if (cfid != fid || cvid != vid) 916 1.55.2.2 rmind return EIO; 917 1.55.2.2 rmind 918 1.55.2.2 rmind return 0; 919 1.55.2.2 rmind } 920 1.55.2.2 rmind 921 1.55.2.2 rmind static int 922 1.55.2.2 rmind acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 923 1.55.2.2 rmind { 924 1.55.2.2 rmind int i = ACPICPU_P_STATE_RETRY * 100; 925 1.55.2.2 rmind uint64_t val; 926 1.55.2.2 rmind 927 1.55.2.2 rmind do { 928 1.55.2.2 rmind val = rdmsr(MSR_0FH_STATUS); 929 1.55.2.2 rmind 930 1.55.2.2 rmind } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 931 1.55.2.2 rmind 932 1.55.2.2 rmind if (i == 0) 933 1.55.2.2 rmind return EAGAIN; 934 1.55.2.2 rmind 935 1.55.2.2 rmind if (cfid != NULL) 936 1.55.2.2 rmind *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 937 1.55.2.2 rmind 938 1.55.2.2 rmind if (cvid != NULL) 939 1.55.2.2 rmind *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 940 1.55.2.2 rmind 941 1.55.2.2 rmind return 0; 942 1.55.2.2 rmind } 943 1.55.2.2 rmind 944 1.55.2.2 rmind static void 945 1.55.2.2 rmind acpicpu_md_pstate_fidvid_write(uint32_t fid, 946 1.55.2.2 rmind uint32_t vid, uint32_t cnt, uint32_t tmo) 947 1.55.2.2 rmind { 948 1.55.2.2 rmind uint64_t val = 0; 949 1.55.2.2 rmind 950 1.55.2.2 rmind val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 951 1.55.2.2 rmind val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 952 1.55.2.2 rmind val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 953 1.55.2.2 rmind val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 954 1.55.2.2 rmind 955 1.55.2.2 rmind wrmsr(MSR_0FH_CONTROL, val); 956 1.55.2.2 rmind DELAY(tmo); 957 1.55.2.2 rmind } 958 1.55.2.2 rmind 959 1.55.2.2 rmind int 960 1.55.2.2 rmind acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 961 1.55.2.2 rmind { 962 1.55.2.2 rmind struct acpicpu_tstate *ts; 963 1.55.2.2 rmind uint64_t val; 964 1.55.2.2 rmind uint32_t i; 965 1.55.2.2 rmind 966 1.55.2.2 rmind val = rdmsr(MSR_THERM_CONTROL); 967 1.55.2.2 rmind 968 1.55.2.2 rmind for (i = 0; i < sc->sc_tstate_count; i++) { 969 1.55.2.2 rmind 970 1.55.2.2 rmind ts = &sc->sc_tstate[i]; 971 1.55.2.2 rmind 972 1.55.2.2 rmind if (ts->ts_percent == 0) 973 1.55.2.2 rmind continue; 974 1.55.2.2 rmind 975 1.55.2.2 rmind if (val == ts->ts_status) { 976 1.55.2.2 rmind *percent = ts->ts_percent; 977 1.55.2.2 rmind return 0; 978 1.55.2.2 rmind } 979 1.55.2.2 rmind } 980 1.55.2.2 rmind 981 1.55.2.2 rmind return EIO; 982 1.55.2.2 rmind } 983 1.55.2.2 rmind 984 1.55.2.2 rmind int 985 1.55.2.2 rmind acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 986 1.55.2.2 rmind { 987 1.55.2.2 rmind uint64_t val; 988 1.55.2.2 rmind uint8_t i; 989 1.55.2.2 rmind 990 1.55.2.2 rmind val = ts->ts_control; 991 1.55.2.2 rmind val = val & __BITS(1, 4); 992 1.55.2.2 rmind 993 1.55.2.2 rmind wrmsr(MSR_THERM_CONTROL, val); 994 1.55.2.2 rmind 995 1.55.2.2 rmind if (ts->ts_status == 0) { 996 1.55.2.2 rmind DELAY(ts->ts_latency); 997 1.55.2.2 rmind return 0; 998 1.55.2.2 rmind } 999 1.55.2.2 rmind 1000 1.55.2.2 rmind for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 1001 1.55.2.2 rmind 1002 1.55.2.2 rmind val = rdmsr(MSR_THERM_CONTROL); 1003 1.55.2.2 rmind 1004 1.55.2.2 rmind if (val == ts->ts_status) 1005 1.55.2.2 rmind return 0; 1006 1.55.2.2 rmind 1007 1.55.2.2 rmind DELAY(ts->ts_latency); 1008 1.55.2.2 rmind } 1009 1.55.2.2 rmind 1010 1.55.2.2 rmind return EAGAIN; 1011 1.55.2.2 rmind } 1012 1.55.2.2 rmind 1013 1.55.2.2 rmind /* 1014 1.55.2.2 rmind * A kludge for backwards compatibility. 1015 1.55.2.2 rmind */ 1016 1.55.2.2 rmind static int 1017 1.55.2.2 rmind acpicpu_md_pstate_sysctl_init(void) 1018 1.55.2.2 rmind { 1019 1.55.2.2 rmind const struct sysctlnode *fnode, *mnode, *rnode; 1020 1.55.2.2 rmind const char *str; 1021 1.55.2.2 rmind int rv; 1022 1.55.2.2 rmind 1023 1.55.2.2 rmind switch (cpu_vendor) { 1024 1.55.2.2 rmind 1025 1.55.2.2 rmind case CPUVENDOR_IDT: 1026 1.55.2.2 rmind case CPUVENDOR_INTEL: 1027 1.55.2.2 rmind str = "est"; 1028 1.55.2.2 rmind break; 1029 1.55.2.2 rmind 1030 1.55.2.2 rmind case CPUVENDOR_AMD: 1031 1.55.2.2 rmind str = "powernow"; 1032 1.55.2.2 rmind break; 1033 1.55.2.2 rmind 1034 1.55.2.2 rmind default: 1035 1.55.2.2 rmind return ENODEV; 1036 1.55.2.2 rmind } 1037 1.55.2.2 rmind 1038 1.55.2.2 rmind 1039 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 1040 1.55.2.2 rmind CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 1041 1.55.2.2 rmind NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 1042 1.55.2.2 rmind 1043 1.55.2.2 rmind if (rv != 0) 1044 1.55.2.2 rmind goto fail; 1045 1.55.2.2 rmind 1046 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 1047 1.55.2.2 rmind 0, CTLTYPE_NODE, str, NULL, 1048 1.55.2.2 rmind NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1049 1.55.2.2 rmind 1050 1.55.2.2 rmind if (rv != 0) 1051 1.55.2.2 rmind goto fail; 1052 1.55.2.2 rmind 1053 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 1054 1.55.2.2 rmind 0, CTLTYPE_NODE, "frequency", NULL, 1055 1.55.2.2 rmind NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1056 1.55.2.2 rmind 1057 1.55.2.2 rmind if (rv != 0) 1058 1.55.2.2 rmind goto fail; 1059 1.55.2.2 rmind 1060 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1061 1.55.2.2 rmind CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 1062 1.55.2.2 rmind acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1063 1.55.2.2 rmind 1064 1.55.2.2 rmind if (rv != 0) 1065 1.55.2.2 rmind goto fail; 1066 1.55.2.2 rmind 1067 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1068 1.55.2.2 rmind CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 1069 1.55.2.2 rmind acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1070 1.55.2.2 rmind 1071 1.55.2.2 rmind if (rv != 0) 1072 1.55.2.2 rmind goto fail; 1073 1.55.2.2 rmind 1074 1.55.2.2 rmind rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 1075 1.55.2.2 rmind CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 1076 1.55.2.2 rmind acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 1077 1.55.2.2 rmind 1078 1.55.2.2 rmind if (rv != 0) 1079 1.55.2.2 rmind goto fail; 1080 1.55.2.2 rmind 1081 1.55.2.2 rmind return 0; 1082 1.55.2.2 rmind 1083 1.55.2.2 rmind fail: 1084 1.55.2.2 rmind if (acpicpu_log != NULL) { 1085 1.55.2.2 rmind sysctl_teardown(&acpicpu_log); 1086 1.55.2.2 rmind acpicpu_log = NULL; 1087 1.55.2.2 rmind } 1088 1.55.2.2 rmind 1089 1.55.2.2 rmind return rv; 1090 1.55.2.2 rmind } 1091 1.55.2.2 rmind 1092 1.55.2.2 rmind static int 1093 1.55.2.2 rmind acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 1094 1.55.2.2 rmind { 1095 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 1096 1.55.2.2 rmind struct sysctlnode node; 1097 1.55.2.2 rmind uint32_t freq; 1098 1.55.2.2 rmind int err; 1099 1.55.2.2 rmind 1100 1.55.2.2 rmind err = acpicpu_pstate_get(ci, &freq); 1101 1.55.2.2 rmind 1102 1.55.2.2 rmind if (err != 0) 1103 1.55.2.2 rmind return err; 1104 1.55.2.2 rmind 1105 1.55.2.2 rmind node = *rnode; 1106 1.55.2.2 rmind node.sysctl_data = &freq; 1107 1.55.2.2 rmind 1108 1.55.2.2 rmind err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1109 1.55.2.2 rmind 1110 1.55.2.2 rmind if (err != 0 || newp == NULL) 1111 1.55.2.2 rmind return err; 1112 1.55.2.2 rmind 1113 1.55.2.2 rmind return 0; 1114 1.55.2.2 rmind } 1115 1.55.2.2 rmind 1116 1.55.2.2 rmind static int 1117 1.55.2.2 rmind acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 1118 1.55.2.2 rmind { 1119 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 1120 1.55.2.2 rmind struct sysctlnode node; 1121 1.55.2.2 rmind uint32_t freq; 1122 1.55.2.2 rmind int err; 1123 1.55.2.2 rmind 1124 1.55.2.2 rmind err = acpicpu_pstate_get(ci, &freq); 1125 1.55.2.2 rmind 1126 1.55.2.2 rmind if (err != 0) 1127 1.55.2.2 rmind return err; 1128 1.55.2.2 rmind 1129 1.55.2.2 rmind node = *rnode; 1130 1.55.2.2 rmind node.sysctl_data = &freq; 1131 1.55.2.2 rmind 1132 1.55.2.2 rmind err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1133 1.55.2.2 rmind 1134 1.55.2.2 rmind if (err != 0 || newp == NULL) 1135 1.55.2.2 rmind return err; 1136 1.55.2.2 rmind 1137 1.55.2.2 rmind acpicpu_pstate_set(ci, freq); 1138 1.55.2.2 rmind 1139 1.55.2.2 rmind return 0; 1140 1.55.2.2 rmind } 1141 1.55.2.2 rmind 1142 1.55.2.2 rmind static int 1143 1.55.2.2 rmind acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1144 1.55.2.2 rmind { 1145 1.55.2.2 rmind struct cpu_info *ci = curcpu(); 1146 1.55.2.2 rmind struct acpicpu_softc *sc; 1147 1.55.2.2 rmind struct sysctlnode node; 1148 1.55.2.2 rmind char buf[1024]; 1149 1.55.2.2 rmind size_t len; 1150 1.55.2.2 rmind uint32_t i; 1151 1.55.2.2 rmind int err; 1152 1.55.2.2 rmind 1153 1.55.2.2 rmind sc = acpicpu_sc[ci->ci_acpiid]; 1154 1.55.2.2 rmind 1155 1.55.2.2 rmind if (sc == NULL) 1156 1.55.2.2 rmind return ENXIO; 1157 1.55.2.2 rmind 1158 1.55.2.2 rmind (void)memset(&buf, 0, sizeof(buf)); 1159 1.55.2.2 rmind 1160 1.55.2.2 rmind mutex_enter(&sc->sc_mtx); 1161 1.55.2.2 rmind 1162 1.55.2.2 rmind for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1163 1.55.2.2 rmind 1164 1.55.2.2 rmind if (sc->sc_pstate[i].ps_freq == 0) 1165 1.55.2.2 rmind continue; 1166 1.55.2.2 rmind 1167 1.55.2.2 rmind len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1168 1.55.2.2 rmind sc->sc_pstate[i].ps_freq, 1169 1.55.2.2 rmind i < (sc->sc_pstate_count - 1) ? " " : ""); 1170 1.55.2.2 rmind } 1171 1.55.2.2 rmind 1172 1.55.2.2 rmind mutex_exit(&sc->sc_mtx); 1173 1.55.2.2 rmind 1174 1.55.2.2 rmind node = *rnode; 1175 1.55.2.2 rmind node.sysctl_data = buf; 1176 1.55.2.2 rmind 1177 1.55.2.2 rmind err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1178 1.55.2.2 rmind 1179 1.55.2.2 rmind if (err != 0 || newp == NULL) 1180 1.55.2.2 rmind return err; 1181 1.55.2.2 rmind 1182 1.55.2.2 rmind return 0; 1183 1.55.2.2 rmind } 1184 1.55.2.2 rmind 1185
Indexes created Tue Sep 30 20:09:53 GMT 2025