acpi_cpu_md.c revision 1.12
1 /* $NetBSD: acpi_cpu_md.c,v 1.12 2010/08/14 05:13:20 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.12 2010/08/14 05:13:20 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 static char native_idle_text[16]; 52 void (*native_idle)(void) = NULL; 53 void (*native_cpu_freq_init)(int) = NULL; 54 55 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 56 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 57 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 58 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 59 static int acpicpu_md_tstate_get_status(uint64_t *); 60 61 extern uint32_t cpus_running; 62 extern struct acpicpu_softc **acpicpu_sc; 63 64 uint32_t 65 acpicpu_md_cap(void) 66 { 67 struct cpu_info *ci = curcpu(); 68 uint32_t val = 0; 69 70 if (cpu_vendor != CPUVENDOR_INTEL) 71 return val; 72 73 /* 74 * Basic SMP C-states (required for _CST). 75 */ 76 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 77 78 /* 79 * If MONITOR/MWAIT is available, announce 80 * support for native instructions in all C-states. 81 */ 82 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 83 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 84 85 /* 86 * Set native P- and T-states, if available. 87 */ 88 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 89 val |= ACPICPU_PDC_P_FFH; 90 91 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 92 val |= ACPICPU_PDC_T_FFH; 93 94 return val; 95 } 96 97 uint32_t 98 acpicpu_md_quirks(void) 99 { 100 struct cpu_info *ci = curcpu(); 101 struct pci_attach_args pa; 102 uint32_t val = 0; 103 104 if (acpicpu_md_cpus_running() == 1) 105 val |= ACPICPU_FLAG_C_BM; 106 107 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 108 val |= ACPICPU_FLAG_C_FFH; 109 110 switch (cpu_vendor) { 111 112 case CPUVENDOR_INTEL: 113 114 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 115 val |= ACPICPU_FLAG_P_FFH; 116 117 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 118 val |= ACPICPU_FLAG_T_FFH; 119 120 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 121 122 /* 123 * Bus master arbitration is not 124 * needed on some recent Intel CPUs. 125 */ 126 if (CPUID2FAMILY(ci->ci_signature) > 15) 127 val &= ~ACPICPU_FLAG_C_ARB; 128 129 if (CPUID2FAMILY(ci->ci_signature) == 6 && 130 CPUID2MODEL(ci->ci_signature) >= 15) 131 val &= ~ACPICPU_FLAG_C_ARB; 132 133 break; 134 135 case CPUVENDOR_AMD: 136 137 /* 138 * XXX: Deal with PowerNow! and C1E here. 139 */ 140 break; 141 } 142 143 /* 144 * There are several erratums for PIIX4. 145 */ 146 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 147 val |= ACPICPU_FLAG_PIIX4; 148 149 return val; 150 } 151 152 static int 153 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 154 { 155 156 /* 157 * XXX: The pci_find_device(9) function only 158 * deals with attached devices. Change this 159 * to use something like pci_device_foreach(). 160 */ 161 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 162 return 0; 163 164 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 165 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 166 return 1; 167 168 return 0; 169 } 170 171 uint32_t 172 acpicpu_md_cpus_running(void) 173 { 174 175 return popcount32(cpus_running); 176 } 177 178 int 179 acpicpu_md_idle_start(void) 180 { 181 const size_t size = sizeof(native_idle_text); 182 183 x86_disable_intr(); 184 x86_cpu_idle_get(&native_idle, native_idle_text, size); 185 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi"); 186 x86_enable_intr(); 187 188 return 0; 189 } 190 191 int 192 acpicpu_md_idle_stop(void) 193 { 194 uint64_t xc; 195 196 x86_disable_intr(); 197 x86_cpu_idle_set(native_idle, native_idle_text); 198 x86_enable_intr(); 199 200 /* 201 * Run a cross-call to ensure that all CPUs are 202 * out from the ACPI idle-loop before detachment. 203 */ 204 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 205 xc_wait(xc); 206 207 return 0; 208 } 209 210 /* 211 * The MD idle loop. Called with interrupts disabled. 212 */ 213 void 214 acpicpu_md_idle_enter(int method, int state) 215 { 216 struct cpu_info *ci = curcpu(); 217 218 switch (method) { 219 220 case ACPICPU_C_STATE_FFH: 221 222 x86_enable_intr(); 223 x86_monitor(&ci->ci_want_resched, 0, 0); 224 225 if (__predict_false(ci->ci_want_resched) != 0) 226 return; 227 228 x86_mwait((state - 1) << 4, 0); 229 break; 230 231 case ACPICPU_C_STATE_HALT: 232 233 if (__predict_false(ci->ci_want_resched) != 0) { 234 x86_enable_intr(); 235 return; 236 } 237 238 x86_stihlt(); 239 break; 240 } 241 } 242 243 int 244 acpicpu_md_pstate_start(void) 245 { 246 const struct sysctlnode *fnode, *mnode, *rnode; 247 const char *str; 248 int rv; 249 250 switch (cpu_vendor) { 251 252 case CPUVENDOR_INTEL: 253 str = "est"; 254 break; 255 256 default: 257 return ENODEV; 258 } 259 260 /* 261 * A kludge for backwards compatibility. 262 */ 263 native_cpu_freq_init = cpu_freq_init; 264 265 if (cpu_freq_sysctllog != NULL) { 266 sysctl_teardown(&cpu_freq_sysctllog); 267 cpu_freq_sysctllog = NULL; 268 } 269 270 rv = sysctl_createv(&cpu_freq_sysctllog, 0, NULL, &rnode, 271 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 272 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 273 274 if (rv != 0) 275 goto fail; 276 277 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &rnode, &mnode, 278 0, CTLTYPE_NODE, str, NULL, 279 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 280 281 if (rv != 0) 282 goto fail; 283 284 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &mnode, &fnode, 285 0, CTLTYPE_NODE, "frequency", NULL, 286 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 287 288 if (rv != 0) 289 goto fail; 290 291 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 292 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 293 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 294 295 if (rv != 0) 296 goto fail; 297 298 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 299 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 300 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 301 302 if (rv != 0) 303 goto fail; 304 305 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 306 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 307 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 308 309 if (rv != 0) 310 goto fail; 311 312 return 0; 313 314 fail: 315 if (cpu_freq_sysctllog != NULL) { 316 sysctl_teardown(&cpu_freq_sysctllog); 317 cpu_freq_sysctllog = NULL; 318 } 319 320 if (native_cpu_freq_init != NULL) 321 (*native_cpu_freq_init)(cpu_vendor); 322 323 return rv; 324 } 325 326 int 327 acpicpu_md_pstate_stop(void) 328 { 329 330 if (cpu_freq_sysctllog != NULL) { 331 sysctl_teardown(&cpu_freq_sysctllog); 332 cpu_freq_sysctllog = NULL; 333 } 334 335 if (native_cpu_freq_init != NULL) 336 (*native_cpu_freq_init)(cpu_vendor); 337 338 return 0; 339 } 340 341 static int 342 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 343 { 344 struct cpu_info *ci = curcpu(); 345 struct acpicpu_softc *sc; 346 struct sysctlnode node; 347 uint32_t freq; 348 int err; 349 350 sc = acpicpu_sc[ci->ci_acpiid]; 351 352 if (sc == NULL) 353 return ENXIO; 354 355 err = acpicpu_pstate_get(sc, &freq); 356 357 if (err != 0) 358 return err; 359 360 node = *rnode; 361 node.sysctl_data = &freq; 362 363 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 364 365 if (err != 0 || newp == NULL) 366 return err; 367 368 return 0; 369 } 370 371 static int 372 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 373 { 374 struct cpu_info *ci = curcpu(); 375 struct acpicpu_softc *sc; 376 struct sysctlnode node; 377 uint32_t freq; 378 int err; 379 380 sc = acpicpu_sc[ci->ci_acpiid]; 381 382 if (sc == NULL) 383 return ENXIO; 384 385 err = acpicpu_pstate_get(sc, &freq); 386 387 if (err != 0) 388 return err; 389 390 node = *rnode; 391 node.sysctl_data = &freq; 392 393 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 394 395 if (err != 0 || newp == NULL) 396 return err; 397 398 err = acpicpu_pstate_set(sc, freq); 399 400 if (err != 0) 401 return err; 402 403 return 0; 404 } 405 406 static int 407 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 408 { 409 struct cpu_info *ci = curcpu(); 410 struct acpicpu_softc *sc; 411 struct sysctlnode node; 412 char buf[1024]; 413 size_t len; 414 uint32_t i; 415 int err; 416 417 sc = acpicpu_sc[ci->ci_acpiid]; 418 419 if (sc == NULL) 420 return ENXIO; 421 422 (void)memset(&buf, 0, sizeof(buf)); 423 424 mutex_enter(&sc->sc_mtx); 425 426 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 427 428 if (sc->sc_pstate[i].ps_freq == 0) 429 continue; 430 431 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 432 sc->sc_pstate[i].ps_freq, 433 i < (sc->sc_pstate_count - 1) ? " " : ""); 434 } 435 436 mutex_exit(&sc->sc_mtx); 437 438 node = *rnode; 439 node.sysctl_data = buf; 440 441 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 442 443 if (err != 0 || newp == NULL) 444 return err; 445 446 return 0; 447 } 448 449 int 450 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 451 { 452 struct acpicpu_pstate *ps; 453 uint64_t val; 454 uint32_t i; 455 456 switch (cpu_vendor) { 457 458 case CPUVENDOR_INTEL: 459 460 val = rdmsr(MSR_PERF_STATUS); 461 val = val & 0xffff; 462 463 for (i = 0; i < sc->sc_pstate_count; i++) { 464 465 ps = &sc->sc_pstate[i]; 466 467 if (ps->ps_freq == 0) 468 continue; 469 470 if (val == ps->ps_status) { 471 *freq = ps->ps_freq; 472 return 0; 473 } 474 } 475 476 return EIO; 477 478 default: 479 return ENODEV; 480 } 481 482 return 0; 483 } 484 485 int 486 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 487 { 488 struct msr_rw_info msr; 489 uint64_t xc, val; 490 int i; 491 492 switch (cpu_vendor) { 493 494 case CPUVENDOR_INTEL: 495 msr.msr_read = true; 496 msr.msr_type = MSR_PERF_CTL; 497 msr.msr_value = ps->ps_control; 498 msr.msr_mask = 0xffffULL; 499 break; 500 501 default: 502 return ENODEV; 503 } 504 505 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 506 xc_wait(xc); 507 508 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 509 510 val = rdmsr(MSR_PERF_STATUS); 511 val = val & 0xffff; 512 513 if (val == ps->ps_status) 514 return 0; 515 516 DELAY(ps->ps_latency); 517 } 518 519 return EAGAIN; 520 } 521 522 int 523 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 524 { 525 struct acpicpu_tstate *ts; 526 uint64_t val; 527 uint32_t i; 528 int rv; 529 530 rv = acpicpu_md_tstate_get_status(&val); 531 532 if (rv != 0) 533 return rv; 534 535 for (i = 0; i < sc->sc_tstate_count; i++) { 536 537 ts = &sc->sc_tstate[i]; 538 539 if (ts->ts_percent == 0) 540 continue; 541 542 if (val == ts->ts_control || val == ts->ts_status) { 543 *percent = ts->ts_percent; 544 return 0; 545 } 546 } 547 548 return EIO; 549 } 550 551 static int 552 acpicpu_md_tstate_get_status(uint64_t *val) 553 { 554 555 switch (cpu_vendor) { 556 557 case CPUVENDOR_INTEL: 558 *val = rdmsr(MSR_THERM_CONTROL); 559 break; 560 561 default: 562 return ENODEV; 563 } 564 565 return 0; 566 } 567 568 int 569 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 570 { 571 struct msr_rw_info msr; 572 uint64_t xc, val; 573 int i; 574 575 switch (cpu_vendor) { 576 577 case CPUVENDOR_INTEL: 578 msr.msr_read = true; 579 msr.msr_type = MSR_THERM_CONTROL; 580 msr.msr_value = ts->ts_control; 581 msr.msr_mask = __BITS(1, 4); 582 break; 583 584 default: 585 return ENODEV; 586 } 587 588 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 589 xc_wait(xc); 590 591 if (ts->ts_status == 0) 592 return 0; 593 594 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 595 596 (void)acpicpu_md_tstate_get_status(&val); 597 598 if (val == ts->ts_status) 599 return 0; 600 601 DELAY(ts->ts_latency); 602 } 603 604 return EAGAIN; 605 } 606
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