acpi_cpu_md.c revision 1.15
1 /* $NetBSD: acpi_cpu_md.c,v 1.15 2010/08/18 18:32:20 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.15 2010/08/18 18:32:20 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 static char native_idle_text[16]; 52 void (*native_idle)(void) = NULL; 53 void (*native_cpu_freq_init)(int) = NULL; 54 55 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 56 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 57 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 58 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 59 static void acpicpu_md_pstate_status(void *, void *); 60 static void acpicpu_md_tstate_status(void *, void *); 61 62 extern uint32_t cpus_running; 63 extern struct acpicpu_softc **acpicpu_sc; 64 65 uint32_t 66 acpicpu_md_cap(void) 67 { 68 struct cpu_info *ci = curcpu(); 69 uint32_t val = 0; 70 71 if (cpu_vendor != CPUVENDOR_INTEL) 72 return val; 73 74 /* 75 * Basic SMP C-states (required for _CST). 76 */ 77 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 78 79 /* 80 * If MONITOR/MWAIT is available, announce 81 * support for native instructions in all C-states. 82 */ 83 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 84 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 85 86 /* 87 * Set native P- and T-states, if available. 88 */ 89 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 90 val |= ACPICPU_PDC_P_FFH; 91 92 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 93 val |= ACPICPU_PDC_T_FFH; 94 95 return val; 96 } 97 98 uint32_t 99 acpicpu_md_quirks(void) 100 { 101 struct cpu_info *ci = curcpu(); 102 struct pci_attach_args pa; 103 uint32_t val = 0; 104 105 if (acpicpu_md_cpus_running() == 1) 106 val |= ACPICPU_FLAG_C_BM; 107 108 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 109 val |= ACPICPU_FLAG_C_FFH; 110 111 switch (cpu_vendor) { 112 113 case CPUVENDOR_INTEL: 114 115 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 116 val |= ACPICPU_FLAG_P_FFH; 117 118 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 119 val |= ACPICPU_FLAG_T_FFH; 120 121 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 122 123 /* 124 * Bus master arbitration is not 125 * needed on some recent Intel CPUs. 126 */ 127 if (CPUID2FAMILY(ci->ci_signature) > 15) 128 val &= ~ACPICPU_FLAG_C_ARB; 129 130 if (CPUID2FAMILY(ci->ci_signature) == 6 && 131 CPUID2MODEL(ci->ci_signature) >= 15) 132 val &= ~ACPICPU_FLAG_C_ARB; 133 134 break; 135 136 case CPUVENDOR_AMD: 137 138 /* 139 * XXX: Deal with (non-XPSS) PowerNow! and C1E. 140 */ 141 break; 142 } 143 144 /* 145 * There are several erratums for PIIX4. 146 */ 147 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 148 val |= ACPICPU_FLAG_PIIX4; 149 150 return val; 151 } 152 153 static int 154 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 155 { 156 157 /* 158 * XXX: The pci_find_device(9) function only 159 * deals with attached devices. Change this 160 * to use something like pci_device_foreach(). 161 */ 162 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 163 return 0; 164 165 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 167 return 1; 168 169 return 0; 170 } 171 172 uint32_t 173 acpicpu_md_cpus_running(void) 174 { 175 176 return popcount32(cpus_running); 177 } 178 179 int 180 acpicpu_md_idle_start(void) 181 { 182 const size_t size = sizeof(native_idle_text); 183 184 x86_disable_intr(); 185 x86_cpu_idle_get(&native_idle, native_idle_text, size); 186 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi"); 187 x86_enable_intr(); 188 189 return 0; 190 } 191 192 int 193 acpicpu_md_idle_stop(void) 194 { 195 uint64_t xc; 196 197 x86_disable_intr(); 198 x86_cpu_idle_set(native_idle, native_idle_text); 199 x86_enable_intr(); 200 201 /* 202 * Run a cross-call to ensure that all CPUs are 203 * out from the ACPI idle-loop before detachment. 204 */ 205 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 206 xc_wait(xc); 207 208 return 0; 209 } 210 211 /* 212 * The MD idle loop. Called with interrupts disabled. 213 */ 214 void 215 acpicpu_md_idle_enter(int method, int state) 216 { 217 struct cpu_info *ci = curcpu(); 218 219 switch (method) { 220 221 case ACPICPU_C_STATE_FFH: 222 223 x86_enable_intr(); 224 x86_monitor(&ci->ci_want_resched, 0, 0); 225 226 if (__predict_false(ci->ci_want_resched) != 0) 227 return; 228 229 x86_mwait((state - 1) << 4, 0); 230 break; 231 232 case ACPICPU_C_STATE_HALT: 233 234 if (__predict_false(ci->ci_want_resched) != 0) { 235 x86_enable_intr(); 236 return; 237 } 238 239 x86_stihlt(); 240 break; 241 } 242 } 243 244 int 245 acpicpu_md_pstate_start(void) 246 { 247 const struct sysctlnode *fnode, *mnode, *rnode; 248 const char *str; 249 int rv; 250 251 switch (cpu_vendor) { 252 253 case CPUVENDOR_INTEL: 254 str = "est"; 255 break; 256 257 case CPUVENDOR_AMD: 258 str = "powernow"; 259 break; 260 261 default: 262 return ENODEV; 263 } 264 265 /* 266 * A kludge for backwards compatibility. 267 */ 268 native_cpu_freq_init = cpu_freq_init; 269 270 if (cpu_freq_sysctllog != NULL) { 271 sysctl_teardown(&cpu_freq_sysctllog); 272 cpu_freq_sysctllog = NULL; 273 } 274 275 rv = sysctl_createv(&cpu_freq_sysctllog, 0, NULL, &rnode, 276 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 277 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 278 279 if (rv != 0) 280 goto fail; 281 282 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &rnode, &mnode, 283 0, CTLTYPE_NODE, str, NULL, 284 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 285 286 if (rv != 0) 287 goto fail; 288 289 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &mnode, &fnode, 290 0, CTLTYPE_NODE, "frequency", NULL, 291 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 292 293 if (rv != 0) 294 goto fail; 295 296 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 297 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 298 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 299 300 if (rv != 0) 301 goto fail; 302 303 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 304 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 305 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 306 307 if (rv != 0) 308 goto fail; 309 310 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 311 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 312 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 313 314 if (rv != 0) 315 goto fail; 316 317 return 0; 318 319 fail: 320 if (cpu_freq_sysctllog != NULL) { 321 sysctl_teardown(&cpu_freq_sysctllog); 322 cpu_freq_sysctllog = NULL; 323 } 324 325 if (native_cpu_freq_init != NULL) 326 (*native_cpu_freq_init)(cpu_vendor); 327 328 return rv; 329 } 330 331 int 332 acpicpu_md_pstate_stop(void) 333 { 334 335 if (cpu_freq_sysctllog != NULL) { 336 sysctl_teardown(&cpu_freq_sysctllog); 337 cpu_freq_sysctllog = NULL; 338 } 339 340 if (native_cpu_freq_init != NULL) 341 (*native_cpu_freq_init)(cpu_vendor); 342 343 return 0; 344 } 345 346 static int 347 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 348 { 349 struct cpu_info *ci = curcpu(); 350 struct acpicpu_softc *sc; 351 struct sysctlnode node; 352 uint32_t freq; 353 int err; 354 355 sc = acpicpu_sc[ci->ci_acpiid]; 356 357 if (sc == NULL) 358 return ENXIO; 359 360 err = acpicpu_pstate_get(sc, &freq); 361 362 if (err != 0) 363 return err; 364 365 node = *rnode; 366 node.sysctl_data = &freq; 367 368 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 369 370 if (err != 0 || newp == NULL) 371 return err; 372 373 return 0; 374 } 375 376 static int 377 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 378 { 379 struct cpu_info *ci = curcpu(); 380 struct acpicpu_softc *sc; 381 struct sysctlnode node; 382 uint32_t freq; 383 int err; 384 385 sc = acpicpu_sc[ci->ci_acpiid]; 386 387 if (sc == NULL) 388 return ENXIO; 389 390 err = acpicpu_pstate_get(sc, &freq); 391 392 if (err != 0) 393 return err; 394 395 node = *rnode; 396 node.sysctl_data = &freq; 397 398 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 399 400 if (err != 0 || newp == NULL) 401 return err; 402 403 err = acpicpu_pstate_set(sc, freq); 404 405 if (err != 0) 406 return err; 407 408 return 0; 409 } 410 411 static int 412 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 413 { 414 struct cpu_info *ci = curcpu(); 415 struct acpicpu_softc *sc; 416 struct sysctlnode node; 417 char buf[1024]; 418 size_t len; 419 uint32_t i; 420 int err; 421 422 sc = acpicpu_sc[ci->ci_acpiid]; 423 424 if (sc == NULL) 425 return ENXIO; 426 427 (void)memset(&buf, 0, sizeof(buf)); 428 429 mutex_enter(&sc->sc_mtx); 430 431 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 432 433 if (sc->sc_pstate[i].ps_freq == 0) 434 continue; 435 436 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 437 sc->sc_pstate[i].ps_freq, 438 i < (sc->sc_pstate_count - 1) ? " " : ""); 439 } 440 441 mutex_exit(&sc->sc_mtx); 442 443 node = *rnode; 444 node.sysctl_data = buf; 445 446 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 447 448 if (err != 0 || newp == NULL) 449 return err; 450 451 return 0; 452 } 453 454 int 455 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 456 { 457 struct acpicpu_pstate *ps, msr; 458 uint32_t i = 0; 459 460 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 461 462 switch (cpu_vendor) { 463 464 case CPUVENDOR_INTEL: 465 msr.ps_control_addr = MSR_PERF_CTL; 466 msr.ps_control_mask = __BITS(0, 15); 467 468 msr.ps_status_addr = MSR_PERF_STATUS; 469 msr.ps_status_mask = __BITS(0, 15); 470 break; 471 472 case CPUVENDOR_AMD: 473 474 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 475 return EOPNOTSUPP; 476 477 break; 478 479 default: 480 return ENODEV; 481 } 482 483 while (i < sc->sc_pstate_count) { 484 485 ps = &sc->sc_pstate[i]; 486 487 if (ps->ps_status_addr == 0) 488 ps->ps_status_addr = msr.ps_status_addr; 489 490 if (ps->ps_status_mask == 0) 491 ps->ps_status_mask = msr.ps_status_mask; 492 493 if (ps->ps_control_addr == 0) 494 ps->ps_control_addr = msr.ps_control_addr; 495 496 if (ps->ps_control_mask == 0) 497 ps->ps_control_mask = msr.ps_control_mask; 498 499 i++; 500 } 501 502 return 0; 503 } 504 505 int 506 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 507 { 508 struct acpicpu_pstate *ps = NULL; 509 uint64_t val; 510 uint32_t i; 511 512 for (i = 0; i < sc->sc_pstate_count; i++) { 513 514 ps = &sc->sc_pstate[i]; 515 516 if (ps->ps_freq != 0) 517 break; 518 } 519 520 if (__predict_false(ps == NULL)) 521 return EINVAL; 522 523 if (ps->ps_status_addr == 0) 524 return EINVAL; 525 526 val = rdmsr(ps->ps_status_addr); 527 528 if (ps->ps_status_mask != 0) 529 val = val & ps->ps_status_mask; 530 531 for (i = 0; i < sc->sc_pstate_count; i++) { 532 533 ps = &sc->sc_pstate[i]; 534 535 if (ps->ps_freq == 0) 536 continue; 537 538 if (val == ps->ps_status) { 539 *freq = ps->ps_freq; 540 return 0; 541 } 542 } 543 544 return EIO; 545 } 546 547 int 548 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 549 { 550 struct msr_rw_info msr; 551 uint64_t xc; 552 int rv = 0; 553 554 msr.msr_read = false; 555 msr.msr_type = ps->ps_control_addr; 556 msr.msr_value = ps->ps_control; 557 558 if (ps->ps_control_mask != 0) { 559 msr.msr_mask = ps->ps_control_mask; 560 msr.msr_read = true; 561 } 562 563 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 564 xc_wait(xc); 565 566 if (ps->ps_status_addr == 0) 567 return 0; 568 569 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 570 xc_wait(xc); 571 572 return rv; 573 } 574 575 static void 576 acpicpu_md_pstate_status(void *arg1, void *arg2) 577 { 578 struct acpicpu_pstate *ps = arg1; 579 uint64_t val; 580 int i; 581 582 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 583 584 val = rdmsr(ps->ps_status_addr); 585 586 if (ps->ps_status_mask != 0) 587 val = val & ps->ps_status_mask; 588 589 if (val == ps->ps_status) 590 return; 591 592 DELAY(ps->ps_latency); 593 } 594 595 *(uintptr_t *)arg2 = EAGAIN; 596 } 597 598 int 599 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 600 { 601 struct acpicpu_tstate *ts; 602 uint64_t val; 603 uint32_t i; 604 605 if (cpu_vendor != CPUVENDOR_INTEL) 606 return ENODEV; 607 608 val = rdmsr(MSR_THERM_CONTROL); 609 610 for (i = 0; i < sc->sc_tstate_count; i++) { 611 612 ts = &sc->sc_tstate[i]; 613 614 if (ts->ts_percent == 0) 615 continue; 616 617 if (val == ts->ts_control || val == ts->ts_status) { 618 *percent = ts->ts_percent; 619 return 0; 620 } 621 } 622 623 return EIO; 624 } 625 626 int 627 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 628 { 629 struct msr_rw_info msr; 630 uint64_t xc; 631 int rv = 0; 632 633 if (cpu_vendor != CPUVENDOR_INTEL) 634 return ENODEV; 635 636 msr.msr_read = true; 637 msr.msr_type = MSR_THERM_CONTROL; 638 msr.msr_value = ts->ts_control; 639 msr.msr_mask = __BITS(1, 4); 640 641 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 642 xc_wait(xc); 643 644 if (ts->ts_status == 0) 645 return 0; 646 647 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 648 xc_wait(xc); 649 650 return rv; 651 } 652 653 static void 654 acpicpu_md_tstate_status(void *arg1, void *arg2) 655 { 656 struct acpicpu_tstate *ts = arg1; 657 uint64_t val; 658 int i; 659 660 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 661 662 val = rdmsr(MSR_THERM_CONTROL); 663 664 if (val == ts->ts_status) 665 return; 666 667 DELAY(ts->ts_latency); 668 } 669 670 *(uintptr_t *)arg2 = EAGAIN; 671 } 672
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