acpi_cpu_md.c revision 1.17
1 /* $NetBSD: acpi_cpu_md.c,v 1.17 2010/08/19 18:30:24 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.17 2010/08/19 18:30:24 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #define MSR_0FH_CONTROL 0xc0010041 /* Family 0Fh (and K7). */ 52 #define MSR_0FH_STATUS 0xc0010042 53 54 #define MSR_10H_LIMIT 0xc0010061 /* Families 10h and 11h. */ 55 #define MSR_10H_CONTROL 0xc0010062 56 #define MSR_10H_STATUS 0xc0010063 57 #define MSR_10H_CONFIG 0xc0010064 58 59 static char native_idle_text[16]; 60 void (*native_idle)(void) = NULL; 61 void (*native_cpu_freq_init)(int) = NULL; 62 63 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 64 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 65 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 66 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 67 static void acpicpu_md_pstate_status(void *, void *); 68 static void acpicpu_md_tstate_status(void *, void *); 69 70 extern uint32_t cpus_running; 71 extern struct acpicpu_softc **acpicpu_sc; 72 73 uint32_t 74 acpicpu_md_cap(void) 75 { 76 struct cpu_info *ci = curcpu(); 77 uint32_t val = 0; 78 79 if (cpu_vendor != CPUVENDOR_IDT && 80 cpu_vendor != CPUVENDOR_INTEL) 81 return val; 82 83 /* 84 * Basic SMP C-states (required for _CST). 85 */ 86 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 87 88 /* 89 * If MONITOR/MWAIT is available, announce 90 * support for native instructions in all C-states. 91 */ 92 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 93 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 94 95 /* 96 * Set native P- and T-states, if available. 97 */ 98 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 99 val |= ACPICPU_PDC_P_FFH; 100 101 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 102 val |= ACPICPU_PDC_T_FFH; 103 104 return val; 105 } 106 107 uint32_t 108 acpicpu_md_quirks(void) 109 { 110 struct cpu_info *ci = curcpu(); 111 struct pci_attach_args pa; 112 uint32_t val = 0; 113 114 if (acpicpu_md_cpus_running() == 1) 115 val |= ACPICPU_FLAG_C_BM; 116 117 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 118 val |= ACPICPU_FLAG_C_FFH; 119 120 switch (cpu_vendor) { 121 122 case CPUVENDOR_IDT: 123 case CPUVENDOR_INTEL: 124 125 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 126 val |= ACPICPU_FLAG_P_FFH; 127 128 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 129 val |= ACPICPU_FLAG_T_FFH; 130 131 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 132 break; 133 134 case CPUVENDOR_AMD: 135 136 switch (CPUID2FAMILY(ci->ci_signature)) { 137 138 case 0x10: 139 case 0x11: 140 141 if ((ci->ci_feat_val[2] & CPUID_APM_HWP) != 0) 142 val |= ACPICPU_FLAG_P_FFH; 143 } 144 145 break; 146 } 147 148 /* 149 * There are several erratums for PIIX4. 150 */ 151 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 152 val |= ACPICPU_FLAG_PIIX4; 153 154 return val; 155 } 156 157 static int 158 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 159 { 160 161 /* 162 * XXX: The pci_find_device(9) function only 163 * deals with attached devices. Change this 164 * to use something like pci_device_foreach(). 165 */ 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 167 return 0; 168 169 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 170 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 171 return 1; 172 173 return 0; 174 } 175 176 uint32_t 177 acpicpu_md_cpus_running(void) 178 { 179 180 return popcount32(cpus_running); 181 } 182 183 int 184 acpicpu_md_idle_start(void) 185 { 186 const size_t size = sizeof(native_idle_text); 187 188 x86_disable_intr(); 189 x86_cpu_idle_get(&native_idle, native_idle_text, size); 190 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi"); 191 x86_enable_intr(); 192 193 return 0; 194 } 195 196 int 197 acpicpu_md_idle_stop(void) 198 { 199 uint64_t xc; 200 201 x86_disable_intr(); 202 x86_cpu_idle_set(native_idle, native_idle_text); 203 x86_enable_intr(); 204 205 /* 206 * Run a cross-call to ensure that all CPUs are 207 * out from the ACPI idle-loop before detachment. 208 */ 209 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 210 xc_wait(xc); 211 212 return 0; 213 } 214 215 /* 216 * The MD idle loop. Called with interrupts disabled. 217 */ 218 void 219 acpicpu_md_idle_enter(int method, int state) 220 { 221 struct cpu_info *ci = curcpu(); 222 223 switch (method) { 224 225 case ACPICPU_C_STATE_FFH: 226 227 x86_enable_intr(); 228 x86_monitor(&ci->ci_want_resched, 0, 0); 229 230 if (__predict_false(ci->ci_want_resched) != 0) 231 return; 232 233 x86_mwait((state - 1) << 4, 0); 234 break; 235 236 case ACPICPU_C_STATE_HALT: 237 238 if (__predict_false(ci->ci_want_resched) != 0) { 239 x86_enable_intr(); 240 return; 241 } 242 243 x86_stihlt(); 244 break; 245 } 246 } 247 248 int 249 acpicpu_md_pstate_start(void) 250 { 251 const struct sysctlnode *fnode, *mnode, *rnode; 252 const char *str; 253 int rv; 254 255 switch (cpu_vendor) { 256 257 case CPUVENDOR_INTEL: 258 case CPUVENDOR_IDT: 259 str = "est"; 260 break; 261 262 case CPUVENDOR_AMD: 263 str = "powernow"; 264 break; 265 266 default: 267 return ENODEV; 268 } 269 270 /* 271 * A kludge for backwards compatibility. 272 */ 273 native_cpu_freq_init = cpu_freq_init; 274 275 if (cpu_freq_sysctllog != NULL) { 276 sysctl_teardown(&cpu_freq_sysctllog); 277 cpu_freq_sysctllog = NULL; 278 } 279 280 rv = sysctl_createv(&cpu_freq_sysctllog, 0, NULL, &rnode, 281 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 282 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 283 284 if (rv != 0) 285 goto fail; 286 287 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &rnode, &mnode, 288 0, CTLTYPE_NODE, str, NULL, 289 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 290 291 if (rv != 0) 292 goto fail; 293 294 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &mnode, &fnode, 295 0, CTLTYPE_NODE, "frequency", NULL, 296 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 297 298 if (rv != 0) 299 goto fail; 300 301 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 302 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 303 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 304 305 if (rv != 0) 306 goto fail; 307 308 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 309 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 310 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 311 312 if (rv != 0) 313 goto fail; 314 315 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 316 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 317 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 318 319 if (rv != 0) 320 goto fail; 321 322 return 0; 323 324 fail: 325 if (cpu_freq_sysctllog != NULL) { 326 sysctl_teardown(&cpu_freq_sysctllog); 327 cpu_freq_sysctllog = NULL; 328 } 329 330 if (native_cpu_freq_init != NULL) 331 (*native_cpu_freq_init)(cpu_vendor); 332 333 return rv; 334 } 335 336 int 337 acpicpu_md_pstate_stop(void) 338 { 339 340 if (cpu_freq_sysctllog != NULL) { 341 sysctl_teardown(&cpu_freq_sysctllog); 342 cpu_freq_sysctllog = NULL; 343 } 344 345 if (native_cpu_freq_init != NULL) 346 (*native_cpu_freq_init)(cpu_vendor); 347 348 return 0; 349 } 350 351 static int 352 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 353 { 354 struct cpu_info *ci = curcpu(); 355 struct acpicpu_softc *sc; 356 struct sysctlnode node; 357 uint32_t freq; 358 int err; 359 360 sc = acpicpu_sc[ci->ci_acpiid]; 361 362 if (sc == NULL) 363 return ENXIO; 364 365 err = acpicpu_pstate_get(sc, &freq); 366 367 if (err != 0) 368 return err; 369 370 node = *rnode; 371 node.sysctl_data = &freq; 372 373 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 374 375 if (err != 0 || newp == NULL) 376 return err; 377 378 return 0; 379 } 380 381 static int 382 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 383 { 384 struct cpu_info *ci = curcpu(); 385 struct acpicpu_softc *sc; 386 struct sysctlnode node; 387 uint32_t freq; 388 int err; 389 390 sc = acpicpu_sc[ci->ci_acpiid]; 391 392 if (sc == NULL) 393 return ENXIO; 394 395 err = acpicpu_pstate_get(sc, &freq); 396 397 if (err != 0) 398 return err; 399 400 node = *rnode; 401 node.sysctl_data = &freq; 402 403 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 404 405 if (err != 0 || newp == NULL) 406 return err; 407 408 err = acpicpu_pstate_set(sc, freq); 409 410 if (err != 0) 411 return err; 412 413 return 0; 414 } 415 416 static int 417 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 418 { 419 struct cpu_info *ci = curcpu(); 420 struct acpicpu_softc *sc; 421 struct sysctlnode node; 422 char buf[1024]; 423 size_t len; 424 uint32_t i; 425 int err; 426 427 sc = acpicpu_sc[ci->ci_acpiid]; 428 429 if (sc == NULL) 430 return ENXIO; 431 432 (void)memset(&buf, 0, sizeof(buf)); 433 434 mutex_enter(&sc->sc_mtx); 435 436 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 437 438 if (sc->sc_pstate[i].ps_freq == 0) 439 continue; 440 441 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 442 sc->sc_pstate[i].ps_freq, 443 i < (sc->sc_pstate_count - 1) ? " " : ""); 444 } 445 446 mutex_exit(&sc->sc_mtx); 447 448 node = *rnode; 449 node.sysctl_data = buf; 450 451 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 452 453 if (err != 0 || newp == NULL) 454 return err; 455 456 return 0; 457 } 458 459 int 460 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 461 { 462 struct acpicpu_pstate *ps, msr; 463 struct cpu_info *ci = curcpu(); 464 uint32_t i = 0; 465 466 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 467 468 switch (cpu_vendor) { 469 470 case CPUVENDOR_IDT: 471 case CPUVENDOR_INTEL: 472 msr.ps_control_addr = MSR_PERF_CTL; 473 msr.ps_control_mask = __BITS(0, 15); 474 475 msr.ps_status_addr = MSR_PERF_STATUS; 476 msr.ps_status_mask = __BITS(0, 15); 477 break; 478 479 case CPUVENDOR_AMD: 480 481 switch (CPUID2FAMILY(ci->ci_signature)) { 482 483 case 0x10: 484 case 0x11: 485 msr.ps_control_addr = MSR_10H_CONTROL; 486 msr.ps_control_mask = __BITS(0, 2); 487 488 msr.ps_status_addr = MSR_10H_STATUS; 489 msr.ps_status_mask = __BITS(0, 2); 490 break; 491 492 default: 493 494 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 495 return EOPNOTSUPP; 496 } 497 498 break; 499 500 default: 501 return ENODEV; 502 } 503 504 while (i < sc->sc_pstate_count) { 505 506 ps = &sc->sc_pstate[i]; 507 508 if (ps->ps_status_addr == 0) 509 ps->ps_status_addr = msr.ps_status_addr; 510 511 if (ps->ps_status_mask == 0) 512 ps->ps_status_mask = msr.ps_status_mask; 513 514 if (ps->ps_control_addr == 0) 515 ps->ps_control_addr = msr.ps_control_addr; 516 517 if (ps->ps_control_mask == 0) 518 ps->ps_control_mask = msr.ps_control_mask; 519 520 i++; 521 } 522 523 return 0; 524 } 525 526 int 527 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 528 { 529 struct acpicpu_pstate *ps = NULL; 530 uint64_t val; 531 uint32_t i; 532 533 for (i = 0; i < sc->sc_pstate_count; i++) { 534 535 ps = &sc->sc_pstate[i]; 536 537 if (ps->ps_freq != 0) 538 break; 539 } 540 541 if (__predict_false(ps == NULL)) 542 return ENODEV; 543 544 if (ps->ps_status_addr == 0) 545 return EINVAL; 546 547 val = rdmsr(ps->ps_status_addr); 548 549 if (ps->ps_status_mask != 0) 550 val = val & ps->ps_status_mask; 551 552 for (i = 0; i < sc->sc_pstate_count; i++) { 553 554 ps = &sc->sc_pstate[i]; 555 556 if (ps->ps_freq == 0) 557 continue; 558 559 if (val == ps->ps_status) { 560 *freq = ps->ps_freq; 561 return 0; 562 } 563 } 564 565 return EIO; 566 } 567 568 int 569 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 570 { 571 struct msr_rw_info msr; 572 uint64_t xc; 573 int rv = 0; 574 575 msr.msr_read = false; 576 msr.msr_type = ps->ps_control_addr; 577 msr.msr_value = ps->ps_control; 578 579 if (ps->ps_control_mask != 0) { 580 msr.msr_mask = ps->ps_control_mask; 581 msr.msr_read = true; 582 } 583 584 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 585 xc_wait(xc); 586 587 if (ps->ps_status_addr == 0) 588 return 0; 589 590 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 591 xc_wait(xc); 592 593 return rv; 594 } 595 596 static void 597 acpicpu_md_pstate_status(void *arg1, void *arg2) 598 { 599 struct acpicpu_pstate *ps = arg1; 600 uint64_t val; 601 int i; 602 603 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 604 605 val = rdmsr(ps->ps_status_addr); 606 607 if (ps->ps_status_mask != 0) 608 val = val & ps->ps_status_mask; 609 610 if (val == ps->ps_status) 611 return; 612 613 DELAY(ps->ps_latency); 614 } 615 616 *(uintptr_t *)arg2 = EAGAIN; 617 } 618 619 int 620 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 621 { 622 struct acpicpu_tstate *ts; 623 uint64_t val; 624 uint32_t i; 625 626 val = rdmsr(MSR_THERM_CONTROL); 627 628 for (i = 0; i < sc->sc_tstate_count; i++) { 629 630 ts = &sc->sc_tstate[i]; 631 632 if (ts->ts_percent == 0) 633 continue; 634 635 if (val == ts->ts_control || val == ts->ts_status) { 636 *percent = ts->ts_percent; 637 return 0; 638 } 639 } 640 641 return EIO; 642 } 643 644 int 645 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 646 { 647 struct msr_rw_info msr; 648 uint64_t xc; 649 int rv = 0; 650 651 msr.msr_read = true; 652 msr.msr_type = MSR_THERM_CONTROL; 653 msr.msr_value = ts->ts_control; 654 msr.msr_mask = __BITS(1, 4); 655 656 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 657 xc_wait(xc); 658 659 if (ts->ts_status == 0) 660 return 0; 661 662 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 663 xc_wait(xc); 664 665 return rv; 666 } 667 668 static void 669 acpicpu_md_tstate_status(void *arg1, void *arg2) 670 { 671 struct acpicpu_tstate *ts = arg1; 672 uint64_t val; 673 int i; 674 675 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 676 677 val = rdmsr(MSR_THERM_CONTROL); 678 679 if (val == ts->ts_status) 680 return; 681 682 DELAY(ts->ts_latency); 683 } 684 685 *(uintptr_t *)arg2 = EAGAIN; 686 } 687
Indexes created Tue Sep 30 20:09:53 GMT 2025