acpi_cpu_md.c revision 1.18
1 /* $NetBSD: acpi_cpu_md.c,v 1.18 2010/08/19 21:40:45 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.18 2010/08/19 21:40:45 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #define MSR_0FH_CONTROL 0xc0010041 /* Family 0Fh (and K7). */ 52 #define MSR_0FH_STATUS 0xc0010042 53 54 #define MSR_10H_LIMIT 0xc0010061 /* Families 10h and 11h. */ 55 #define MSR_10H_CONTROL 0xc0010062 56 #define MSR_10H_STATUS 0xc0010063 57 #define MSR_10H_CONFIG 0xc0010064 58 59 static char native_idle_text[16]; 60 void (*native_idle)(void) = NULL; 61 void (*native_cpu_freq_init)(int) = NULL; 62 63 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 64 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 65 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 66 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 67 static void acpicpu_md_pstate_status(void *, void *); 68 static void acpicpu_md_tstate_status(void *, void *); 69 70 extern uint32_t cpus_running; 71 extern struct acpicpu_softc **acpicpu_sc; 72 73 uint32_t 74 acpicpu_md_cap(void) 75 { 76 struct cpu_info *ci = curcpu(); 77 uint32_t val = 0; 78 79 if (cpu_vendor != CPUVENDOR_IDT && 80 cpu_vendor != CPUVENDOR_INTEL) 81 return val; 82 83 /* 84 * Basic SMP C-states (required for _CST). 85 */ 86 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 87 88 /* 89 * If MONITOR/MWAIT is available, announce 90 * support for native instructions in all C-states. 91 */ 92 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 93 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 94 95 /* 96 * Set native P- and T-states, if available. 97 */ 98 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 99 val |= ACPICPU_PDC_P_FFH; 100 101 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 102 val |= ACPICPU_PDC_T_FFH; 103 104 return val; 105 } 106 107 uint32_t 108 acpicpu_md_quirks(void) 109 { 110 struct cpu_info *ci = curcpu(); 111 struct pci_attach_args pa; 112 uint32_t family, val = 0; 113 114 if (acpicpu_md_cpus_running() == 1) 115 val |= ACPICPU_FLAG_C_BM; 116 117 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 118 val |= ACPICPU_FLAG_C_FFH; 119 120 switch (cpu_vendor) { 121 122 case CPUVENDOR_IDT: 123 case CPUVENDOR_INTEL: 124 125 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 126 val |= ACPICPU_FLAG_P_FFH; 127 128 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 129 val |= ACPICPU_FLAG_T_FFH; 130 131 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 132 break; 133 134 case CPUVENDOR_AMD: 135 136 family = CPUID2FAMILY(ci->ci_signature); 137 138 if (family == 0xf) 139 family += CPUID2EXTFAMILY(ci->ci_signature); 140 141 switch (family) { 142 143 case 0x10: 144 case 0x11: 145 146 if ((ci->ci_feat_val[2] & CPUID_APM_HWP) != 0) 147 val |= ACPICPU_FLAG_P_FFH; 148 } 149 150 break; 151 } 152 153 /* 154 * There are several erratums for PIIX4. 155 */ 156 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 157 val |= ACPICPU_FLAG_PIIX4; 158 159 return val; 160 } 161 162 static int 163 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 164 { 165 166 /* 167 * XXX: The pci_find_device(9) function only 168 * deals with attached devices. Change this 169 * to use something like pci_device_foreach(). 170 */ 171 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 172 return 0; 173 174 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 175 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 176 return 1; 177 178 return 0; 179 } 180 181 uint32_t 182 acpicpu_md_cpus_running(void) 183 { 184 185 return popcount32(cpus_running); 186 } 187 188 int 189 acpicpu_md_idle_start(void) 190 { 191 const size_t size = sizeof(native_idle_text); 192 193 x86_disable_intr(); 194 x86_cpu_idle_get(&native_idle, native_idle_text, size); 195 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi"); 196 x86_enable_intr(); 197 198 return 0; 199 } 200 201 int 202 acpicpu_md_idle_stop(void) 203 { 204 uint64_t xc; 205 206 x86_disable_intr(); 207 x86_cpu_idle_set(native_idle, native_idle_text); 208 x86_enable_intr(); 209 210 /* 211 * Run a cross-call to ensure that all CPUs are 212 * out from the ACPI idle-loop before detachment. 213 */ 214 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 215 xc_wait(xc); 216 217 return 0; 218 } 219 220 /* 221 * The MD idle loop. Called with interrupts disabled. 222 */ 223 void 224 acpicpu_md_idle_enter(int method, int state) 225 { 226 struct cpu_info *ci = curcpu(); 227 228 switch (method) { 229 230 case ACPICPU_C_STATE_FFH: 231 232 x86_enable_intr(); 233 x86_monitor(&ci->ci_want_resched, 0, 0); 234 235 if (__predict_false(ci->ci_want_resched) != 0) 236 return; 237 238 x86_mwait((state - 1) << 4, 0); 239 break; 240 241 case ACPICPU_C_STATE_HALT: 242 243 if (__predict_false(ci->ci_want_resched) != 0) { 244 x86_enable_intr(); 245 return; 246 } 247 248 x86_stihlt(); 249 break; 250 } 251 } 252 253 int 254 acpicpu_md_pstate_start(void) 255 { 256 const struct sysctlnode *fnode, *mnode, *rnode; 257 const char *str; 258 int rv; 259 260 switch (cpu_vendor) { 261 262 case CPUVENDOR_INTEL: 263 case CPUVENDOR_IDT: 264 str = "est"; 265 break; 266 267 case CPUVENDOR_AMD: 268 str = "powernow"; 269 break; 270 271 default: 272 return ENODEV; 273 } 274 275 /* 276 * A kludge for backwards compatibility. 277 */ 278 native_cpu_freq_init = cpu_freq_init; 279 280 if (cpu_freq_sysctllog != NULL) { 281 sysctl_teardown(&cpu_freq_sysctllog); 282 cpu_freq_sysctllog = NULL; 283 } 284 285 rv = sysctl_createv(&cpu_freq_sysctllog, 0, NULL, &rnode, 286 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 287 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 288 289 if (rv != 0) 290 goto fail; 291 292 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &rnode, &mnode, 293 0, CTLTYPE_NODE, str, NULL, 294 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 295 296 if (rv != 0) 297 goto fail; 298 299 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &mnode, &fnode, 300 0, CTLTYPE_NODE, "frequency", NULL, 301 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 302 303 if (rv != 0) 304 goto fail; 305 306 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 307 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 308 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 309 310 if (rv != 0) 311 goto fail; 312 313 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 314 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 315 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 316 317 if (rv != 0) 318 goto fail; 319 320 rv = sysctl_createv(&cpu_freq_sysctllog, 0, &fnode, &rnode, 321 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 322 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 323 324 if (rv != 0) 325 goto fail; 326 327 return 0; 328 329 fail: 330 if (cpu_freq_sysctllog != NULL) { 331 sysctl_teardown(&cpu_freq_sysctllog); 332 cpu_freq_sysctllog = NULL; 333 } 334 335 if (native_cpu_freq_init != NULL) 336 (*native_cpu_freq_init)(cpu_vendor); 337 338 return rv; 339 } 340 341 int 342 acpicpu_md_pstate_stop(void) 343 { 344 345 if (cpu_freq_sysctllog != NULL) { 346 sysctl_teardown(&cpu_freq_sysctllog); 347 cpu_freq_sysctllog = NULL; 348 } 349 350 if (native_cpu_freq_init != NULL) 351 (*native_cpu_freq_init)(cpu_vendor); 352 353 return 0; 354 } 355 356 static int 357 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 358 { 359 struct cpu_info *ci = curcpu(); 360 struct acpicpu_softc *sc; 361 struct sysctlnode node; 362 uint32_t freq; 363 int err; 364 365 sc = acpicpu_sc[ci->ci_acpiid]; 366 367 if (sc == NULL) 368 return ENXIO; 369 370 err = acpicpu_pstate_get(sc, &freq); 371 372 if (err != 0) 373 return err; 374 375 node = *rnode; 376 node.sysctl_data = &freq; 377 378 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 379 380 if (err != 0 || newp == NULL) 381 return err; 382 383 return 0; 384 } 385 386 static int 387 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 388 { 389 struct cpu_info *ci = curcpu(); 390 struct acpicpu_softc *sc; 391 struct sysctlnode node; 392 uint32_t freq; 393 int err; 394 395 sc = acpicpu_sc[ci->ci_acpiid]; 396 397 if (sc == NULL) 398 return ENXIO; 399 400 err = acpicpu_pstate_get(sc, &freq); 401 402 if (err != 0) 403 return err; 404 405 node = *rnode; 406 node.sysctl_data = &freq; 407 408 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 409 410 if (err != 0 || newp == NULL) 411 return err; 412 413 err = acpicpu_pstate_set(sc, freq); 414 415 if (err != 0) 416 return err; 417 418 return 0; 419 } 420 421 static int 422 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 423 { 424 struct cpu_info *ci = curcpu(); 425 struct acpicpu_softc *sc; 426 struct sysctlnode node; 427 char buf[1024]; 428 size_t len; 429 uint32_t i; 430 int err; 431 432 sc = acpicpu_sc[ci->ci_acpiid]; 433 434 if (sc == NULL) 435 return ENXIO; 436 437 (void)memset(&buf, 0, sizeof(buf)); 438 439 mutex_enter(&sc->sc_mtx); 440 441 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 442 443 if (sc->sc_pstate[i].ps_freq == 0) 444 continue; 445 446 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 447 sc->sc_pstate[i].ps_freq, 448 i < (sc->sc_pstate_count - 1) ? " " : ""); 449 } 450 451 mutex_exit(&sc->sc_mtx); 452 453 node = *rnode; 454 node.sysctl_data = buf; 455 456 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 457 458 if (err != 0 || newp == NULL) 459 return err; 460 461 return 0; 462 } 463 464 int 465 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 466 { 467 struct acpicpu_pstate *ps, msr; 468 struct cpu_info *ci = curcpu(); 469 uint32_t family, i = 0; 470 471 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 472 473 switch (cpu_vendor) { 474 475 case CPUVENDOR_IDT: 476 case CPUVENDOR_INTEL: 477 msr.ps_control_addr = MSR_PERF_CTL; 478 msr.ps_control_mask = __BITS(0, 15); 479 480 msr.ps_status_addr = MSR_PERF_STATUS; 481 msr.ps_status_mask = __BITS(0, 15); 482 break; 483 484 case CPUVENDOR_AMD: 485 486 family = CPUID2FAMILY(ci->ci_signature); 487 488 if (family == 0xf) 489 family += CPUID2EXTFAMILY(ci->ci_signature); 490 491 switch (family) { 492 493 case 0x10: 494 case 0x11: 495 msr.ps_control_addr = MSR_10H_CONTROL; 496 msr.ps_control_mask = __BITS(0, 2); 497 498 msr.ps_status_addr = MSR_10H_STATUS; 499 msr.ps_status_mask = __BITS(0, 2); 500 break; 501 502 default: 503 504 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 505 return EOPNOTSUPP; 506 } 507 508 break; 509 510 default: 511 return ENODEV; 512 } 513 514 while (i < sc->sc_pstate_count) { 515 516 ps = &sc->sc_pstate[i]; 517 518 if (ps->ps_status_addr == 0) 519 ps->ps_status_addr = msr.ps_status_addr; 520 521 if (ps->ps_status_mask == 0) 522 ps->ps_status_mask = msr.ps_status_mask; 523 524 if (ps->ps_control_addr == 0) 525 ps->ps_control_addr = msr.ps_control_addr; 526 527 if (ps->ps_control_mask == 0) 528 ps->ps_control_mask = msr.ps_control_mask; 529 530 i++; 531 } 532 533 return 0; 534 } 535 536 int 537 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 538 { 539 struct acpicpu_pstate *ps = NULL; 540 uint64_t val; 541 uint32_t i; 542 543 for (i = 0; i < sc->sc_pstate_count; i++) { 544 545 ps = &sc->sc_pstate[i]; 546 547 if (ps->ps_freq != 0) 548 break; 549 } 550 551 if (__predict_false(ps == NULL)) 552 return ENODEV; 553 554 if (ps->ps_status_addr == 0) 555 return EINVAL; 556 557 val = rdmsr(ps->ps_status_addr); 558 559 if (ps->ps_status_mask != 0) 560 val = val & ps->ps_status_mask; 561 562 for (i = 0; i < sc->sc_pstate_count; i++) { 563 564 ps = &sc->sc_pstate[i]; 565 566 if (ps->ps_freq == 0) 567 continue; 568 569 if (val == ps->ps_status) { 570 *freq = ps->ps_freq; 571 return 0; 572 } 573 } 574 575 return EIO; 576 } 577 578 int 579 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 580 { 581 struct msr_rw_info msr; 582 uint64_t xc; 583 int rv = 0; 584 585 msr.msr_read = false; 586 msr.msr_type = ps->ps_control_addr; 587 msr.msr_value = ps->ps_control; 588 589 if (ps->ps_control_mask != 0) { 590 msr.msr_mask = ps->ps_control_mask; 591 msr.msr_read = true; 592 } 593 594 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 595 xc_wait(xc); 596 597 if (ps->ps_status_addr == 0) 598 return 0; 599 600 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 601 xc_wait(xc); 602 603 return rv; 604 } 605 606 static void 607 acpicpu_md_pstate_status(void *arg1, void *arg2) 608 { 609 struct acpicpu_pstate *ps = arg1; 610 uint64_t val; 611 int i; 612 613 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 614 615 val = rdmsr(ps->ps_status_addr); 616 617 if (ps->ps_status_mask != 0) 618 val = val & ps->ps_status_mask; 619 620 if (val == ps->ps_status) 621 return; 622 623 DELAY(ps->ps_latency); 624 } 625 626 *(uintptr_t *)arg2 = EAGAIN; 627 } 628 629 int 630 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 631 { 632 struct acpicpu_tstate *ts; 633 uint64_t val; 634 uint32_t i; 635 636 val = rdmsr(MSR_THERM_CONTROL); 637 638 for (i = 0; i < sc->sc_tstate_count; i++) { 639 640 ts = &sc->sc_tstate[i]; 641 642 if (ts->ts_percent == 0) 643 continue; 644 645 if (val == ts->ts_control || val == ts->ts_status) { 646 *percent = ts->ts_percent; 647 return 0; 648 } 649 } 650 651 return EIO; 652 } 653 654 int 655 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 656 { 657 struct msr_rw_info msr; 658 uint64_t xc; 659 int rv = 0; 660 661 msr.msr_read = true; 662 msr.msr_type = MSR_THERM_CONTROL; 663 msr.msr_value = ts->ts_control; 664 msr.msr_mask = __BITS(1, 4); 665 666 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 667 xc_wait(xc); 668 669 if (ts->ts_status == 0) 670 return 0; 671 672 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 673 xc_wait(xc); 674 675 return rv; 676 } 677 678 static void 679 acpicpu_md_tstate_status(void *arg1, void *arg2) 680 { 681 struct acpicpu_tstate *ts = arg1; 682 uint64_t val; 683 int i; 684 685 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 686 687 val = rdmsr(MSR_THERM_CONTROL); 688 689 if (val == ts->ts_status) 690 return; 691 692 DELAY(ts->ts_latency); 693 } 694 695 *(uintptr_t *)arg2 = EAGAIN; 696 } 697
Indexes created Tue Sep 30 20:09:53 GMT 2025