acpi_cpu_md.c revision 1.21
1 /* $NetBSD: acpi_cpu_md.c,v 1.21 2010/08/21 02:47:37 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.21 2010/08/21 02:47:37 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 #define MSR_0FH_CONTROL 0xc0010041 /* Family 0Fh (and K7). */ 52 #define MSR_0FH_STATUS 0xc0010042 53 54 #define MSR_10H_LIMIT 0xc0010061 /* Families 10h and 11h. */ 55 #define MSR_10H_CONTROL 0xc0010062 56 #define MSR_10H_STATUS 0xc0010063 57 #define MSR_10H_CONFIG 0xc0010064 58 59 static char native_idle_text[16]; 60 void (*native_idle)(void) = NULL; 61 62 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 63 static void acpicpu_md_pstate_status(void *, void *); 64 static void acpicpu_md_tstate_status(void *, void *); 65 static int acpicpu_md_pstate_sysctl_init(void); 66 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 67 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 68 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 69 70 extern uint32_t cpus_running; 71 extern struct acpicpu_softc **acpicpu_sc; 72 static struct sysctllog *acpicpu_log = NULL; 73 74 uint32_t 75 acpicpu_md_cap(void) 76 { 77 struct cpu_info *ci = curcpu(); 78 uint32_t val = 0; 79 80 if (cpu_vendor != CPUVENDOR_IDT && 81 cpu_vendor != CPUVENDOR_INTEL) 82 return val; 83 84 /* 85 * Basic SMP C-states (required for _CST). 86 */ 87 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 88 89 /* 90 * If MONITOR/MWAIT is available, announce 91 * support for native instructions in all C-states. 92 */ 93 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 94 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 95 96 /* 97 * Set native P- and T-states, if available. 98 */ 99 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 100 val |= ACPICPU_PDC_P_FFH; 101 102 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 103 val |= ACPICPU_PDC_T_FFH; 104 105 return val; 106 } 107 108 uint32_t 109 acpicpu_md_quirks(void) 110 { 111 struct cpu_info *ci = curcpu(); 112 struct pci_attach_args pa; 113 uint32_t family, val = 0; 114 uint32_t regs[4]; 115 116 if (acpicpu_md_cpus_running() == 1) 117 val |= ACPICPU_FLAG_C_BM; 118 119 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 120 val |= ACPICPU_FLAG_C_FFH; 121 122 switch (cpu_vendor) { 123 124 case CPUVENDOR_IDT: 125 case CPUVENDOR_INTEL: 126 127 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 128 val |= ACPICPU_FLAG_P_FFH; 129 130 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 131 val |= ACPICPU_FLAG_T_FFH; 132 133 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 134 break; 135 136 case CPUVENDOR_AMD: 137 138 family = CPUID2FAMILY(ci->ci_signature); 139 140 if (family == 0xf) 141 family += CPUID2EXTFAMILY(ci->ci_signature); 142 143 switch (family) { 144 145 case 0x10: 146 case 0x11: 147 148 x86_cpuid(0x80000007, regs); 149 150 if ((regs[3] & CPUID_APM_HWP) != 0) 151 val |= ACPICPU_FLAG_P_FFH; 152 153 if ((regs[3] & CPUID_APM_CPB) != 0) 154 val |= ACPICPU_FLAG_P_TURBO; 155 } 156 157 break; 158 } 159 160 /* 161 * There are several erratums for PIIX4. 162 */ 163 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 164 val |= ACPICPU_FLAG_PIIX4; 165 166 return val; 167 } 168 169 static int 170 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 171 { 172 173 /* 174 * XXX: The pci_find_device(9) function only 175 * deals with attached devices. Change this 176 * to use something like pci_device_foreach(). 177 */ 178 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 179 return 0; 180 181 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 182 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 183 return 1; 184 185 return 0; 186 } 187 188 uint32_t 189 acpicpu_md_cpus_running(void) 190 { 191 192 return popcount32(cpus_running); 193 } 194 195 int 196 acpicpu_md_idle_start(void) 197 { 198 const size_t size = sizeof(native_idle_text); 199 200 x86_disable_intr(); 201 x86_cpu_idle_get(&native_idle, native_idle_text, size); 202 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi"); 203 x86_enable_intr(); 204 205 return 0; 206 } 207 208 int 209 acpicpu_md_idle_stop(void) 210 { 211 uint64_t xc; 212 213 x86_disable_intr(); 214 x86_cpu_idle_set(native_idle, native_idle_text); 215 x86_enable_intr(); 216 217 /* 218 * Run a cross-call to ensure that all CPUs are 219 * out from the ACPI idle-loop before detachment. 220 */ 221 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 222 xc_wait(xc); 223 224 return 0; 225 } 226 227 /* 228 * The MD idle loop. Called with interrupts disabled. 229 */ 230 void 231 acpicpu_md_idle_enter(int method, int state) 232 { 233 struct cpu_info *ci = curcpu(); 234 235 switch (method) { 236 237 case ACPICPU_C_STATE_FFH: 238 239 x86_enable_intr(); 240 x86_monitor(&ci->ci_want_resched, 0, 0); 241 242 if (__predict_false(ci->ci_want_resched) != 0) 243 return; 244 245 x86_mwait((state - 1) << 4, 0); 246 break; 247 248 case ACPICPU_C_STATE_HALT: 249 250 if (__predict_false(ci->ci_want_resched) != 0) { 251 x86_enable_intr(); 252 return; 253 } 254 255 x86_stihlt(); 256 break; 257 } 258 } 259 260 int 261 acpicpu_md_pstate_start(void) 262 { 263 const uint64_t est = __BIT(16); 264 uint64_t val; 265 266 switch (cpu_vendor) { 267 268 case CPUVENDOR_IDT: 269 case CPUVENDOR_INTEL: 270 271 val = rdmsr(MSR_MISC_ENABLE); 272 273 if ((val & est) == 0) { 274 275 val |= est; 276 277 wrmsr(MSR_MISC_ENABLE, val); 278 val = rdmsr(MSR_MISC_ENABLE); 279 280 if ((val & est) == 0) 281 return ENOTTY; 282 } 283 } 284 285 return acpicpu_md_pstate_sysctl_init(); 286 } 287 288 int 289 acpicpu_md_pstate_stop(void) 290 { 291 292 if (acpicpu_log != NULL) 293 sysctl_teardown(&acpicpu_log); 294 295 return 0; 296 } 297 298 int 299 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 300 { 301 struct acpicpu_pstate *ps, msr; 302 struct cpu_info *ci = curcpu(); 303 uint32_t family, i = 0; 304 305 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 306 307 switch (cpu_vendor) { 308 309 case CPUVENDOR_IDT: 310 case CPUVENDOR_INTEL: 311 msr.ps_control_addr = MSR_PERF_CTL; 312 msr.ps_control_mask = __BITS(0, 15); 313 314 msr.ps_status_addr = MSR_PERF_STATUS; 315 msr.ps_status_mask = __BITS(0, 15); 316 break; 317 318 case CPUVENDOR_AMD: 319 320 family = CPUID2FAMILY(ci->ci_signature); 321 322 if (family == 0xf) 323 family += CPUID2EXTFAMILY(ci->ci_signature); 324 325 switch (family) { 326 327 case 0x10: 328 case 0x11: 329 msr.ps_control_addr = MSR_10H_CONTROL; 330 msr.ps_control_mask = __BITS(0, 2); 331 332 msr.ps_status_addr = MSR_10H_STATUS; 333 msr.ps_status_mask = __BITS(0, 2); 334 break; 335 336 default: 337 338 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 339 return EOPNOTSUPP; 340 } 341 342 break; 343 344 default: 345 return ENODEV; 346 } 347 348 while (i < sc->sc_pstate_count) { 349 350 ps = &sc->sc_pstate[i]; 351 352 if (ps->ps_status_addr == 0) 353 ps->ps_status_addr = msr.ps_status_addr; 354 355 if (ps->ps_status_mask == 0) 356 ps->ps_status_mask = msr.ps_status_mask; 357 358 if (ps->ps_control_addr == 0) 359 ps->ps_control_addr = msr.ps_control_addr; 360 361 if (ps->ps_control_mask == 0) 362 ps->ps_control_mask = msr.ps_control_mask; 363 364 i++; 365 } 366 367 return 0; 368 } 369 370 int 371 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 372 { 373 struct acpicpu_pstate *ps = NULL; 374 uint64_t val; 375 uint32_t i; 376 377 for (i = 0; i < sc->sc_pstate_count; i++) { 378 379 ps = &sc->sc_pstate[i]; 380 381 if (ps->ps_freq != 0) 382 break; 383 } 384 385 if (__predict_false(ps == NULL)) 386 return ENODEV; 387 388 if (ps->ps_status_addr == 0) 389 return EINVAL; 390 391 val = rdmsr(ps->ps_status_addr); 392 393 if (ps->ps_status_mask != 0) 394 val = val & ps->ps_status_mask; 395 396 for (i = 0; i < sc->sc_pstate_count; i++) { 397 398 ps = &sc->sc_pstate[i]; 399 400 if (ps->ps_freq == 0) 401 continue; 402 403 if (val == ps->ps_status) { 404 *freq = ps->ps_freq; 405 return 0; 406 } 407 } 408 409 return EIO; 410 } 411 412 int 413 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 414 { 415 struct msr_rw_info msr; 416 uint64_t xc; 417 int rv = 0; 418 419 msr.msr_read = false; 420 msr.msr_type = ps->ps_control_addr; 421 msr.msr_value = ps->ps_control; 422 423 if (ps->ps_control_mask != 0) { 424 msr.msr_mask = ps->ps_control_mask; 425 msr.msr_read = true; 426 } 427 428 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 429 xc_wait(xc); 430 431 if (ps->ps_status_addr == 0) 432 return 0; 433 434 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 435 xc_wait(xc); 436 437 return rv; 438 } 439 440 static void 441 acpicpu_md_pstate_status(void *arg1, void *arg2) 442 { 443 struct acpicpu_pstate *ps = arg1; 444 uint64_t val; 445 int i; 446 447 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 448 449 val = rdmsr(ps->ps_status_addr); 450 451 if (ps->ps_status_mask != 0) 452 val = val & ps->ps_status_mask; 453 454 if (val == ps->ps_status) 455 return; 456 457 DELAY(ps->ps_latency); 458 } 459 460 *(uintptr_t *)arg2 = EAGAIN; 461 } 462 463 int 464 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 465 { 466 struct acpicpu_tstate *ts; 467 uint64_t val; 468 uint32_t i; 469 470 val = rdmsr(MSR_THERM_CONTROL); 471 472 for (i = 0; i < sc->sc_tstate_count; i++) { 473 474 ts = &sc->sc_tstate[i]; 475 476 if (ts->ts_percent == 0) 477 continue; 478 479 if (val == ts->ts_control || val == ts->ts_status) { 480 *percent = ts->ts_percent; 481 return 0; 482 } 483 } 484 485 return EIO; 486 } 487 488 int 489 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 490 { 491 struct msr_rw_info msr; 492 uint64_t xc; 493 int rv = 0; 494 495 msr.msr_read = true; 496 msr.msr_type = MSR_THERM_CONTROL; 497 msr.msr_value = ts->ts_control; 498 msr.msr_mask = __BITS(1, 4); 499 500 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 501 xc_wait(xc); 502 503 if (ts->ts_status == 0) 504 return 0; 505 506 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 507 xc_wait(xc); 508 509 return rv; 510 } 511 512 static void 513 acpicpu_md_tstate_status(void *arg1, void *arg2) 514 { 515 struct acpicpu_tstate *ts = arg1; 516 uint64_t val; 517 int i; 518 519 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 520 521 val = rdmsr(MSR_THERM_CONTROL); 522 523 if (val == ts->ts_status) 524 return; 525 526 DELAY(ts->ts_latency); 527 } 528 529 *(uintptr_t *)arg2 = EAGAIN; 530 } 531 532 /* 533 * A kludge for backwards compatibility. 534 */ 535 static int 536 acpicpu_md_pstate_sysctl_init(void) 537 { 538 const struct sysctlnode *fnode, *mnode, *rnode; 539 const char *str; 540 int rv; 541 542 switch (cpu_vendor) { 543 544 case CPUVENDOR_IDT: 545 case CPUVENDOR_INTEL: 546 str = "est"; 547 break; 548 549 case CPUVENDOR_AMD: 550 str = "powernow"; 551 break; 552 553 default: 554 return ENODEV; 555 } 556 557 558 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 559 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 560 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 561 562 if (rv != 0) 563 goto fail; 564 565 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 566 0, CTLTYPE_NODE, str, NULL, 567 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 568 569 if (rv != 0) 570 goto fail; 571 572 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 573 0, CTLTYPE_NODE, "frequency", NULL, 574 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 575 576 if (rv != 0) 577 goto fail; 578 579 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 580 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 581 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 582 583 if (rv != 0) 584 goto fail; 585 586 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 587 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 588 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 589 590 if (rv != 0) 591 goto fail; 592 593 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 594 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 595 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 596 597 if (rv != 0) 598 goto fail; 599 600 return 0; 601 602 fail: 603 if (acpicpu_log != NULL) { 604 sysctl_teardown(&acpicpu_log); 605 acpicpu_log = NULL; 606 } 607 608 return rv; 609 } 610 611 static int 612 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 613 { 614 struct cpu_info *ci = curcpu(); 615 struct acpicpu_softc *sc; 616 struct sysctlnode node; 617 uint32_t freq; 618 int err; 619 620 sc = acpicpu_sc[ci->ci_acpiid]; 621 622 if (sc == NULL) 623 return ENXIO; 624 625 err = acpicpu_pstate_get(sc, &freq); 626 627 if (err != 0) 628 return err; 629 630 node = *rnode; 631 node.sysctl_data = &freq; 632 633 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 634 635 if (err != 0 || newp == NULL) 636 return err; 637 638 return 0; 639 } 640 641 static int 642 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 643 { 644 struct cpu_info *ci = curcpu(); 645 struct acpicpu_softc *sc; 646 struct sysctlnode node; 647 uint32_t freq; 648 int err; 649 650 sc = acpicpu_sc[ci->ci_acpiid]; 651 652 if (sc == NULL) 653 return ENXIO; 654 655 err = acpicpu_pstate_get(sc, &freq); 656 657 if (err != 0) 658 return err; 659 660 node = *rnode; 661 node.sysctl_data = &freq; 662 663 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 664 665 if (err != 0 || newp == NULL) 666 return err; 667 668 err = acpicpu_pstate_set(sc, freq); 669 670 if (err != 0) 671 return err; 672 673 return 0; 674 } 675 676 static int 677 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 678 { 679 struct cpu_info *ci = curcpu(); 680 struct acpicpu_softc *sc; 681 struct sysctlnode node; 682 char buf[1024]; 683 size_t len; 684 uint32_t i; 685 int err; 686 687 sc = acpicpu_sc[ci->ci_acpiid]; 688 689 if (sc == NULL) 690 return ENXIO; 691 692 (void)memset(&buf, 0, sizeof(buf)); 693 694 mutex_enter(&sc->sc_mtx); 695 696 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 697 698 if (sc->sc_pstate[i].ps_freq == 0) 699 continue; 700 701 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 702 sc->sc_pstate[i].ps_freq, 703 i < (sc->sc_pstate_count - 1) ? " " : ""); 704 } 705 706 mutex_exit(&sc->sc_mtx); 707 708 node = *rnode; 709 node.sysctl_data = buf; 710 711 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 712 713 if (err != 0 || newp == NULL) 714 return err; 715 716 return 0; 717 } 718 719
Indexes created Tue Sep 30 20:09:53 GMT 2025