acpi_cpu_md.c revision 1.32
1 /* $NetBSD: acpi_cpu_md.c,v 1.32 2010/08/24 07:28:00 jruoho Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Jukka Ruohonen <jruohonen (at) iki.fi> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.32 2010/08/24 07:28:00 jruoho Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/kcore.h> 35 #include <sys/sysctl.h> 36 #include <sys/xcall.h> 37 38 #include <x86/cpu.h> 39 #include <x86/cpufunc.h> 40 #include <x86/cputypes.h> 41 #include <x86/cpuvar.h> 42 #include <x86/cpu_msr.h> 43 #include <x86/machdep.h> 44 45 #include <dev/acpi/acpica.h> 46 #include <dev/acpi/acpi_cpu.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcidevs.h> 50 51 /* 52 * AMD families 10h and 11h. 53 */ 54 #define MSR_10H_LIMIT 0xc0010061 55 #define MSR_10H_CONTROL 0xc0010062 56 #define MSR_10H_STATUS 0xc0010063 57 #define MSR_10H_CONFIG 0xc0010064 58 59 /* 60 * AMD family 0Fh. 61 */ 62 #define MSR_0FH_CONTROL 0xc0010041 63 #define MSR_0FH_STATUS 0xc0010042 64 65 #define MSR_0FH_STATUS_CFID __BITS( 0, 5) 66 #define MSR_0FH_STATUS_CVID __BITS(32, 36) 67 #define MSR_0FH_STATUS_PENDING __BITS(31, 31) 68 69 #define MSR_0FH_CONTROL_FID __BITS( 0, 5) 70 #define MSR_0FH_CONTROL_VID __BITS( 8, 12) 71 #define MSR_0FH_CONTROL_CHG __BITS(16, 16) 72 #define MSR_0FH_CONTROL_CNT __BITS(32, 51) 73 74 #define ACPI_0FH_STATUS_FID __BITS( 0, 5) 75 #define ACPI_0FH_STATUS_VID __BITS( 6, 10) 76 77 #define ACPI_0FH_CONTROL_FID __BITS( 0, 5) 78 #define ACPI_0FH_CONTROL_VID __BITS( 6, 10) 79 #define ACPI_0FH_CONTROL_VST __BITS(11, 17) 80 #define ACPI_0FH_CONTROL_MVS __BITS(18, 19) 81 #define ACPI_0FH_CONTROL_PLL __BITS(20, 26) 82 #define ACPI_0FH_CONTROL_RVO __BITS(28, 29) 83 #define ACPI_0FH_CONTROL_IRT __BITS(30, 31) 84 85 #define FID_TO_VCO_FID(fidd) (((fid) < 8) ? (8 + ((fid) << 1)) : (fid)) 86 87 static char native_idle_text[16]; 88 void (*native_idle)(void) = NULL; 89 90 static int acpicpu_md_quirks_piix4(struct pci_attach_args *); 91 static void acpicpu_md_pstate_status(void *, void *); 92 static int acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *, 93 uint32_t *); 94 static int acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *); 95 static int acpicpu_md_pstate_fidvid_read(uint32_t *, uint32_t *); 96 static void acpicpu_md_pstate_fidvid_write(uint32_t, uint32_t, 97 uint32_t, uint32_t); 98 static void acpicpu_md_tstate_status(void *, void *); 99 static int acpicpu_md_pstate_sysctl_init(void); 100 static int acpicpu_md_pstate_sysctl_get(SYSCTLFN_PROTO); 101 static int acpicpu_md_pstate_sysctl_set(SYSCTLFN_PROTO); 102 static int acpicpu_md_pstate_sysctl_all(SYSCTLFN_PROTO); 103 104 extern uint32_t cpus_running; 105 extern struct acpicpu_softc **acpicpu_sc; 106 static struct sysctllog *acpicpu_log = NULL; 107 108 uint32_t 109 acpicpu_md_cap(void) 110 { 111 struct cpu_info *ci = curcpu(); 112 uint32_t val = 0; 113 114 if (cpu_vendor != CPUVENDOR_IDT && 115 cpu_vendor != CPUVENDOR_INTEL) 116 return val; 117 118 /* 119 * Basic SMP C-states (required for _CST). 120 */ 121 val |= ACPICPU_PDC_C_C1PT | ACPICPU_PDC_C_C2C3; 122 123 /* 124 * If MONITOR/MWAIT is available, announce 125 * support for native instructions in all C-states. 126 */ 127 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 128 val |= ACPICPU_PDC_C_C1_FFH | ACPICPU_PDC_C_C2C3_FFH; 129 130 /* 131 * Set native P- and T-states, if available. 132 */ 133 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 134 val |= ACPICPU_PDC_P_FFH; 135 136 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 137 val |= ACPICPU_PDC_T_FFH; 138 139 return val; 140 } 141 142 uint32_t 143 acpicpu_md_quirks(void) 144 { 145 struct cpu_info *ci = curcpu(); 146 struct pci_attach_args pa; 147 uint32_t family, val = 0; 148 uint32_t regs[4]; 149 150 if (acpicpu_md_cpus_running() == 1) 151 val |= ACPICPU_FLAG_C_BM; 152 153 if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0) 154 val |= ACPICPU_FLAG_C_FFH; 155 156 val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC; 157 158 switch (cpu_vendor) { 159 160 case CPUVENDOR_IDT: 161 162 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 163 val |= ACPICPU_FLAG_P_FFH; 164 165 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 166 val |= ACPICPU_FLAG_T_FFH; 167 168 break; 169 170 case CPUVENDOR_INTEL: 171 172 val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB; 173 174 if ((ci->ci_feat_val[1] & CPUID2_EST) != 0) 175 val |= ACPICPU_FLAG_P_FFH; 176 177 if ((ci->ci_feat_val[0] & CPUID_ACPI) != 0) 178 val |= ACPICPU_FLAG_T_FFH; 179 180 /* 181 * Check whether MSR_APERF, MSR_MPERF, and Turbo 182 * Boost are available. Also see if we might have 183 * an invariant local APIC timer ("ARAT"). 184 */ 185 if (cpuid_level >= 0x06) { 186 187 x86_cpuid(0x06, regs); 188 189 if ((regs[2] & __BIT(0)) != 0) /* ECX.06[0] */ 190 val |= ACPICPU_FLAG_P_HW; 191 192 if ((regs[0] & __BIT(1)) != 0) /* EAX.06[1] */ 193 val |= ACPICPU_FLAG_P_TURBO; 194 195 if ((regs[0] & __BIT(2)) != 0) /* EAX.06[2] */ 196 val &= ~ACPICPU_FLAG_C_APIC; 197 } 198 199 /* 200 * Detect whether TSC is invariant. If it is not, 201 * we keep the flag to note that TSC will not run 202 * at constant rate. Depending on the CPU, this may 203 * affect P- and T-state changes, but especially 204 * relevant are C-states; with variant TSC, states 205 * larger than C1 may completely stop the counter. 206 */ 207 x86_cpuid(0x80000000, regs); 208 209 if (regs[0] >= 0x80000007) { 210 211 x86_cpuid(0x80000007, regs); 212 213 if ((regs[3] & __BIT(8)) != 0) 214 val &= ~ACPICPU_FLAG_C_TSC; 215 } 216 217 break; 218 219 case CPUVENDOR_AMD: 220 221 x86_cpuid(0x80000000, regs); 222 223 if (regs[0] < 0x80000007) 224 break; 225 226 x86_cpuid(0x80000007, regs); 227 228 family = CPUID2FAMILY(ci->ci_signature); 229 230 if (family == 0xf) 231 family += CPUID2EXTFAMILY(ci->ci_signature); 232 233 switch (family) { 234 235 case 0x0f: 236 237 if ((regs[3] & CPUID_APM_FID) == 0) 238 break; 239 240 if ((regs[3] & CPUID_APM_VID) == 0) 241 break; 242 243 val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; 244 break; 245 246 case 0x10: 247 case 0x11: 248 249 if ((regs[3] & CPUID_APM_TSC) != 0) 250 val &= ~ACPICPU_FLAG_C_TSC; 251 252 if ((regs[3] & CPUID_APM_HWP) != 0) 253 val |= ACPICPU_FLAG_P_FFH; 254 255 if ((regs[3] & CPUID_APM_CPB) != 0) 256 val |= ACPICPU_FLAG_P_TURBO; 257 } 258 259 break; 260 } 261 262 /* 263 * There are several erratums for PIIX4. 264 */ 265 if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) 266 val |= ACPICPU_FLAG_PIIX4; 267 268 return val; 269 } 270 271 static int 272 acpicpu_md_quirks_piix4(struct pci_attach_args *pa) 273 { 274 275 /* 276 * XXX: The pci_find_device(9) function only 277 * deals with attached devices. Change this 278 * to use something like pci_device_foreach(). 279 */ 280 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 281 return 0; 282 283 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_ISA || 284 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_PMC) 285 return 1; 286 287 return 0; 288 } 289 290 uint32_t 291 acpicpu_md_cpus_running(void) 292 { 293 294 return popcount32(cpus_running); 295 } 296 297 int 298 acpicpu_md_idle_start(struct acpicpu_softc *sc) 299 { 300 const size_t size = sizeof(native_idle_text); 301 struct acpicpu_cstate *cs; 302 bool ipi = false; 303 int i; 304 305 x86_cpu_idle_get(&native_idle, native_idle_text, size); 306 307 for (i = 0; i < ACPI_C_STATE_COUNT; i++) { 308 309 cs = &sc->sc_cstate[i]; 310 311 if (cs->cs_method == ACPICPU_C_STATE_HALT) { 312 ipi = true; 313 break; 314 } 315 } 316 317 x86_cpu_idle_set(acpicpu_cstate_idle, "acpi", ipi); 318 319 return 0; 320 } 321 322 int 323 acpicpu_md_idle_stop(void) 324 { 325 uint64_t xc; 326 bool ipi; 327 328 ipi = (native_idle != x86_cpu_idle_halt) ? false : true; 329 x86_cpu_idle_set(native_idle, native_idle_text, ipi); 330 331 /* 332 * Run a cross-call to ensure that all CPUs are 333 * out from the ACPI idle-loop before detachment. 334 */ 335 xc = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 336 xc_wait(xc); 337 338 return 0; 339 } 340 341 /* 342 * Called with interrupts disabled. 343 * Caller should enable interrupts after return. 344 */ 345 void 346 acpicpu_md_idle_enter(int method, int state) 347 { 348 struct cpu_info *ci = curcpu(); 349 350 switch (method) { 351 352 case ACPICPU_C_STATE_FFH: 353 354 x86_enable_intr(); 355 x86_monitor(&ci->ci_want_resched, 0, 0); 356 357 if (__predict_false(ci->ci_want_resched != 0)) 358 return; 359 360 x86_mwait((state - 1) << 4, 0); 361 break; 362 363 case ACPICPU_C_STATE_HALT: 364 365 if (__predict_false(ci->ci_want_resched != 0)) 366 return; 367 368 x86_stihlt(); 369 break; 370 } 371 } 372 373 int 374 acpicpu_md_pstate_start(void) 375 { 376 const uint64_t est = __BIT(16); 377 uint64_t val; 378 379 switch (cpu_vendor) { 380 381 case CPUVENDOR_IDT: 382 case CPUVENDOR_INTEL: 383 384 val = rdmsr(MSR_MISC_ENABLE); 385 386 if ((val & est) == 0) { 387 388 val |= est; 389 390 wrmsr(MSR_MISC_ENABLE, val); 391 val = rdmsr(MSR_MISC_ENABLE); 392 393 if ((val & est) == 0) 394 return ENOTTY; 395 } 396 } 397 398 return acpicpu_md_pstate_sysctl_init(); 399 } 400 401 int 402 acpicpu_md_pstate_stop(void) 403 { 404 405 if (acpicpu_log != NULL) 406 sysctl_teardown(&acpicpu_log); 407 408 return 0; 409 } 410 411 int 412 acpicpu_md_pstate_pss(struct acpicpu_softc *sc) 413 { 414 struct acpicpu_pstate *ps, msr; 415 struct cpu_info *ci = curcpu(); 416 uint32_t family, i = 0; 417 418 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); 419 420 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 421 msr.ps_flags = ACPICPU_FLAG_P_FIDVID; 422 423 switch (cpu_vendor) { 424 425 case CPUVENDOR_IDT: 426 case CPUVENDOR_INTEL: 427 msr.ps_control_addr = MSR_PERF_CTL; 428 msr.ps_control_mask = __BITS(0, 15); 429 430 msr.ps_status_addr = MSR_PERF_STATUS; 431 msr.ps_status_mask = __BITS(0, 15); 432 break; 433 434 case CPUVENDOR_AMD: 435 436 family = CPUID2FAMILY(ci->ci_signature); 437 438 if (family == 0xf) 439 family += CPUID2EXTFAMILY(ci->ci_signature); 440 441 switch (family) { 442 443 case 0x0f: 444 msr.ps_control_addr = MSR_0FH_CONTROL; 445 msr.ps_status_addr = MSR_0FH_STATUS; 446 break; 447 448 case 0x10: 449 case 0x11: 450 msr.ps_control_addr = MSR_10H_CONTROL; 451 msr.ps_control_mask = __BITS(0, 2); 452 453 msr.ps_status_addr = MSR_10H_STATUS; 454 msr.ps_status_mask = __BITS(0, 2); 455 break; 456 457 default: 458 459 if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) 460 return EOPNOTSUPP; 461 } 462 463 break; 464 465 default: 466 return ENODEV; 467 } 468 469 /* 470 * Fill the P-state structures with MSR addresses that are 471 * known to be correct. If we do not know the addresses, 472 * leave the values intact. If a vendor uses XPSS, we do 473 * not necessary need to do anything to support new CPUs. 474 */ 475 while (i < sc->sc_pstate_count) { 476 477 ps = &sc->sc_pstate[i]; 478 479 if (msr.ps_flags != 0) 480 ps->ps_flags |= msr.ps_flags; 481 482 if (msr.ps_status_addr != 0) 483 ps->ps_status_addr = msr.ps_status_addr; 484 485 if (msr.ps_status_mask != 0) 486 ps->ps_status_mask = msr.ps_status_mask; 487 488 if (msr.ps_control_addr != 0) 489 ps->ps_control_addr = msr.ps_control_addr; 490 491 if (msr.ps_control_mask != 0) 492 ps->ps_control_mask = msr.ps_control_mask; 493 494 i++; 495 } 496 497 /* 498 * When the state is P0 and Turbo Boost has been 499 * detected, we need to skip the status check as 500 * BIOS may not report right comparison values for 501 * the IA32_PERF_STATUS register. Note that this 502 * issue is specific to Intel. For discussion, see: 503 * 504 * Intel Corporation: Intel Turbo Boost Technology 505 * in Intel Core(tm) Microarchitectures (Nehalem) 506 * Based Processors. White Paper, November 2008. 507 */ 508 if (cpu_vendor != CPUVENDOR_INTEL) 509 return 0; 510 511 if ((sc->sc_flags & ACPICPU_FLAG_P_TURBO) == 0) 512 return 0; 513 514 if (sc->sc_pstate[1].ps_freq + 1 == sc->sc_pstate[0].ps_freq) 515 sc->sc_pstate[0].ps_flags |= ACPICPU_FLAG_P_TURBO; 516 517 return 0; 518 } 519 520 int 521 acpicpu_md_pstate_get(struct acpicpu_softc *sc, uint32_t *freq) 522 { 523 struct acpicpu_pstate *ps = NULL; 524 uint64_t val; 525 uint32_t i; 526 527 if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0) 528 return acpicpu_md_pstate_fidvid_get(sc, freq); 529 530 for (i = 0; i < sc->sc_pstate_count; i++) { 531 532 ps = &sc->sc_pstate[i]; 533 534 if (__predict_true(ps->ps_freq != 0)) 535 break; 536 } 537 538 if (__predict_false(ps == NULL)) 539 return ENODEV; 540 541 if (__predict_false(ps->ps_status_addr == 0)) 542 return EINVAL; 543 544 val = rdmsr(ps->ps_status_addr); 545 546 if (__predict_true(ps->ps_status_mask != 0)) 547 val = val & ps->ps_status_mask; 548 549 for (i = 0; i < sc->sc_pstate_count; i++) { 550 551 ps = &sc->sc_pstate[i]; 552 553 if (__predict_false(ps->ps_freq == 0)) 554 continue; 555 556 if (val == ps->ps_status) { 557 *freq = ps->ps_freq; 558 return 0; 559 } 560 } 561 562 return EIO; 563 } 564 565 int 566 acpicpu_md_pstate_set(struct acpicpu_pstate *ps) 567 { 568 struct msr_rw_info msr; 569 uint64_t xc; 570 int rv = 0; 571 572 if ((ps->ps_flags & ACPICPU_FLAG_P_FIDVID) != 0) 573 return acpicpu_md_pstate_fidvid_set(ps); 574 575 msr.msr_read = false; 576 msr.msr_type = ps->ps_control_addr; 577 msr.msr_value = ps->ps_control; 578 579 if (__predict_true(ps->ps_control_mask != 0)) { 580 msr.msr_mask = ps->ps_control_mask; 581 msr.msr_read = true; 582 } 583 584 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 585 xc_wait(xc); 586 587 if (__predict_false(ps->ps_status == 0)) 588 goto out; 589 590 if (__predict_false(ps->ps_status_addr == 0)) 591 goto out; 592 593 if ((ps->ps_flags & ACPICPU_FLAG_P_TURBO) != 0) 594 goto out; 595 596 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_pstate_status, ps, &rv); 597 xc_wait(xc); 598 599 return rv; 600 601 out: 602 DELAY(ps->ps_latency); 603 604 return 0; 605 } 606 607 static void 608 acpicpu_md_pstate_status(void *arg1, void *arg2) 609 { 610 struct acpicpu_pstate *ps = arg1; 611 uint64_t val; 612 int i; 613 614 for (i = val = 0; i < ACPICPU_P_STATE_RETRY; i++) { 615 616 val = rdmsr(ps->ps_status_addr); 617 618 if (__predict_true(ps->ps_status_mask != 0)) 619 val = val & ps->ps_status_mask; 620 621 if (val == ps->ps_status) 622 return; 623 624 DELAY(ps->ps_latency); 625 } 626 627 *(uintptr_t *)arg2 = EAGAIN; 628 } 629 630 static int 631 acpicpu_md_pstate_fidvid_get(struct acpicpu_softc *sc, uint32_t *freq) 632 { 633 struct acpicpu_pstate *ps; 634 uint32_t fid, i, vid; 635 uint32_t cfid, cvid; 636 int rv; 637 638 /* 639 * AMD family 0Fh needs special treatment. 640 * While it wants to use ACPI, it does not 641 * comply with the ACPI specifications. 642 */ 643 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 644 645 if (rv != 0) 646 return rv; 647 648 for (i = 0; i < sc->sc_pstate_count; i++) { 649 650 ps = &sc->sc_pstate[i]; 651 652 if (__predict_false(ps->ps_freq == 0)) 653 continue; 654 655 fid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_FID); 656 vid = __SHIFTOUT(ps->ps_status, ACPI_0FH_STATUS_VID); 657 658 if (cfid == fid && cvid == vid) { 659 *freq = ps->ps_freq; 660 return 0; 661 } 662 } 663 664 return EIO; 665 } 666 667 static int 668 acpicpu_md_pstate_fidvid_set(struct acpicpu_pstate *ps) 669 { 670 const uint64_t ctrl = ps->ps_control; 671 uint32_t cfid, cvid, fid, i, irt; 672 uint32_t pll, vco_cfid, vco_fid; 673 uint32_t val, vid, vst; 674 int rv; 675 676 rv = acpicpu_md_pstate_fidvid_read(&cfid, &cvid); 677 678 if (rv != 0) 679 return rv; 680 681 fid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_FID); 682 vid = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VID); 683 irt = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_IRT); 684 vst = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_VST); 685 pll = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_PLL); 686 687 vst = vst * 20; 688 pll = pll * 1000 / 5; 689 irt = 10 * __BIT(irt); 690 691 /* 692 * Phase 1. 693 */ 694 while (cvid > vid) { 695 696 val = 1 << __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_MVS); 697 val = (val > cvid) ? 0 : cvid - val; 698 699 acpicpu_md_pstate_fidvid_write(cfid, val, 1, vst); 700 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 701 702 if (rv != 0) 703 return rv; 704 } 705 706 i = __SHIFTOUT(ctrl, ACPI_0FH_CONTROL_RVO); 707 708 for (; i > 0 && cvid > 0; --i) { 709 710 acpicpu_md_pstate_fidvid_write(cfid, cvid - 1, 1, vst); 711 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 712 713 if (rv != 0) 714 return rv; 715 } 716 717 /* 718 * Phase 2. 719 */ 720 if (cfid != fid) { 721 722 vco_fid = FID_TO_VCO_FID(fid); 723 vco_cfid = FID_TO_VCO_FID(cfid); 724 725 while (abs(vco_fid - vco_cfid) > 2) { 726 727 if (fid <= cfid) 728 val = cfid - 2; 729 else { 730 val = (cfid > 6) ? cfid + 2 : 731 FID_TO_VCO_FID(cfid) + 2; 732 } 733 734 acpicpu_md_pstate_fidvid_write(val, cvid, pll, irt); 735 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 736 737 if (rv != 0) 738 return rv; 739 740 vco_cfid = FID_TO_VCO_FID(cfid); 741 } 742 743 acpicpu_md_pstate_fidvid_write(fid, cvid, pll, irt); 744 rv = acpicpu_md_pstate_fidvid_read(&cfid, NULL); 745 746 if (rv != 0) 747 return rv; 748 } 749 750 /* 751 * Phase 3. 752 */ 753 if (cvid != vid) { 754 755 acpicpu_md_pstate_fidvid_write(cfid, vid, 1, vst); 756 rv = acpicpu_md_pstate_fidvid_read(NULL, &cvid); 757 758 if (rv != 0) 759 return rv; 760 } 761 762 if (cfid != fid || cvid != vid) 763 return EIO; 764 765 return 0; 766 } 767 768 static int 769 acpicpu_md_pstate_fidvid_read(uint32_t *cfid, uint32_t *cvid) 770 { 771 int i = ACPICPU_P_STATE_RETRY * 100; 772 uint64_t val; 773 774 do { 775 val = rdmsr(MSR_0FH_STATUS); 776 777 } while (__SHIFTOUT(val, MSR_0FH_STATUS_PENDING) != 0 && --i >= 0); 778 779 if (i == 0) 780 return EAGAIN; 781 782 if (cfid != NULL) 783 *cfid = __SHIFTOUT(val, MSR_0FH_STATUS_CFID); 784 785 if (cvid != NULL) 786 *cvid = __SHIFTOUT(val, MSR_0FH_STATUS_CVID); 787 788 return 0; 789 } 790 791 static void 792 acpicpu_md_pstate_fidvid_write(uint32_t fid, 793 uint32_t vid, uint32_t cnt, uint32_t tmo) 794 { 795 struct msr_rw_info msr; 796 uint64_t xc; 797 798 msr.msr_read = false; 799 msr.msr_type = MSR_0FH_CONTROL; 800 msr.msr_value = 0; 801 802 msr.msr_value |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID); 803 msr.msr_value |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID); 804 msr.msr_value |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT); 805 msr.msr_value |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG); 806 807 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 808 xc_wait(xc); 809 810 DELAY(tmo); 811 } 812 813 int 814 acpicpu_md_tstate_get(struct acpicpu_softc *sc, uint32_t *percent) 815 { 816 struct acpicpu_tstate *ts; 817 uint64_t val; 818 uint32_t i; 819 820 val = rdmsr(MSR_THERM_CONTROL); 821 822 for (i = 0; i < sc->sc_tstate_count; i++) { 823 824 ts = &sc->sc_tstate[i]; 825 826 if (ts->ts_percent == 0) 827 continue; 828 829 if (val == ts->ts_status) { 830 *percent = ts->ts_percent; 831 return 0; 832 } 833 } 834 835 return EIO; 836 } 837 838 int 839 acpicpu_md_tstate_set(struct acpicpu_tstate *ts) 840 { 841 struct msr_rw_info msr; 842 uint64_t xc; 843 int rv = 0; 844 845 msr.msr_read = true; 846 msr.msr_type = MSR_THERM_CONTROL; 847 msr.msr_value = ts->ts_control; 848 msr.msr_mask = __BITS(1, 4); 849 850 xc = xc_broadcast(0, (xcfunc_t)x86_msr_xcall, &msr, NULL); 851 xc_wait(xc); 852 853 if (ts->ts_status == 0) { 854 DELAY(ts->ts_latency); 855 return 0; 856 } 857 858 xc = xc_broadcast(0, (xcfunc_t)acpicpu_md_tstate_status, ts, &rv); 859 xc_wait(xc); 860 861 return rv; 862 } 863 864 static void 865 acpicpu_md_tstate_status(void *arg1, void *arg2) 866 { 867 struct acpicpu_tstate *ts = arg1; 868 uint64_t val; 869 int i; 870 871 for (i = val = 0; i < ACPICPU_T_STATE_RETRY; i++) { 872 873 val = rdmsr(MSR_THERM_CONTROL); 874 875 if (val == ts->ts_status) 876 return; 877 878 DELAY(ts->ts_latency); 879 } 880 881 *(uintptr_t *)arg2 = EAGAIN; 882 } 883 884 /* 885 * A kludge for backwards compatibility. 886 */ 887 static int 888 acpicpu_md_pstate_sysctl_init(void) 889 { 890 const struct sysctlnode *fnode, *mnode, *rnode; 891 const char *str; 892 int rv; 893 894 switch (cpu_vendor) { 895 896 case CPUVENDOR_IDT: 897 case CPUVENDOR_INTEL: 898 str = "est"; 899 break; 900 901 case CPUVENDOR_AMD: 902 str = "powernow"; 903 break; 904 905 default: 906 return ENODEV; 907 } 908 909 910 rv = sysctl_createv(&acpicpu_log, 0, NULL, &rnode, 911 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 912 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL); 913 914 if (rv != 0) 915 goto fail; 916 917 rv = sysctl_createv(&acpicpu_log, 0, &rnode, &mnode, 918 0, CTLTYPE_NODE, str, NULL, 919 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 920 921 if (rv != 0) 922 goto fail; 923 924 rv = sysctl_createv(&acpicpu_log, 0, &mnode, &fnode, 925 0, CTLTYPE_NODE, "frequency", NULL, 926 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL); 927 928 if (rv != 0) 929 goto fail; 930 931 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 932 CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL, 933 acpicpu_md_pstate_sysctl_set, 0, NULL, 0, CTL_CREATE, CTL_EOL); 934 935 if (rv != 0) 936 goto fail; 937 938 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 939 CTLFLAG_READONLY, CTLTYPE_INT, "current", NULL, 940 acpicpu_md_pstate_sysctl_get, 0, NULL, 0, CTL_CREATE, CTL_EOL); 941 942 if (rv != 0) 943 goto fail; 944 945 rv = sysctl_createv(&acpicpu_log, 0, &fnode, &rnode, 946 CTLFLAG_READONLY, CTLTYPE_STRING, "available", NULL, 947 acpicpu_md_pstate_sysctl_all, 0, NULL, 0, CTL_CREATE, CTL_EOL); 948 949 if (rv != 0) 950 goto fail; 951 952 return 0; 953 954 fail: 955 if (acpicpu_log != NULL) { 956 sysctl_teardown(&acpicpu_log); 957 acpicpu_log = NULL; 958 } 959 960 return rv; 961 } 962 963 static int 964 acpicpu_md_pstate_sysctl_get(SYSCTLFN_ARGS) 965 { 966 struct cpu_info *ci = curcpu(); 967 struct acpicpu_softc *sc; 968 struct sysctlnode node; 969 uint32_t freq; 970 int err; 971 972 sc = acpicpu_sc[ci->ci_acpiid]; 973 974 if (sc == NULL) 975 return ENXIO; 976 977 err = acpicpu_pstate_get(sc, &freq); 978 979 if (err != 0) 980 return err; 981 982 node = *rnode; 983 node.sysctl_data = &freq; 984 985 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 986 987 if (err != 0 || newp == NULL) 988 return err; 989 990 return 0; 991 } 992 993 static int 994 acpicpu_md_pstate_sysctl_set(SYSCTLFN_ARGS) 995 { 996 struct cpu_info *ci = curcpu(); 997 struct acpicpu_softc *sc; 998 struct sysctlnode node; 999 uint32_t freq; 1000 int err; 1001 1002 sc = acpicpu_sc[ci->ci_acpiid]; 1003 1004 if (sc == NULL) 1005 return ENXIO; 1006 1007 err = acpicpu_pstate_get(sc, &freq); 1008 1009 if (err != 0) 1010 return err; 1011 1012 node = *rnode; 1013 node.sysctl_data = &freq; 1014 1015 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1016 1017 if (err != 0 || newp == NULL) 1018 return err; 1019 1020 err = acpicpu_pstate_set(sc, freq); 1021 1022 if (err != 0) 1023 return err; 1024 1025 return 0; 1026 } 1027 1028 static int 1029 acpicpu_md_pstate_sysctl_all(SYSCTLFN_ARGS) 1030 { 1031 struct cpu_info *ci = curcpu(); 1032 struct acpicpu_softc *sc; 1033 struct sysctlnode node; 1034 char buf[1024]; 1035 size_t len; 1036 uint32_t i; 1037 int err; 1038 1039 sc = acpicpu_sc[ci->ci_acpiid]; 1040 1041 if (sc == NULL) 1042 return ENXIO; 1043 1044 (void)memset(&buf, 0, sizeof(buf)); 1045 1046 mutex_enter(&sc->sc_mtx); 1047 1048 for (len = 0, i = sc->sc_pstate_max; i < sc->sc_pstate_count; i++) { 1049 1050 if (sc->sc_pstate[i].ps_freq == 0) 1051 continue; 1052 1053 len += snprintf(buf + len, sizeof(buf) - len, "%u%s", 1054 sc->sc_pstate[i].ps_freq, 1055 i < (sc->sc_pstate_count - 1) ? " " : ""); 1056 } 1057 1058 mutex_exit(&sc->sc_mtx); 1059 1060 node = *rnode; 1061 node.sysctl_data = buf; 1062 1063 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 1064 1065 if (err != 0 || newp == NULL) 1066 return err; 1067 1068 return 0; 1069 } 1070 1071
Indexes created Tue Sep 30 20:09:53 GMT 2025